SU739735A1 - Functional analog-to-code converter - Google Patents

Description

one

The invention relates to computing, can be used in spectrum analyzers with logarithmic quantization of signals with a given absolute error in the whole range of their changes.

Functional converters analog code, in particular, logarithmic converters allow with a constant relative conversion error to effectively use the bit grid of code layers and replace the multiplication operation with the addition operation when applying a weight function to the process under study. However, with logarithmic quantization of signals, the absolute quantization error increases with an increase in the signal to be converted. In this connection, when receiving a signal, it is necessary to arrange the structure of the device so that the fine structure of its envelope can be estimated with a given absolute error when the input process is unequally quantized.

A known analog-to-code converter with an uneven distribution of quantization levels, comprising a comparison circuit, a saw-tooth voltage generator, a key, a pulse generator, a frequency divider with loop outputs, control valves, a control register and a coding counter 1. This device can be used in the technique; communications to encode speech signals and convert analog values to a functional binary code corresponding to a logarithmic compression characteristic.

Application in the known device of the principle of comparison of analog values with the value of the reference voltage in combination with the method of sequential counting

15 limits the speed and, accordingly, the class of processed signals. In addition, in this device, the absolute error of the conversion varies with the magnitude of the signal.

20

Claims (4)

The Analog-to-code converter is known, which contains two analog keys, a delay element, a subtraction unit, a comparators unit, a limiter amplifier, and an encoder. 37 switch, adder, converter, voltage, voltage reference block and synchronizer 2. The essence of the operation of this device is that the values of each analog signal sample are represented as fixed-code words, i.e. consist of a characteristic and manthiss. In this case, the meanings of the left and right parts of the codewords are formed sequentially by the same block of comparators. The known device allows generating a logarithmic binary code, i.e. it implements a conversion with a constant relative error of analog signals into codewords when the absolute conversion error changes. When analyzing the fine structure of the envelope of signals in a wide range of their changes, it is necessary to have a device that allows one to maintain the specified absolute error with non-uniform quantization of the input process. In this case, the advantages of logarithmic quantization would be realized in the course of the спектра1-spectrum analysis of signals and the loss of information would be excluded. The aim of the invention is to preserve the specified absolute conversion error with non-uniform quantization of the input process. The goal is achieved by the fact that in a known functional converter an analog-code containing a delay element, the input of which is connected to the converter input, and the first output of the delay element is connected to the first input of the subtractor, the second input of which is connected to the first input of the adder, the device and the first input of the switch, the first output of which is connected to the first input of the reference voltage block, the second input of the adder, the output of which is the first output of the converter, and through the converter Or code-voltage - with the third input of the subtraction unit, the output of which through the amplifier limiter is connected to the first input of the first analog switch, the second output of which is connected to the second input of the reference voltage block, to the first input of the synchronizer and to the second input of the switch, third which entrance is connected to the third entrance of the block. the reference voltages, to the second output of the synchronizer and to the first input of the second analog switch, the output of which is connected to the first input of the comparators unit, the second and third inputs of which are connected respectively to the outputs of the first analog switch and the reference voltage, and the output unit comp. The rators are connected to the input of the encoder, the second output of which is the second output of the converter, the analysis block and the digital generator are entered, the first input of the digital generator is connected to the fourth input of the reference voltage block and the output of the analysis block, the first input of which is the converter input and the second input is connected to the third output of the synchronizer, the fourth output of which is connected to the second input of the digital generator, the output of which is connected to the third input of the adder, and the second output of the element is the delay associated with the second input of the second analog switch. The essence of the invention is that the entire dynamic range of signal changes is divided into a number of subbands. Each subrange is matched with a logarithm scale with its own scale, so that the logarithm of the input signal, the level of which corresponds to this subband, has an absolute quantization error on the scale of the corresponding logarithmic scale that does not exceed the specified magnitude. The number of splits of the Dynamic range into subranges and the scale of each logarithmic scale is chosen based on the specified range and absolute accuracy, subject to minimization of hardware costs. In accordance with the selected scales, a set of reference voltages is produced separately for the characteristic and for the mantissa, and these voltages are chosen according to the scaling signal. The scaling signal indicates to which subdigence the quantized value of the input signal corresponds to. To obtain uniqueness of the code information, the code words are converted in accordance with the scale of the first Scale, for which the code is shifted by bit cells, which is equivalent to the transfer of a comma in the signal code. Pa drawing presents a functional diagram of the device. The analog converter has a delay element 1, the input of which is connected to the converter input, and the first output of the delay element 1 is connected to the first input of the subtraction unit 2. The second input of the subtraction unit is connected to the first input of the summatr 3, the first output of the encoder 4 and the first input of the switch 5. The first output of the switch is connected to the first input of the block 6 of reference voltages, the second input of the adder 3, the output of which is the first output through the converter 7 code-voltage - with the third input of the subtraction unit 2. The output of the subtraction unit through the amplifier-buncher 8 is connected to the first input of the analog Boro key 9, the second input of which is connected to the second input of the block 6 of the reference voltage, to the first input of the synchronizer 10 and to the second input of the switch 5. The third input of the switch 5 is connected to the third input block 6 of the reference voltage to the second output of the synchronizer 10 and to the first input of the analog switch 11, the output of which is connected to the first input of the comparators block 12, the second and third inputs of which are connected respectively to the outputs of the analog switch 9 and the block 6 o partial stresses. The output of the comparators block is connected to the input of the encoder 4, the second output of which is the second output of the device. The first input of the digital generator 13 is connected to the fourth input of the block 6 of the reference voltages and the C-output of the analysis block 14, the first input of which is the input of the conversion l. The second input of the analysis unit is connected to the third output of the synchronizer 10, the fourth output of which is connected to the second input of the digital generator 13, the output of which is soy, is dinane to the third input of the adder 3. The second output of the delay element 1 is connected with the second input of the analog switch 11. The operation of the proposed converter is as follows. The analyzed signal is fed to the input of the analysis unit 14 and to the input of the delay element 1. The analysis unit 14 determines which of the subbands into which the dynamic range of the input signal is divided belongs to the signal, and generates a scaling signal value supplied to the reference voltage block 6 and to the digital oscillator 13. In the reference voltage block, the corresponding the main set and p reference, the voltages applied to the input of the block of 12 comparators. The digital oscillator 13 is prepared by the scale signal to generate the number of pulses set to the value of the scale signal. The input signal delayed by the element 1 for the time determined by the time of formation of a set of reference voltages is fed to the inputs of the analog switch 11 and 2 subtraction. From the synchronizer outputs 10 and the inputs of the analog switches 9 and 11, respectively, the first and second pulses of the strobe-pulse pair are received. A sample from the output of the analog key 11 is fed to the input of the comparator block 12, in which they are compared with the values of the reference voltages and the subsequent formation of code words in the encoder 4. At the output of the encoder 4, which is the output of the converter, with a sign and a code of the characteristic, and also a sign. The signal. The value of the characteristic code through the switch 5 is written to the corresponding bits of the adder 3 and is fed to the inputs of the block 6 of the reference voltages} i of the code-voltage converter 7. The voltage value from the output of the converter 7 is supplied to the input of block 2 v1 Read. The differential value of the signal from the output of block 2 through the amplifier (limit 8), whose parameters are determined by the dynamic range of the signal changes, is fed to the input of the analog switch 9. The second input of the analog switch from the synchronizer output 10 receives the second of a pair of strobe pulses. The sampling value from the output of the analog switch 9 is fed to the input of the comparator unit 12, the reference voltages to which are supplied from the reference voltage block 6 and determined by the characteristic value and the scaling signal from the output of the analysis unit 14. Similarly to the above, the conversion takes place in block 12 of the comparators and in the encoder. 4. By the second strobe-pulse, the switch 5 is set to the position at which the 1-bit sample in binary code is written to the lower bits of the adder 3 as the mantissa. Thus, a logarithmic binary code is formed in the adder: with the scale corresponding to the given subband, taking into account the characters of the input signal and the characteristic. The ratios between the Scales of the respective subranges are chosen so that the codes of the same value for different scales differ only in the position of the comma separating the characteristic or the mantissa. Therefore, to obtain the output code in an equivalent scale, the synchronizer signal 10 digital generator 13 supplies the third input of the adder 3 with the number of shift pulses corresponding to the scaling signal. In this case, the code shifts in the adder 3, which is equivalent to the transfer of a comma in the logarithm code. This shows that at the output of the converter, a binary logarithmic code of the signal at the equivalent scale taking into account the sign of the signal and the characteristic is formed. A command is formed at the output of the encoder 4 in the event that none of the comparators have triggered, i.e. the input signal is identified with zero. Note the requirements for the choice of converter parameters and their interrelationships. Denote: - the number of comparators in block 12; .cL reduced dynamic range of the input signal; and - reference voltage; taKcliyUpl U is required absolute error ofOHOCTbJ - OUTPUT code of magnitude The dynamic range is divided into subbands of E, E, ... E, Shchtem-E, .. such that if the signal Uftx belongs to the -th sub-band, then 6 , E. each subband selects its own binary code x, where 0 is VK and because o and 2IDc V K, then the conversion from the code number V to the code is carried out by simply moving the comma to the left, to / positions. The scale of voltage V for each subrange is selected so as to satisfy the requirements of absolute accuracy, and the values of the reference voltage to determine the characteristics and mantissa are respectively: i..l) 0 op) -% 1k) cr 7 ok-1 a) Based on the absolute requirements, it can be shown accurately that for each sub-band .1S g. Denote: m jUK S tS K O K i, Z, ..., tl. The minimum required number of comparators to characterize each sub-band is whereE; {; 1 is the integral part of the number. At the same time, p max P, preferably V, in order to reduce the redundancy of compilers during the coding step of the characteristic Number t. and the coefficients a are chosen taking into account the requirement for minimization of hardware costs, i.e. minimizing the number of comparators n ,. For example, for the p-and Sj, 2L6 0,2 :) a, Q, .a-i; Q a-o-g .. P ,, - ai .2b. Thus, the greatest excess of comparators at the stage of the formation of the characteristic code is Moksp-R 15. Note that for p. When constructing the ADC for the given values of D and SQ in the prototype, 710 comparators would have to be used, i.e. more than 27 times more than in the proposed converter, and at the stage of generating the characteristic code no more than 9 comparators would be used. Thus, this functional analog-code converter provides the specified absolute conversion accuracy with logarithmic analog-to-digital conversion and significantly lower hardware costs. A functional analogue code converter comprising a delay element, the input of which is connected to the converter input, and the first output of the delay element is connected to the first input of the subtractor, the second input of which is connected to the first input of the adder, and to the first input of the switch, the first output of which is connected to the first input of the reference voltage block, to the second input of the adder, the output of which is the first output of the converter, and through the code-voltage converter - to the third input of the subtraction unit, the output of which is connected via an amplifier-limiter to the first input of the first analog switch, the second input of which is connected to the second input of the reference voltage block, to the first input of the synchronizer and to the second input of the switch 1, the third input connected to the third input of the voltage reference block, to the second output of the synchronizer and to the first input of the second analog switch, the output of which is connected to the first input of the comparators block, the second and Vpetia inputs of which are connected respectively to you the strokes of the first analog key and the reference voltage block, and the comparators block is connected to the input of the encoder, the second output of which is the second output of the converter, characterized in that, in order to preserve the specified absolute conversion error with non-uniform quantization of the input process, a block is entered into it analysis and digital generator,