JPH036921A - Method of converting digital signal composed of data word into pulse-width modulated analog signal and digital/analog converter - Google Patents

Abstract

PURPOSE: To set the timewise resolution of an analog signal larger than resolution determined by clock period time by leading a bit-reduced data word from which at least only lower bits 2 deg. are cut out to the data input side of a previously controllable binary counter and determining the delay time of a counter carry pulse by the lower bits. CONSTITUTION: A data word from which only two lower bits are reduced is led into the data input side of the previously controllable binary up counter 1. An RS flip flop(FF) 2 is set by a counter set pulse Load, the data word is temporarily stored in the counter 1 and then a counting process is started by an enable signal for a clock signal Clock. The two lower bits for determining delay time are led to the control input side of a data selector 3, one of four outputs from a delay element 4 is selected in accordance with the contents of led data and a transfer pulse RC from the counter 1 for resetting the FF 2 is delayed based on a rule.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The invention relates to a digital signal consisting of data words, such as a PC
The present invention relates to a method for converting an M signal into a pulse width modulated analog signal by using a clocked digital-to-analog converter.

PRIOR ART The following methods are most well known for converting pulse-coded signals into analog signals: In a frequently used method, a digital input signal is used to actuate a switch, which This creates a defined connection path in the resistor-conductor network, so that a voltage or current value corresponding to the input word in digital form can be produced at the network output connection. However, this method requires a narrow tolerance class of the resistors used, thereby trying to avoid loss of accuracy in the D/A converter.

In another, more frequently used method, a pulse width modulator (PWM) is used as a preadjustable binary counter connected to an R8' flip-flop, integrating the pulse width modulated signal. At the output, an analog DC voltage value corresponding to the digital input word is then generated. This D/A converter is much slower than the previously described D/A converters and can only process a limited amount of data based on its maximum clock frequency.

Problem to be Solved by the Invention The problem to be solved by the invention is therefore to provide a method of the type mentioned at the outset.
The object of the present invention is to improve the temporal resolution of the analog signal so that it is greater than the resolution determined by the clock period time of the clock pulse clocking the digital/analog converter.

Means for solving the problem This problem consists in providing a preadjustable binary counter with a reduced number of bits (cut only to the least significant bit 2a, preferably only to bits 20 and 2) on the data input side of the preadjustable binary counter. The data word is guided, and the RS flip-flop is set by the counter set pulse and reset by the counter carry pulse, where the counter carry pulse is guided to the RS flip-flop with a delay, the delay time being The solution is that the unit time corresponding to bit 20 is determined by the lower bits, and that the unit time corresponding to bit 20 is multiplied by the value of the data word consisting of the lower bits or the lower bits.

In other words, the determination of the total pulse width is carried out in two steps. The portion of the pulse width that corresponds to an integral multiple of the clock period time is determined simply by evaluating the upper bits of the incoming data word. On the other hand, the portion of the pulse width corresponding to a fraction of the clock cycle time is determined by a stepped delay time. The total pulse width then results from the sum of both parts.

The invention furthermore relates to a digital/analog converter according to the preamble of claim 2.

In this regard, the object of the invention is to provide a digital/analog converter of the type mentioned at the outset with a temporal resolution of the analog signal that is greater than the resolution determined by the clock period time of the clock pulses clocking the digital/analog converter. The goal is to improve so that it grows.

The problem is that a pre-adjustable binary counter, an RS flip-flop, a delay element and a data selector are provided, into which a data word is led, and at the input of said pre-adjustable binary counter. so that a reduced data word with fewer bits (both lower bits 20, preferably bits 20 and 21 cut off) is introduced; furthermore, said counter is clocked by a clock signal, and said RS flip-flop is clocked by a clock signal. The counter carry pulse is settable by a counter set pulse and resettable by a counter carry pulse, with the counter carry pulse being guided to the RS flip-flop via a delay element and a data selector; The output side is selected by a data selector in such a way that the delay time is determined by the low-order bit or bits, in which the unit time corresponding to bit 20 consists of the low-order bits. This problem is solved by multiplying by the value of the data word.

Advantageous embodiments of the method and of the analog/digital converter according to the invention emerge from the claims, the following description and the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the circuit shown in FIG. 1, a complete data word is led to the data input of a preadjustable binary up-counter 1. In the circuit shown in FIG. The counter set pulse sets the RS flip-flop 2 and the data word is intermediately stored in the counter 1. The counting process is then started by an enable signal to the clock signal. When the transfer pulse RC appears at the counter output, the RS flip-flop 2 is reset again, so that at the output of the RS flip-flop 2 a pulse-width modulated signal corresponding to the data word is generated.

The counting process is then interrupted by removing the enable signal for the clock signal and the counter 5 is reset, after which the next data word is introduced at the data input and the conversion cycle is started anew.

FIG. 3 is a pulse diagram of the circuit shown in FIG. The first column shows the clock pulse signal that clocks the binary counter 5, and the second to 177th columns show the 4-bit data word that will arrive at the input of the counter 5. The output signal of the RS flip-flop 2 is shown for 16 possible platings. Data word values are shown on the right side of the figure as binary and decimal numbers. The output signal of the RS flip-flop 2 represents a pulse width modulated signal in analog form.

As shown in the figure, the possible resolution of the pulse width of the analog signal is determined by the period time of the clock signal.

In the case of the circuit shown in FIG. 2, the data word with its lower bits reduced by two digits is led to the data input of a preadjustable binary up counter 1, which has two Requires less data entry. The counter set pulse LOAD likewise sets the RS flip-flop 2 and the data word is intermediately stored in the counter 1, and then the counting process is started by means of an enable signal for the clock signal C1ock. In this case, the transfer pulse RC appears earlier. Because counter 1
This is because two fewer binary digits need to be processed. In order to obtain a complete pulse width corresponding to a complete data word, the transfer pulse RC of the counter 1 which resets the RS flip-flop 2 is delayed in a defined manner, in this case:
The two lower bits determining the delay time are led to the control input of the data selector 3, which selects one of the four outputs of the delay element 4 depending on the data content and also resets the flip-flop 2. Connected to the input side. A reset pulse R8 is applied to each output side of the delay element 4.
appears with a delay of equal length unit time each time,
The sum of these unit times then amounts to one complete locking signal period.

FIG. 4 shows a pulse diagram of the circuit shown in FIG. The first column shows the clock signal C1ock that clocks the binary counter 1, and the second to 177th columns show the 4-bit data word that will arrive at the input side of the circuit. The output signal of the RS flip-flop 2 is shown for 16 possible platings. The output signal of the RS flip-flop 1, whose data word values are shown as binary and decimal numbers on the right side of the drawing, represents a pulse width modulated signal in analog form.

In this case, the clock signal in the first column has a period time that is longer by a factor of 4. This results in the data word value 014.8.
All pulse widths corresponding to 12 and 16 can be produced. The intermediate value is 1 of the period time of the clock signal.
/4.Produced by delaying the counter carry pulse RC by 1/2 or 3/4.

If the resolution is not to be increased over the circuit according to FIG. 1, but merely to be the same, then a clock frequency that is reduced by a factor of 4 will suffice. This may be advantageous when using components that, due to their limited frequencies, cannot be operated at a clock frequency corresponding to the desired resolution.

Note that advantageous configurations according to the present invention are summarized below.

According to the invention, the delay element 4 is constructed by a series connection of a delay network of LC elements, said delay network being constructed using gyrator technology.

7 Effects of the Invention The present invention provides a method for converting a digital signal into an analog signal, in which the temporal resolution of the analog signal is greater than the resolution determined by the clock cycle time of the clock pulse that clocks the digital/analog converter. A method and an analog-to-digital converter are provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a known digital/analog converter, FIG. 2 is a block diagram of a digital/analog converter according to the present invention, FIG. 3 is a time chart of the circuit according to FIG. 2 shows a time chart diagram of the circuit according to FIG. 1... Binary counter, 2... RSS flip-flop 3... Data selector, 4... Delay element Fig,
1 Fig, 2

Claims (1)

Claims: 1. A method for converting a digital signal consisting of data words into a pulse width modulated analog signal by using a clocked digital-to-analog converter, comprising: a data input of a preadjustable binary counter; On the side, a bit-compressed data word with at least the lower bits 2^0 cut off is introduced, and the RS flip-flop is set by the counter set pulse (Load) and reset by the counter carry pulse (RC). In this case, the counter carry pulse (RC) is guided to the RS flip-flop with a delay, the delay time being determined by the lower bit, where the unit time corresponding to bit 2^0 is A method for converting a digital signal consisting of a data word into a pulse width modulated analog signal, characterized in that the signal is multiplied by the value of the data word consisting of the lower bits. 2. In a digital-to-analog converter for converting a digital signal consisting of data words into a pulse-width modulated analog signal, a preadjustable binary counter (1), an RS flip-flop (2), a delay element (4) ), and a data selector (3) to which a data word is led, at least the lower bit 2^0 being input to the input of said preadjustable binary counter (1). A compressed data word of bits is derived which has been cut by Clock.
), and the RS flip-flop (2) can be set by a counter set pulse (Load) and reset by a counter carry pulse (RC), in which case the counter carry pulse (RC) is guided to the RS flip-flop (2) via a delay element (4) and a data selector (3), and the output side of the delay element (4) is connected such that the delay time is determined by the lower bits. and data selector (3)
0), then within the data selector,
A digital signal for converting a digital signal consisting of a data word into a pulse width modulated analog signal, characterized in that a unit time corresponding to bit 2^0 is multiplied by the value of the data word consisting of lower bits. /Analog converter.