JP3407851B2 - Delta-sigma D / A converter with PWM circuit / weighting circuit combination - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter for converting a multi-bit modulated digital signal obtained from a delta-sigma type modulation circuit into an analog signal. In particular, the present invention relates to a D / A converter in which a weighting circuit and a PWM circuit are used in combination to perform weighting in a voltage or current level direction and a time axis direction. 2. Description of the Related Art A D / A converter of a weighted circuit type has a 2 n
When converting a digital signal weighted to the power to an analog signal, prepare a voltage source or current source corresponding to the weight of each bit of the digital signal, and control those voltage source or current source signals with digital input signals Then, a desired analog signal is obtained. FIG. 4 is a diagram showing a schematic configuration of the D / A converter of the weighted circuit type. A digital signal input to a digital input signal terminal 51 causes a switch control circuit 52 to operate.
Are controlled, and the switches 5311 to 531 of the resistor group 53 are controlled.
n is on / off controlled, and the resistance elements 5321 to 532n
Is applied with a voltage Vrefb. This resistance element 532
1 to 532n are set to have a resistance value of R to 2 ^n-1 × R. Voltages generated by currents flowing through the resistance elements 5321 to 532n are added by an adder 54 including an operational amplifier 541 and a feedback resistor 542, and output to an analog signal output terminal 55. However, the D / A conversion circuit of the weighting circuit type has a problem that a highly accurate analog circuit is required for a circuit (the resistor group 53 in FIG. 4) for performing weighting according to the number of bits of a digital signal. is there. In the case of the D / A conversion circuit shown in FIG. 4, the resistance ratio accuracy is required to be 0.2% for 8 bits, 0.05% for 10 bits, and 0.0125% for 12 bits. When the range is 8 bits, the difference between the minimum resistance value and the maximum resistance value is 128 times, that is, 512 times for 10 bits, and 2048 times for 12 bits, which requires a high specific accuracy and a wide resistance value range. On the other hand, in recent years, digital
There is a delta-sigma modulation type D / A converter used as a D / A converter for audio. The feature of this delta sigma modulation type D / A converter is that extremely high oversampling is performed, digital data is converted into time information, and 1-bit D / A conversion (reference voltage is turned on / off by time information). ) To convert the data into a pulse width, and then average the data with an analog filter. [0006] An analog converter for a 1-bit modulated digital signal can be realized very easily, and since it is a 1-bit signal, there is no problem in principle such as relative accuracy. FIG. 5 shows the configuration of the delta-sigma modulation type D / A converter. The digital signal input to the digital input terminal 61 is input to the interpolation filter 6.
After being oversampled by 2 to increase the sampling frequency, it is applied to the delta-sigma modulation circuit 63. The delta-sigma modulation circuit 63 is of a double integration type, and includes adders 631, 632,
33, 634, requantizer 635, 1 timing delay 636, sign inverters 637, 6 forming a negative feedback loop
38. The requantizer 635 includes a plurality of comparators 6351 to 635 to which different reference voltages are set.
n. The output of the delta-sigma modulation circuit 63 is P
The pulse width modulation is applied to the WM circuit 64 and the PW
The M output is filtered by an analog filter circuit 65 and appears at an output terminal 66 as an analog output signal. In the PWM circuit 64, when all the LSB to MSB of the multi-bit output of the requantizer 635 are 0, a pulse (width of 1) corresponding to one central clock width rises, and only the LSB is 1 and the others are 1. When it is 0, a pulse corresponding to the central three clock widths (the total width of LSB, 1 and LSB) rises,.
When all of SB to MSB are 1, pulses corresponding to the maximum clock width (pulse width including the MSBs on both sides) stand. Here, assuming that the input signal of the delta-sigma modulation circuit 63 is X, the output of the delta-sigma modulation circuit 63 is represented by Y = X + (1−Z ⁻¹ ) ² · Q. Here, Q is quantization noise generated when requantization is performed by the requantizer 635. (1−Z ⁻¹ ) indicates differentiation, and the configuration example in FIG. 5 indicates that second order differentiation is applied. The frequency characteristic of the derivative is -∞ at DC, and the higher the frequency, the higher the gain. Therefore, as described in FIG. 6 for noise shaping, the signal component X remains unchanged and the noise Q shifts to a higher frequency. After this signal is subjected to pulse width modulation by the PWM circuit 64, a high-frequency noise component is removed by the analog low-pass filter 65, and a desired analog signal can be obtained. [0010] In addition to the above, the operation principle and characteristics of the delta-sigma modulation type D / A converter are described in "Transistor Technology Special No. 16 Special Edition A / D / D".
-A conversion circuit technology "(QC Publishing), pp. 24-2
You can find out on page 5. [0011] The quantization resolution of the requantizer used in the delta-sigma modulation circuit is n, the oversampling rate (the ratio of the frequency twice as high as the signal band to the sampling frequency) is m,
Assuming that the order of the derivative is k, the delta-sigma modulation type D / A
The S / N realized by the converter is: S / N (dB) = (6k + 3) log ₂ m− (8k−4) +
20 log ₁₀ (n-1). When k = 2 and n = 2, 8 bits (49.92 dB), 10 bits (61.96 dB),
The oversampling rates when trying to obtain 12-bit (74 dB) precision are 18 times, 31 times, and 5 times, respectively.
The value is three times as large. Therefore, generally, an increase in the oversampling rate is suppressed by setting the requantization resolution to multiple values. Also, by making the requantization resolution multi-valued, it is possible to prevent oscillation from occurring in the loop of the delta-sigma modulation circuit. When the requantizer has one bit, the D / A converter is the simplest. When the output of the quantizer is "H" (high level voltage), Send a signal,
At the time of "L" (low-level voltage), no signal should be sent. However, when the requantizer has a multi-bit output, a PWM that changes the pulse width according to the output quantization level is required as shown in FIG. FIG. 7 shows a case where the output of the quantizer is 3 bits (8 gradations), but an operation of returning both ends of the pulse signal to the “L” level is essential. This is because any of the output waveforms includes rising and falling edges. If this operation is not performed, the output will be distorted due to the mismatch between the rising and falling waveforms, and the S / N will be degraded. Therefore, 16 clocks are required to output one data, and when an output signal is obtained using PWM, a clock 16 times the oversampling frequency is required. Of course, when increasing the resolution of the quantizer, a higher-speed clock is required. Therefore, there is a configuration using a switched capacitor (SC) integrator as a D / A converter that does not require a high-speed clock and has a relatively small circuit scale.
Since the accuracy of this SC integrator is determined by the capacitance ratio accuracy,
A highly accurate D / A converter can be configured relatively easily. However, the timing clock for charging and pumping the capacity of the SC integrator requires complicated clock control that does not overlap each other, and a high-precision timing clock generation circuit is required to realize high-speed operation. Is necessary. An object of the present invention is to provide a delta-sigma modulation type D
In the / A conversion device, as a device for converting a multi-bit modulated digital signal subjected to delta sigma modulation into an analog signal, a D / A conversion of a PWM circuit / weighting circuit combination type is performed.
It is an object of the present invention to alleviate the clock speed required for the operation and to perform highly accurate D / A conversion without using a complicated multi-phase clock. According to the present invention, there is provided a D / A converter for converting a multi-bit modulated digital signal from a delta-sigma type modulation circuit into an analog signal. , A weight conversion circuit, a PWM circuit, and a weight circuit. The weight conversion circuit decomposes the modulated digital signal into a plurality of signals.
The circuit corresponds to the plurality of signals and rises and falls.
To generate a plurality of PWM signals having, in which so as to obtain given the different voltage or current amplitude the pulse width portion of each of the PWM signal in the multiplex circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] In a D / A conversion by a weighting circuit, a voltage source (or current source) weighted according to an input signal as described with reference to FIG. Are selected and added to obtain a desired signal. However, n voltage sources (or current sources) are required for an n-bit input signal. This weighting circuit
Weighting is performed in the voltage (or current) axis direction. On the other hand, the PWM circuit develops data weights in the time axis direction and outputs a unit amount of voltage (or current) for a time corresponding to the weights. Time resolution of bits is required. In the first embodiment, a weighting circuit for weighting in the voltage axis direction and a PWM circuit for weighting in the time axis direction are used together to perform weighting in both the voltage axis and the time axis. , D /
A conversion device. FIG. 1 shows a D / A according to a first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a conversion device. The modulation digital signal X input from the delta-sigma modulation circuit to the input terminal 11 is first subjected to weight conversion processing in the weight conversion circuit 12. In FIG. 1, for the sake of simplicity, the input digital signal is assumed to be weighted to seven levels of 0, 1,... The weighting conversion circuit 12 can be composed of, for example, a conversion table, and the input digital signal is 0 (= 00).
0000), a signal of switches S11 = OFF, S12 = OFF, S13 = ON is output as a switch control signal S1, and a signal of switches S21 = OFF, S22 = OFF, S23 = ON is output as a switch control signal S2. I do. If the input digital signal is 1, 2, 3,
・ When the number is 6, it is as shown in the table. Reference numeral 13 denotes a PWM circuit, which includes switches S11 to S11 controlled by the switch control signal S1.
13, a first PWM unit 131 for selecting a pulse width (TW1 = + 1, 0, -1), and a switch control signal S2.
PW selecting pulse width (TW2 = + 1, 0, -1) by switches S21 to S23 controlled by
M section 132. Thus, in FIG. 1, in order to realize weights from 0 to 6, the weights in the time axis direction are decomposed into TW1 and TW2, which are further divided into “0, +”, respectively.
1, -1 ". A weighting circuit 14 is composed of VW1, ie, a first voltage generator 141 having a weight of “1”, and VW2, ie, a second voltage generator 142 having a weight of “2”. The first voltage generation section 141 selects and outputs the voltage Vsig when the output signal of the first PWM section 131 is “H”,
When it is "L", it has a switch 1411 for selecting and outputting the voltage Vref and a resistor 1412 for addition. Also, the second
Of the second PWM unit 132
Is "H", the voltage 2Vsig (Vsig 2
Voltage), and when "L", the voltage Vre
It has a switch 1421 for selecting and outputting f and a resistor 1422 for addition. As described above, the VW1 receiving TW1 is weighted with “1”, and the VW2 receiving TW2 is weighted with “2”. Reference numeral 15 denotes a voltage adder comprising an operational amplifier 151 to which a reference voltage Vrefa is set and a feedback resistor 152. The voltage adder 15 includes an output voltage of the first voltage generator 141 of the weighting circuit 14 and a second voltage generator. The output voltage of the section 142 is added and sent to the output terminal 16. As described above, the weighting TW1,
Depending on the combination of TW2, VW1, and VW2, the weight is-
3 / -2 / -1 / 0 / + 1 / + 2 / + 3. That is, the modulated digital signal input to the input terminal 11 is converted as follows and output from the output terminal 16. 0 → Select S13, S23 → Output −31 → Select S12, S23 → Output −22 → Select S13, S22 → Output −13 → Select S12, S22 → Output 04 → Select S11, S22 → Output +15 → S12, S21 selection → output + 26 → S11, S21 selection → output + 3 As described above, the configuration of the first embodiment is as follows.
The digital signal X input from the delta-sigma modulation circuit to the input terminal 11 is decomposed into a weight in the time axis direction (TW) and a weight in the voltage axis direction (VW), and weighting is performed for each of them. That is, the weighting conversion circuit 12 converts the input digital signal X into “2 ⁰ × a”, “2 ¹ × a”,.
・ Convert to “2 ⁿ × a” (where a is an arbitrary number)
The M circuit 13 weights a in the time axis direction, and the weighting circuit 14 weights 2 ⁿ voltages. As described above, by using the apparatus according to the present embodiment, the number of necessary weighting stages of the weighting circuit can be reduced, and the relative accuracy of the elements and the constant voltage source / constant current source can be easily secured. Also, even if the accuracy is compensated for by trimming or the like,
Since the number of trimming portions is small, it can be realized more easily than the conventional configuration. Further, the clock operation speed required for realizing PWM can be reduced as compared with the PWM method. [Second Embodiment] FIG. 2 shows an interpolation filter circuit 1 connected to a digital signal input terminal 17.
8 is connected, and a delta-sigma modulation circuit 19 is connected to the subsequent stage, and the output is connected to the weight conversion circuit 12 shown in FIG.
Connected to. FIG. 2 is more generalized than FIG. Here, the digital signal input to the digital input terminal 17 is oversampled by the interpolation filter circuit 18, the oversampled signal is delta-sigma modulated by the delta-sigma modulation circuit 19, and the delta-sigma modulated signal is The weighting conversion circuit 12 converts the signal into a combination signal of the weight a in the time direction and the voltage weight b (a value indicated by 2 ⁿ ),
The signal is converted by the M circuit 13 into a pulse width signal corresponding to the weight a in the time direction, and the weighting circuit 14
, A voltage having a voltage value corresponding to the voltage weight b is generated, and the voltage is added by the voltage adding circuit 15. [Third Embodiment] FIG. 3 replaces the weighting circuit 14 of the embodiment shown in FIG. 2 with a current-type weighting circuit 14 'and similarly replaces the voltage adding circuit 15 with the current adding circuit 15. '. Here, the digital signal input to the digital input terminal 17 is oversampled by the interpolation filter circuit 18, the oversampled signal is delta-sigma modulated by the delta-sigma modulation circuit 19, and the delta-sigma modulated signal is The weighting conversion circuit 12 converts the signal into a combination signal of the weight a in the time direction and the voltage weight k, and the PWM circuit 13 converts the signal into a pulse width signal corresponding to the weight a in the time direction. Current weight b
Is generated, and the current is added by the current adding circuit 15 '. As described above, according to the present invention, it is possible to reduce the clock frequency for PWM, which is a problem when converting a multi-bit modulated digital signal from a delta-sigma modulation circuit into an analog signal. There is an advantage that a highly accurate D / A conversion circuit can be realized without requiring a complicated multi-phase clock.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a main part of a configuration of a delta-sigma type D / A converter using a PWM circuit / weighting circuit in combination according to a first embodiment of the present invention. FIG. 2 is an overall block diagram of a configuration of a delta-sigma D / A converter using a PWM circuit / weighting circuit in combination according to a second embodiment; FIG. 3 is an overall block diagram of a configuration of a delta-sigma type D / A converter using a PWM circuit / weighting circuit in combination according to a third embodiment; FIG. 4 is a circuit diagram of a configuration of a general weighted circuit type D / A converter. FIG. 5 is a block diagram of a configuration of a general delta-sigma modulation type D / A converter. FIG. 6 is an explanatory diagram of delta-sigma modulation type noise shaping. FIG. 7 is a diagram illustrating an output waveform of a 3-bit PWM circuit. [Description of Signs] 11: Modulated digital signal input terminal, 12: Weight conversion circuit, 13: PWM circuit, 14: Weighting circuit, 15: Voltage addition circuit, 16: Output terminal, 17: Digital signal input terminal, 18: Inter Poration filter, 19: delta-sigma modulation circuit.

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 3/02 H03K 7/08 H03M 1/66 H03M 7/32

Claims (1)

(1) A D / A converter for converting a multi-bit modulated digital signal from a delta-sigma type modulation circuit into an analog signal, comprising: a weighting conversion circuit; and a PWM circuit. And a weighting circuit, wherein the weighted conversion circuit decomposes the modulated digital signal into a plurality of signals, and the PWM circuit generates a plurality of PWM signals corresponding to the plurality of signals and having rising and falling edges. , pa respective PWM signal in the multiplexing circuit
PWM circuit / weighting circuit combined type delta-sigma A / D converter, wherein the a given el this <br/> different voltage or current amplitude with respect to pulse width portion.