JP3336576B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter of a noise shaping type using a D / A converter for feedback, and more particularly to a technique for suppressing a deterioration in accuracy due to a latch error of the D / A converter for feedback. It is about.

[0002]

2. Description of the Related Art A / D of a conventional noise shaping system
The converter is based on the paper "" A Unity Bit Coding Method by Neg
ative Feedback. "Proc.IEEE, Vol.51, pp.1524-1535, Nov
ember1963. " FIG. 6 shows a signal system diagram of the A / D converter. Reference numeral 51 denotes an input terminal of the analog signal X; 52, a loop filter having a transfer function of Hf; 53, a quantizer having a transfer function in which quantization noise Eq is superimposed on an input signal and output; An encoder for converting the output signal of the converter 53 into a binary code; 55, a feedback D / A converter; 56, an analog subtractor for subtracting the input signal X from the output signal of the feedback D / A converter 55; Output terminal for digital signal Y.

Here, the feedback D / A converter 55 includes a latch circuit 551 for latching input data and delaying it by one sample time, and a D / A converter 552 for converting the latched data into an analog signal. Be composed. This D /
As the A conversion circuit 552, a load network or a switched capacitor circuit is generally applied.

[0004] The circuit connection relationship includes an input signal X and a feedback D /
An analog subtractor 56 subtracts the signal fed back from the A conversion unit 55, and the subtraction result (difference) is input to the loop filter 52.
Is input to a quantizer 53, the output of the quantizer 53 is input to an encoder 54 and a feedback D / A conversion circuit 55, and the output signal of the encoder 54 is input to the A / D converter 50.
It is connected so that it may become the output of.

The transfer function of the A / D converter shown in FIG. 6 is expressed as follows: Y = [Hf / (Hf · z ⁻¹ +1)] · [X + (1 / Hf) · Eq] (1) Is done. The encoder 54 outputs the output of the quantizer 53 to 2
The transfer function is 1 because it is only converted to a binary code.

Assuming that the input signal X is a sine wave, the quantization noise Eq is white noise. Therefore, only the quantization noise Eq becomes a spectrum shaped by the characteristics of the loop filter 52 from the equation (1). In general, the loop filter 52 in this configuration may be a low-pass type. For example, in the case of a loop filter having a simple integration characteristic, its transfer function Hf is as shown in the following equation (2). Hf = 1 / (1-z ^-1 ) (2) In this case, the above equation (1) is transformed into Y = X + (1-z ^-1 ) Eq (3) The frequency characteristics of the output signal are as shown in FIG.

At this time, if the quantizer 53 performs oversampling at a frequency Fs which is sufficiently faster than twice the bandwidth (Fb) of the input signal X, quantization in the low frequency region by shaping is performed. Due to the noise suppression effect, the quantization noise in the signal band is reduced, and a highly accurate A / D conversion characteristic can be obtained.

On the other hand, a PWM type D using a pulse width modulation method (PWM) described in Japanese Patent Application No. 62-6186.
The / A converter outputs a waveform signal whose pulse width is modulated according to the digital value of the input signal, as shown in FIG. FIG. 8 shows an example of a conversion operation waveform of 2-bit PWM D / A conversion. FIG. 9 shows this 2-bit PWM type D /
FIG. 3 is a circuit diagram showing a configuration of an A conversion circuit. A 2-bit digital input signal is taken into a decoder 62 from an input terminal 61, and the output of the decoder 62 is output to four DFF circuits 63.
1 of the parallel / serial conversion circuit 63
The signal is taken into the FF circuit, converted into a serial signal, and converted into a PWM waveform as shown in FIG.
To the output terminal 65. 66 is a clock input terminal and 67 is a preset control input terminal. Note that PD of the DFF circuit 631 is a preset data input terminal, D is a data input terminal, C is a clock input terminal, PR
Is a preset control input terminal, and Q is a data output terminal.

When the PWM type D / A conversion circuit shown in FIG. 9 is applied to an A / D converter having a first-order noise shaping order, the signal system diagram becomes as shown in FIG. Reference numeral 60 in FIG. 10 is a PWM type D / A converter. Since the DFF circuit 631 has a delay function,
This PWM type D / A converter 60 has the same function as the latch circuit 551 shown in FIG. PWM type D / A converter 6
The output signal from 0 is a PWM waveform as shown in FIG. 8. When the signal of the PWM waveform is at a high level, the loop filter 52 is supplied with electric charge from a power supply VDD (not shown), Sometimes that charge is extracted. Therefore, the supply amount of the charge to the loop filter 52 within one conversion time differs depending on the pulse width, and the resistor R2 (having a value of 2R) connected to the output side of the PWM type D / A converter 60 has the charge amount. The moving amount is converted into a voltage. From the above,
The A / D converter shown in FIG. 10 performs the same conversion operation as the A / D converter shown in FIG. In this case, the analog subtractor 56 shown in FIG. 6 is constituted by the resistors R1 (value is R) and R2.

The quantizer 53 generally has a voltage comparator group 6 comprising a reference voltage generating circuit 68 for generating a reference voltage and a plurality of voltage comparators 691, as shown in FIG.
9. 70 is an analog signal input terminal, 7
1 is a digital signal output terminal. FIG. 12 is a diagram showing a specific circuit configuration when the quantizer 53 is of a 2-bit type. When a 2-bit quantizer is used for the noise-shaping A / D converter, the minimum output voltage of the loop filter 52 is Vmin, and the maximum voltage is V.
Assuming that max, the reference voltages V1, V2, and V3 to be set by the reference voltage generation circuit 68 are as follows: V1 = (Vmax-Vmin) / 6 V2 = 3 (Vmax-Vmin) / 6 V3 = 5 (Vmax-Vmin) / 6.

[0011] In the A / D converter noise shaping method, the comparator 691 in order comparator group 69 Ru FIG speed of the quantizer, that of the positive feedback type as shown in FIG. 13 Is used. In FIG. 13, MP1 to PM3 are p
MOS transistors, MN1 to MN3 are nMOS transistors, 72 and 73 are transmission gates, 74
, An output buffer; 75, a reference voltage terminal to which a reference voltage Vref is applied; 76, an input terminal to which an input signal Vin is applied;
7 is an output terminal, 78 is a control terminal to which the clock φ1 is applied, 79 is a control terminal to which the inverted clock φ1n of the clock φ1 is applied, 80 and 81 are control terminals to which the clock φ2 is applied, and 82 and 83 are inverted clocks of the clock φ2. φ2n
Is a control terminal to be applied.

[0012]

However, in the positive feedback type comparator 691, as shown in FIG. 14, the difference between the voltage Va corresponding to the reference voltage Vref and the voltage Vb corresponding to the input voltage Vin is small. The more it becomes, the longer the time required for comparison becomes. This is also a characteristic of a general comparator. In FIG. 14, the difference between Va and Vb is 1
The case of 0 mV, 1 mV, and 100 μV is shown. The upper characteristic is for Va <Vb, and the lower characteristic is for Va> Vb.

For this reason, the time during which the output potential of the comparator 691 is uncertain near the reference voltage Vref differs depending on the difference between the input voltage Vin to the comparator 691 and the reference voltage Vref. Feedback D / A converter 5 which takes in the output of the comparator after a lapse of a predetermined time from the comparison operation of
In No. 5, when the potential difference between the reference voltage Vref and the input signal voltage Vin in the comparator is very small, a latch error occurs in which erroneous data is taken in.

FIG. 15 is a signal system diagram in which the error due to the above-mentioned latch error is set to El and added by an adder 84 on the input side of the feedback D / A converter 55. The transfer function in this case is as follows: Y = [Hf / (Hf · z ⁻¹ +1)] · [X−El · z ⁻¹ + (1 / Hf) · Eq] (4) When the loop filter 52 has the characteristic of the equation (2), the equation (4) becomes the following equation (5). Y = X−El · z ⁻¹ + (1−z ⁻¹ ) · Eq (5) As described above, in the conventional A / D converter, if there is a latch miss, large noise is generated, and S / S There was a disadvantage that N was greatly deteriorated.

The present invention has been made in view of the above points, and an object of the present invention is to provide an A / D converter in which noise due to a latch error is suppressed using a noise shaping technique.

[0016]

[0017]

SUMMARY OF THE INVENTION The present invention provides a loop filter, a quantizer for inputting and quantizing an output signal of the loop filter, and a pulse width modulation for converting an output digital signal of the quantizer into an analog signal. A feedback loop comprising a type D / A converter and an encoder, and forming a feedback loop so as to input a difference between an output signal and an input signal of the pulse width modulation type D / A converter to the loop filter, and extracting the feedback from the feedback loop. A noise-shaping type A / D converter, which encodes the converted signal with the encoder and outputs the signal as an output signal.
A conversion unit having a parallel / serial converter, using an output point of the parallel / serial converter as a signal extraction point from the feedback loop, and passing the signal at the signal extraction point through a serial / parallel converter; The input is made to the encoder.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Example] FIG. 1 is a signal flow diagram of the A / D converter as a first reference example of the present invention. 11 is an input terminal of the analog signal X, 1
Reference numeral 2 denotes a loop filter having a transfer function of Hf, reference numeral 13 denotes a quantizer having a transfer function in which quantization noise Eq is superimposed on an input signal and output, and reference numeral 14 denotes a D / A converter for feedback. The feedback D / A converter 14 includes a latch circuit 141 with a delay of one sample time and a D / A converter 142. An encoder 15 converts the output signal of the latch circuit 141 into a binary code, an analog subtractor 16 subtracts the input signal X and the output of the feedback D / A converter 14, and an output terminal 17 of a digital signal Y. is there.

The circuit connection relationship includes an input signal X and a feedback D /
An analog subtracter 16 subtracts the signal fed back from the A conversion unit 14, and the subtraction result is input to a loop filter 12, and the output of the loop filter 12 is input to a quantizer 13. and inputs the output of the feedback D / a converter 14. Then, the encoder 15, the latch circuit 141 of the feedback D / A converter 14
The signal on the output side is input.

That is, the conventional circuit shown in FIG.
Latch circuit 141 of the present embodiment is the feedback D / A converter 14
Is output to the encoder 15. The transfer function of the circuit shown in Fig. 1 is as follows: Y = z- ¹ [Hf / (Hf z- ¹ +1)] [X + (1 / Hf) Eq] (6) When the filter 12 has the characteristic of the equation (2), the equation (6) is expressed as follows: Y = z ⁻¹ [X + (1−z ⁻¹ ) · Eq] (7)

The equations (6) and (7) are obtained by simply multiplying the equations (1) and (3) by the delay term z-1, and the output signal Y is obtained by the circuit shown in FIG. The same data as the data to be output is output with a delay of one sample time. Therefore, the S / N is exactly the same and the accuracy is also the same. Thus, the feedback D / A converter 14
Even if the configuration is such that the output signal of the latch circuit 141 at the preceding stage is taken out and input to the encoder 15, the same characteristics as those of the A / D converter having the configuration shown in FIG. 6 can be obtained.

[0022] [Second Example] Fig. 2 is a circuit diagram showing the configuration of a D / A converter as a second reference example of the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals. The second reference example, the feedback D / A converter 14 is obtained by suppressing Ratchimisu in latch circuit 141, the feedback D / A converter unit 1 4 and quantity <br/> coca 13 An adder 18 for adding the error E1 due to a latch error is provided between them.

The transfer function of the circuit shown in FIG. 2 is as follows: Y = z ⁻¹ [Hf / (Hf · z ⁻¹ +1)] · [X + (1 / Hf) (Eq + El)] (8) Become. When the loop filter 12 has the characteristic of the equation (2), the equation (8) is expressed as follows: Y = z ⁻¹ [X + (1−z ⁻¹ ) · El + (1−z ⁻¹ ) · Eq]・ ・ (9)

The major difference between Equations (4) and (5), which take account of latch errors in the D / A converter described in the conventional example, and Equations (8), (9), which take latch errors into account in this embodiment , is 8), (9) takes the noise shaping with respect to the error E1 in accordance Ratchimisu, when the oversampling Ratchimisu noise in the signal band by suppression of the noise in the low frequency region by shaping is also be smaller. As described above, in the present embodiment, it is possible to obtain A / D conversion characteristics having high resistance to latch miss.

[0025] [Third Example] Fig. 3 is a diagram showing a specific circuit configuration of the D / A converter as a third reference example of the present invention. Here, the quantizer 1
As 3, the circuit shown in FIG. 12 is used. Also,
As the D / A conversion circuit 142, a resistance load network type is used. The analog subtractor 16 includes a resistor R connected to the input terminal 11 and a resistor (not shown) in the D / A conversion circuit 142. As described above, in the present reference example, it is only necessary to change the connection point of the input of the encoder 15 with respect to the conventional circuit, and a new circuit technique is unnecessary and can be simply configured.

[0026] [First Embodiment] FIG. 4 is a diagram showing a specific circuit configuration of the D / A converter to the first embodiment of the present invention. Here, D / A for feedback
As the converter 19, the PWM type D / A converter shown in FIG. 9 is used. The PWM waveform is “0” in the voltage direction,
It has only information of “1” and has information corresponding to the output of the quantizer 13 in the time axis direction. Therefore, the output of the parallel / serial converter 63 in the feedback D / A converter 19 and inverse transformed by a serial / Parallel converter 20, PWM
The data latched by the type D / A conversion unit is reconstructed, and is input to the encoder 15 to be converted into a binary code. R4 and R5 are resistors constituting the analog subtractor 16, and the value is R.

In this embodiment, the parallel / serial converter 63 of the PWM type D / A converter is a DFF circuit 631
9 has a delay function, and the delay signal is used as an input signal of the encoder 15, so that this circuit can also obtain the same effect as the circuit shown in FIG.

[0028]

As described above, while the conventional noise shaping circuit causes a large error due to a latch error and deteriorates the N / S, according to the present invention, noise shaping is applied to the error due to the latch error. When oversampling is performed, latch miss noise in the signal band is significantly reduced due to the noise suppression effect in the low frequency region due to shaping.

Also, in the present invention, exactly the same output can be obtained only by the output of the A / D converter having a delay of one sample time with respect to the conventional circuit, and the good point of the conventional circuit remains. Also in the circuit configuration, there is no increase in the number of circuit parts that degrade the accuracy of the analog circuit and the like, and only a simple increase in the number of digital circuits is required.

FIG. 5 is an S / N characteristic diagram for explaining the effect of the present invention by simulation. According to the characteristics of the present invention shown by the solid line, the effect of suppressing the latch miss noise
The S / N is greatly improved as compared with the conventional characteristics indicated by the broken line.

[Brief description of the drawings]

FIG. 1 is a signal system diagram of an A / D converter according to a first reference example of the present invention.

FIG. 2 is a signal system diagram of an A / D converter according to a second reference example of the present invention.

FIG. 3 is a circuit diagram showing a specific configuration of an A / D converter according to a third reference example of the present invention.

FIG. 4 is a circuit diagram showing a specific configuration of the A / D converter according to the first embodiment of the present invention.

FIG. 5 is an S / N characteristic diagram of the A / D converter of the present invention and a conventional A / D converter.

FIG. 6 is a signal system diagram of a conventional A / D converter.

FIG. 7 is a frequency characteristic diagram of an output signal of the A / D converter in FIG. 6;

FIG. 8 is a waveform diagram for converting a digital signal into a PWM waveform.

FIG. 9 is a circuit diagram showing a configuration of a PWM type D / A converter.

10 is a signal system diagram of a conventional A / D converter using the PWM D / A converter of FIG.

FIG. 11 is a diagram showing a schematic configuration of a quantizer.

FIG. 12 is a specific circuit diagram of a 2-bit quantizer.

FIG. 13 is a circuit diagram of a positive feedback comparator.

FIG. 14 is an operation characteristic diagram of the comparator.

FIG. 15 is a signal system diagram of a D / A converter considering a latch miss.

Claims (1)

(57) [Claims] 1. A loop filter, a quantizer that inputs and quantizes an output signal of the loop filter, a pulse width modulation type D / A converter that converts an output digital signal of the quantizer into an analog signal, and An encoder, said pulse
Forming a feedback loop so that the difference between the output signal of the width modulation type D / A converter and the input signal is input to the loop filter, encoding the signal extracted from the feedback loop by the encoder, and outputting as an output signal; In the noise-shaping type A / D converter, the pulse width modulation type D / A conversion unit may be a parallel / serial.
The parallel / serial converter has an output point as a signal extraction point from the feedback loop, and the signal at the signal extraction point passes through the serial / parallel converter.
After, characterized in that is input to the encoder A /
D converter.