JP3388143B2 - D / A conversion circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A conversion circuit, and more particularly to a PWM modulation circuit for converting multi-valued digital data output from a ΔΣ modulation noise shaping circuit or the like in a ΔΣ modulation system A / D conversion device. The present invention relates to a D / A conversion circuit suitable for use in the case of converting into an analog signal.

[0002]

2. Description of the Related Art Conventionally, a .DELTA..SIGMA. Modulation system A / D which can obtain high resolution and high accuracy without adjustment in a D / A conversion stage of a digital audio source device such as a CD player or DAT.
A converter is used. FIG. 11 shows an example of a conventional ΔΣ modulation type A / D converter. The 16-bit digital audio data D ₁ having the sampling frequency f _S is oversampled to 4 f _S by the oversampling circuit 1, and then the ΔΣ modulation noise shaping circuit 2 significantly reduces the quantization noise in the audio band. . The ΔΣ modulation noise shaping circuit 2 has a sampling frequency F _S = 32f _S and n = (2k + 1) value {−
k,-(k-1),-(k-2), ..., -2, -1,
0, +1, +2, ..., + (k-2), + (k-1),
The digital data Y of + k} is output.

The digital data Y is a, b, ...
A PWM modulation circuit 3 having M output terminals of m systems PWM-modulates and outputs the value of the digital data Y and the value obtained by adding the output pulse width of each system for m systems. The PWM modulation circuit 3 has a frequency of 32 f _S
According to the double clock CK ₀ , the digital data Y output from the ΔΣ modulation noise shaping circuit 2 is read (input) at the timing of R _i in FIG. 12, and the PWM modulation signal corresponding to Y is output with a delay of 1T. The output of the PWM modulation circuit 3 is m buffer amplifiers 4 ₁ ,
4 ₂ , ..., 4 _m are individually passed to enable a large current to be output, and then resistors R ₁ , R ₂ ,.
R _m , the operational amplifier 5, and the addition circuit 6 having the resistors R _f1 and R _f2 for feedback are added. The resistors R ₁ , R ₂ , ..., R _m , R _f1 , and R _f2 all have the same resistance value. Then, the output of the adder circuit 6 is input to the analog low-pass filter 7, and the low frequency component (audio band component) of f _S / 2 or less is extracted and output as an analog audio signal.

[0004]

In the PWM modulation circuit 3, for example, the digital data Y has n = 5 values (-2, -1,
0, +1, +2) and the number of output systems m is two systems a and b, the operation is performed as shown in the diagram of FIG. 12, and the value of the digital data Y causes each output system to operate at the bottom of FIG. The PWM modulation signal of the combination pattern shown in is output. Specifically, when 1 / 32f _S is the period T, the pulse widths of a and b are both zero when Y = -2 (A pattern), and the pulse width of a is zero and b when Y = -1.
Has a pulse width of T / 2 (B pattern), and when Y = 0, the pulse widths of a and b are both T / 2 (C pattern) and Y = + 1.
The pulse width of a is T / 2, the pulse width of b is T (D pattern), and the pulse widths of a and b are both T when Y = + 2.
(E pattern).

On the other hand, in the output of the buffer amplifier 4 ₁ , a is H
V ₁ (H) when L, V ₁ (L) when L, buffer amplifier 4
The output of ₂ is V ₂ (H) when a is H, and V ₂ (L) when a is L (provided that V ₁ (H)> V ₁ (L), V ₂ (H)> V ₂ (L )
), Ideally V ₁ (H) = V ₂ (H), V ₁ (L) = V
₂ (L). However, the circuit constants, circuit characteristics of the buffer amplifier 4 ₁ and 4 _2, because of variations in the supply voltage, for example, only [Delta] V (H) is generated between the V ₁ (H) and V ₂ (H),
There is a difference of ΔV (L) between V ₁ (L) and V ₂ (L), and V ₁ (H) = V ₂ (H) + ΔV (H) ··· (1) V ₁ (L) = V ₂ (L) + ΔV (L) ··· (2) may occur.

As a concrete example, V ₁ (H) = 5 (V), V ₂
(H) = 4 (V), ΔV (H) = 1 (V), V ₁ (L) = 0.
5 (V), V ₂ (L) = 1 (V), ΔV (L) = -0.5
Assuming that (V), the relationship (Y, E) between Y and the average voltage E between the period T seen at the output point of the adder circuit 6 is P ₁ (−2,0.75) as shown in FIG. ), P ₂ (−1, 1.
5), P ₃ (0, 2.625), P ₄ (+1, 3.37)
5), P ₅ (+2,4.5), and P ₁ , P _3, P ₅
Does not have a perfect linear relationship by
A conversion accuracy will be poor. In order to improve the D / A conversion accuracy, it is necessary to make adjustments so that the output errors ΔV (H) and ΔV (L) between the buffer amplifiers 4 ₁ and 4 ₂ become zero, which is troublesome. .

The present invention has been made in view of the above problems of the prior art.
It is an object of the present invention to provide a D / A conversion circuit that can perform D / A conversion with high accuracy even if the output voltage of the buffer amplifier varies.

[0008]

In the D / A conversion circuit according to the first aspect of the present invention, the multi-value digital data having the sampling frequency F _S having m output systems and having n values is input. Then, P is set so that the value of the multi-level digital data and the value obtained by adding the output pulse widths of the respective systems for m systems are proportional to each other.
A PWM modulation circuit for performing WM modulation and output, m buffer amplifiers for individually inputting m system outputs of the PWM modulation circuit, an addition circuit for adding outputs of the m buffer amplifiers, and an output of the addition circuit In a D / A conversion circuit including an analog low-pass filter having a cut-off frequency f _C smaller than F _S / 2 for extracting a low-frequency component, the m-system output of the PWM modulation circuit and m buffer amplifiers are in a one-to-one correspondence. A switching circuit is provided for switching the combination of the connections of 1) at a fixed or variable switching speed higher than the cutoff frequency f _C of the analog low-pass filter.

The analog low-pass filter has a function of averaging the PWM modulation signals output from the m buffer amplifiers from the present time to the past. Even if there are variations in the output voltage value among the buffer amplifiers due to variations in the buffer amplifier circuit constants, circuit characteristics, power supply voltage, etc., P
By switching the 1-to-1 connection combination of the m system output of the WM modulation circuit and the m buffer amplifiers at a time interval shorter than 1 / f _C , variations in the output voltage value between the buffer amplifiers cancel each other out. Then, the average voltage of the added value of the output of each buffer amplifier during the D / A conversion operation becomes a value close to that when the output voltage value of each buffer amplifier is operated without variation, and the analog low-pass filter outputs D
An output with high A / A conversion accuracy can be obtained.

In the D / A conversion circuit according to the third aspect of the present invention, there are m output systems, and multi-valued digital data of a sampling frequency F _S that takes n values is input and the multi-valued data is input. A PWM modulation circuit that performs PWM modulation so that the digital data value and the value obtained by adding the output pulse width of each system for m systems are proportional to each other, and m units that individually input the m system output of the PWM modulation circuit Buffer amplifier, an adder circuit for adding the outputs of m buffer amplifiers, and a cutoff frequency f _C for taking out the low-frequency component of the output of the adder circuit is F _S /
D / including an analog low-pass filter smaller than 2
In the A conversion circuit, a switching circuit is provided for switching the combination of the 1-to-1 connection of the m system output of the PWM modulation circuit and the m buffer amplifiers, and the switching circuit is P
Every time multi-valued digital data other than a value in which the output of each system of the WM modulation circuit has the same pulse width is input to the PWM modulation circuit, one output of the m system of the PWM modulation circuit and m buffer amplifiers The feature is that the combination of the connection of pair 1 is switched.

As a result, the average voltage of the added values of the outputs of the respective buffer amplifiers during the D / A conversion operation becomes almost the same value as that when the output voltage values of the respective buffer amplifiers are operated without variation, and the analog voltage An output with higher D / A conversion accuracy can be obtained from the low-pass filter.

In the D / A conversion circuit according to any one of claims 1 and 3, the switching circuit regularly sets, for example, a combination of one-to-one connection between the m-system output of the PWM modulation circuit and m buffer amplifiers. (For example, cyclically) or randomly, by accumulating the times when certain multivalued digital data other than the values that all outputs of each system of the PWM modulation circuit have the same pulse width are PWM-modulated. When viewed, it is advisable to switch so that the output of any system of the PWM modulation circuit is input to all the buffer amplifiers with almost equal probability.

D / A according to claims 2 and 4 of the present invention
The conversion circuit is characterized in that the multi-valued digital data is data which is noise-shaped by the ΔΣ modulation method after being oversampled by the oversampling circuit and then passed through the ΔΣ modulation noise shaping circuit. As a result, digital data can be D / A converted with high accuracy.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a D / A according to the present invention.
FIG. 12 is a circuit diagram of the conversion device, and the same components as those in FIG. 11 are denoted by the same reference numerals. 1 is a 16-bit digital filter that oversamples input digital audio data D ₁ having a sampling frequency f _{S by} a factor of 4 and outputs 17-bit digital data D ₂ having a sampling frequency of 4 f _S , 2 is a ΔΣ with respect to digital data D _2.
Modulation method Performs noise shaper, -2, -1, 0, +
Sampling frequency F _S = 32f that takes five values of 1 and +2
_The ΔΣ modulation noise shaping circuit that outputs the multi-valued digital data Y of _S , 3A has two-system output terminals a and b, and outputs the multi-valued digital data Y with the value of Y and the output pulse width of each system. This is a PWM modulation circuit that performs PWM modulation so as to be proportional to the value obtained by adding two systems, and specifically, outputs as in the patterns A to E in FIG.

As shown in FIG. 2, the PWM modulation circuit 3A has a period of 32f input from a timing control circuit (not shown).
_The multi-valued digital data Y is read and the PWM modulation output is performed according to the clock CK ₁ of _S · n. The PWM modulation circuit 3A takes in (inputs) the multivalued digital data Y at the timing of R _i in FIG. 2 in CK ₁ , and outputs the PW corresponding to Y with a delay of the sampling cycle T (= 1/32 f _S ).
Output the M-modulated signal. 4 ₁ and 4 ₂ are P for each system
A buffer amplifier through which the WM modulated signal is passed, 6A is resistors R ₁ and R ₂ for addition, and R _f1 and R forming a feedback system.
_This is an adder circuit composed of _f2 and the operational amplifier 5, and adds the output voltages of the buffer amplifiers 4 ₁ and 4 ₂ . 7 is a cutoff frequency f lower than f _S / 2 with respect to the output of the adder circuit 6A.
It is an analog low-pass filter that extracts the low-frequency component at _C and outputs an analog audio signal. Here, the attenuation amount of the analog low-pass filter 7 at 32 f _S is −9.
It is assumed that it is set to about 0 dB (note that the analog low-pass filter 7 reduces the attenuation amount at u · f _S by −90 d).
It may be set to about B. However, u is 1, 2, 4, 8,
One real value in the range 1-32, such as 16,24).

A switching circuit 10 is provided between the PWM modulation circuit 3A and the buffer amplifiers 4 ₁ and 4 ₂ .
The PWM modulation circuit 3A uses the PWM of the multi-valued digital data Y
Every time the modulation output is completed for one data (every time the PWM modulation circuit 3A inputs the multi-value digital data Y for one data),
The combination of the output terminals a and b of the PWM modulation circuit 3A and the one-to-one connection of the buffer amplifiers 4 ₁ and 4 ₂ is switched. In the switching circuit 10, SW ₁ is a 2-input (e terminal and f terminal), 1-output analog switch, and on the input side, the e terminal is connected to the output terminal a of the PWM modulation circuit 3A and the f terminal is connected to the output terminal b. The output side is connected to the input side of the buffer amplifier 4 ₁ . SW ₂ also has 2 inputs (e
Terminals and f terminals) are one-output analog switches. On the input side, the e terminal is connected to the output terminal b of the PWM modulation circuit 3A, the f terminal is connected to the output terminal a, and the output side is the input side of the buffer amplifier 4 ₂ . Connected with. Reference numeral 20 denotes a switching control circuit, which is synchronized with the PWM modulation operation of the PWM modulation circuit 3A in accordance with a clock CK ₁ having a cycle of 1/32 f _S
Each time the WM modulation circuit 3A completes the PWM modulation output of the multi-valued digital data Y for one data (each time the multi-valued digital data Y is input to the PWM modulation circuit 3A), the analog switches SW ₁ and SW ₂ are set to the e side. And f side.

Next, the operation of the above-described embodiment will be described with reference to FIGS. FIG. 2 is a time chart showing the operation of the PWM modulation circuit 3A, the switching control circuit 20, and the switching circuit 10. FIG. 3 shows the value of the multivalued digital data Y.
FIG. 7 is a diagram showing the relationship with the average voltage E during the sampling period T (= 1 / 32f _S ) of the multilevel digital data Y seen at the output point of the adder circuit 6A. The output voltages of the buffer amplifiers 4 ₁ and 4 ₂ when the H level is input are respectively V ₁
(H), V ₂ (H), and the output voltage of the buffer amplifiers 4 ₁ and 4 ₂ when the L level is input are V ₁ (L) and V, respectively.
₂ (L). Circuit constants of buffer amplifiers 4 ₁ and 4 ₂ ,
Due to variations in circuit characteristics and power supply voltage, V ₁ (H) and V
There is a difference of ΔV (H) between ₂ (H) and V ₁ (L) and V
_A difference of ΔV (L) occurs between ₂ (L), and V ₁ (H) = V ₂ (H) + ΔV (H) ··· (3) V ₁ (L) = V ₂ (L) + ΔV ( L) ・ ・ (4). Here, as an example, V ₁
(H) = 5 (V), V ₂ (H) = 4 (V), ΔV (H) = 1
(V), V ₁ (L) = 0.5 (V), V ₂ (L) = 1
(V) and ΔV (L) = − 0.5 (V).

When the device starts the D / A conversion operation when the power is turned on, the 16-bit externally input digital audio data D ₁ having a sampling frequency f _S is oversampled four times by the digital filter 1.
17 bits, it is output as digital data D ₂ of the sampling frequency 4f _S. The digital data D ₂ is Δ
The Σ-modulation noise shaping circuit 2 performs the noise shaper of the ΔΣ modulation method so that the quantization noise of f _S / 2 or less is significantly reduced, and the sampling frequency is 32 f _S.
5 values (-2, -1, 0, +1, +2) of digital data Y are output.

As shown in FIG. 2, the multi-valued digital data Y output from the ΔΣ modulation noise shaping circuit 2 is generated by the PWM modulation circuit 3A according to the clock CK ₁ .
After reading (inputting) one data at a timing of R _i and performing PWM modulation, the relationship between the value of the multi-valued digital data Y and the pulse width of a and b from the output terminals a and b is as shown in FIG. The PWM modulation signal is output with a delay of 1T from the reading timing. The switching control circuit 20 has a cycle 1 synchronized with the PWM modulation operation of the PWM modulation circuit 3A.
According to the clock CK ₁ of / 32f _S , the PWM modulation circuit 3
Each time A completes the PWM modulation output of the multi-valued digital data Y by one data (every time the PWM modulation circuit 3A inputs the multi-valued digital data Y by one data), the analog switches SW ₁ and SW ₂ are set to the e side and the f side. Alternate between the sides.

As a result, each time the multi-valued digital data Y for one data is input to the PWM modulation circuit 3A, the PWM
Output terminal a of the modulation circuit 3A is connected to the input side of the buffer amplifier 4 _1, PWM modulated signal is output which is input from the output terminal a from the buffer amplifier 4 _1, b is connected to the input side of the buffer amplifier 4 ₂ Then, the PWM modulation signal input from the output terminal b is output from the buffer amplifier 4 _2, or conversely, the output terminal a of the PWM modulation circuit 3A is connected to the input side of the buffer amplifier 4 ₂ ,
PWM modulated signal inputted from the output terminal a ₂ is output, b is connected to the input side of the buffer amplifier 4 _1, as the PWM modulation signal input from the output terminal a from the buffer amplifier 4 ₁ is output switching To be

If the analog switches SW ₁ and SW _{2 of the} switching circuit 10 are both fixed to the e side, the value of the multivalued digital data Y and the adder 6
The sampling period of the corresponding PWM modulated signal Y as seen at the output T (1 / 32f _S) average voltage E between the (V)
The relationship (Y, E) of P ₁ (-
₂ , 0.75), P ₂ (-1, 1.5), P ₃ (0,
2.625), P ₄ (+1,3.375), P ₅ (+
2, 4.5) and P ₁ , P ₃ , P ₅ ride on the straight line L, but P ₂ and P ₄ are 0.18 from the straight line L to the minus side of E.
Only 75 (V) is off. For a period much longer than T,
For example, the original multi-valued digital data Y PWM-modulated during 10T in FIG. 2 is -2, -2, -1,-in time series.
When changing to 1,0,0, + 1, + 1, + 2, + 1, the average voltage E ′ during 10T seen at the output point of the adding circuit 6A becomes 2.4375 (V), which is an ideal value. Than 0.
It becomes smaller by 09375 (V).

On the contrary, if analog switch SW ₁ ,
Assuming that both SW ₂ are fixed to the f side, between the value of the multivalued digital data Y and the sampling period T of the PWM modulation signal corresponding to Y seen at the output point of the adder circuit 6A. The relationship (Y, E) of the average voltage E is Q ₁ (−2, 0.75), Q ₂ (−1,) as shown in FIG. 3B.
1.875), Q ₃ (0, 2.625), Q ₄ (+1,
3.75), Q ₅ (+2,4.5), and Q ₁ ,
Q ₃ and Q ₅ are the same as P ₁ , P ₂ and P ₃ , respectively, and are straight lines L
However, Q ₂ and Q ₄ are 0.
Only 1875 (V) is off. PWM during 10T of FIG.
The original multi-valued digital data Y that has been modulated and output is chronologically −
2, -2, -1, -1, 0, 0, +1, +1, +2, +
When it was changed to 1, 1 at the output point of the adder circuit 6A
The average voltage E ′ during 0T is 2.625 (V), which is higher than the ideal value by 0.093375 (V).

However, in this embodiment, each time the multivalued digital data Y is input to the PWM modulation circuit 3A, the output terminals a and b of the PWM modulation circuit 3A and the buffer amplifiers 4 ₁ and 4 ₂ are input. Since the combination of connection with and is switched, the value of the multi-valued digital data Y is converted into the average voltage E according to A of FIG. 3 every time the multi-valued digital data Y is input to the PWM modulation circuit 3A. Alternatively, the average voltage E is converted according to B in FIG.

Therefore, the original multivalued digital data Y PWM-modulated during 10T in FIG. 2 is -2, -in time series.
2, -1, -1, 0, 0, +1, +1, +2, +1 and, as shown in FIG. 2, the analog switch SW ₁
And SW ₂ while the PWM modulation output corresponding to the first −2 is performed, f while the PWM modulation output corresponding to the second −2 is performed, and the PWM modulation output corresponding to the first −1. While the output is e, the PWM modulation output corresponding to the second −1 is f, the PWM modulation output corresponding to the first 0 is e, and the PWM corresponding to the second 0 is output.
PW corresponding to the first +1 while f is being modulated
E during M modulation output, f during second PWM modulation output corresponding to +1 and PW corresponding to +2
While the M modulation output is being performed, P corresponding to the last +1
When the WM modulation output is switched to e, and the PWM modulation output corresponding to the last +1 is switched to f, the average voltage E ′ during 10T seen at the output point of the adder circuit 6A is , 2.55 (V), ideal value 2.5312
It is only 0.01875 (V) smaller than 5 (V),
The value is closer to the ideal value than when the switching circuit 10 is not provided.
The voltage averaged over a period longer than 10 T becomes closer to the ideal value.

The output of the adder circuit 6A is extracted by the analog low-pass filter 7 as a component having a cut-off frequency f _C or less, which is slightly lower than f _S / 2, and is output as an analog audio signal. Analog low pass filter 7
Of the PWM modulation signal output from the _two buffer amplifiers 4 ₁ and 4 ₂ is traced back from the present time to the past, and the sampling cycle T (= 1
/ 32f _s ) is equivalent to averaging over a much longer period. Therefore, even if the output voltages of the buffer amplifiers 4 ₁ and 4 ₂ when the H level or the L level is input have the difference shown in the formula (3) or (4), the PWM
The output terminals a and b of the modulation circuit 3A and the buffer amplifier 4 ₁ ,
By switching the combination of connection with 4 ₂ in the cycle T, the output of the analog low-pass filter 7 is the buffer amplifier 4 ₁ when H level or L level is input.
And the output voltage of 4 ₂ have almost the same value as the ideal value when there is no difference, and the D / A conversion accuracy is improved.

According to this embodiment, the two outputs of the PWM modulation circuit 3A and the two buffer amplifiers 4 are provided between the output terminals a and b of the PWM modulation circuit 3A and the buffer amplifiers 4 ₁ and 4 _2. A switching circuit 10 capable of switching a 1: 1 connection combination with ₁ , 4 ₂ is provided, and the switching control circuit 20 synchronizes with the PWM modulation operation of the PWM modulation circuit 3A in accordance with the clock CK ₁ having a cycle of 1 / 32f _S. ,
The PWM modulation circuit 3A uses the PWM of the multi-valued digital data Y
Every time the modulation output is completed for one data (every time the PWM modulation circuit 3A inputs the multi-value digital data Y for one data),
The two-system output of the PWM modulation circuit 3A and the one-to-one connection combination of the _two buffer amplifiers 4 ₁ and 4 ₂ are switched at a switching speed much higher than f _C.

The analog low-pass filter 7 is an adder circuit 6
Because it has a function of averaging the output of the A, circuit constants of the buffer amplifier 4 _1, 4 _2, circuit characteristics, the variation in power supply voltage or the like if there are variations in the output voltage value between the buffer amplifier 4 _1, 4 ₂ Also, by switching the combination of the one-to-one connection between the two outputs of the PWM modulation circuit 3A and the two buffer amplifiers 4 ₁ and 4 ₂ at a switching speed much higher than f _C , each buffer amplifier 4 ₁ , 4 ₂ are canceled out, and the average voltage of the added value of the outputs of the buffer amplifiers 4 ₁ , 4 ₂ during the D / A conversion operation is dispersed in the output voltage value of each buffer amplifier. It becomes a value close to that when it is operated in the absence of the condition, an output with high D / A conversion accuracy can be obtained from the analog low pass filter 7, and the capability of the ΔΣ modulation noise shaper type D / A conversion device can be improved. so Wear.

In the above-described embodiment, the switching control circuit 20 causes the switching circuit 10 to switch each time the PWM modulation circuit 3A inputs the multivalued digital data Y for one data. It can be switched every time a fixed number of data is input at about 8, or 1 to 8
The number may be changed every time a variable number of data is input, and if the cutoff frequency f _C of the Arona glow pass filter 7 is 32 f _S / 2 or less, f _S /
It can be set higher than 2 (in this case, the attenuation amount of the analog low-pass filter 7 is -9 at 2f _C , for example).
It is set to be about 0 dB or 32f _S / 2-3
It may be set to be about −90 dB at a certain frequency within the range of 2f _S ). In short, the cutoff frequency f _C of the analog low-pass filter 7 is set to be smaller than 32 f _S / 2, and the output of the two systems of the PWM modulation circuit 3A and 2
The one-to-one connection combination with each of the buffer amplifiers 4 ₁ and 4 ₂ is switched at a fixed or variable switching speed higher than the cutoff frequency f _C of the analog low-pass filter 7, and each of the systems of the PWM modulation circuit 3A is switched. Some multi-valued digital data other than the values that all output have the same pulse width is P
When WM-modulated output is cumulatively viewed (Y = -1
When the PWM modulation output is cumulatively viewed or when Y = + 1 when the PWM modulation output is cumulatively viewed), the output of any system of the PWM modulation circuit 3A is
The buffer amplifiers 4 ₁ and 4 ₂ may be switched so that they are input with almost equal probability.

FIG. 4 shows a D according to the second embodiment of the present invention.
2 is a circuit diagram of an A / A conversion device, and the same components as those in FIG. 1 are denoted by the same reference numerals. In the embodiment of FIG. 1, the switching control circuit 20 switches the analog switches SW ₁ and SW ₂ of the switching circuit 10 every time the PWM modulation circuit 3A inputs the multi-valued digital data Y. Then, every time the PWM modulation circuit 3A inputs -1 and +1 of the multilevel digital data Y, the switching circuit 1
The 0 analog switches SW ₁ and SW ₂ are switched.

In FIG. 4, 20A is a PWM modulation circuit 3
Each time A inputs -1 and +1 in the multi-valued digital data Y, the analog switches SW ₁ , S of the switching circuit 10 are input.
It is a switching control circuit for switching W ₂ . In the switching control circuit 20A, 21 is an odd number discriminating circuit, and the multi-valued digital data Y is read at the time when the PWM modulation circuit 3A reads the multi-valued digital data Y (at the time of inputting) according to the clock CK ₁ of the frequency 32f _S. Determine if it is odd,
If the number is odd, the H level is output, and if the number is even, the L level is output. Reference numeral 22 denotes a D-flip-flop, which has an inverting output terminal connected to the D terminal and an output terminal of the odd number discrimination circuit 21 connected to the enable terminal E. Further, the clock CK ₁ is input to the clock terminal CK. This D-flip-flop 22 does not change its state while the input of the enable terminal is at the L level, and becomes operable when the input of the enable terminal becomes the H level, and the clock CK ₁
At the rising timing of, the level obtained by inverting the input of the D terminal is output from the inverting output terminal. The D-flip-flop 22 outputs a switching control signal from the inverting output terminal to the analog switches SW ₁ and SW ₂ of the switching circuit 10.
The analog switches SW ₁ and SW ₂ are switched to the e side when the switching control signal is at the H level and to the f side when the switching control signal is at the L level. The other components of FIG. 4 are constructed in exactly the same way as in FIG.

Next, the operation of the above-described embodiment will be described with reference to FIG. FIG. 5 is a time chart showing the operations of the PWM modulation circuit 3A, the switching control circuit 20A, and the switching circuit 10. The output voltages V ₁ (H) and V ₂ (H) of the buffer amplifiers 4 ₁ and 4 ₂ when the H level is input
Between and between the output voltages V ₁ (L) and V ₂ (L) of the buffer amplifiers 4 ₁ and 4 ₂ when the L level is input, the circuit constants and circuits of the buffer amplifiers 4 ₁ and 4 ₂ Due to variations in characteristics, power supply voltage, etc., a difference of ΔV (H) and ΔV (L) occurs, and the relationships (3) and (4) described above are assumed. Here, as an example, V ₁ (H) = 5 (V), V
₂ (H) = 4 (V), ΔV (H) = 1 (V), V ₁ (L) =
_{0.5 (V), V 2 (} L) = 1 (V), ΔV (L) = -0.
5 (V).

After the device starts the D / A conversion operation when the power is turned on, the multi-level digital data Y output from the ΔΣ modulation noise shaping circuit 2 is P-valued as shown in FIG.
The WM modulation circuit 3A reads (inputs) one data at a timing of R _i according to the clock CK ₁ , and outputs P
After the WM modulation, the relationship between the value of the multi-valued digital data Y and the pulse width of a and b from the output terminals a and b is shown in FIG.
The PWM modulation signal having the patterns A to E is output 1T behind the reading timing. Here, 1
The original multilevel digital data Y of the PWM modulation output during 2T is -1, -2, -2, -1, 0, +1, + in time series.
2, +1, 0, -1, -2, -1.

Odd number discrimination circuit 2 of switching control circuit 20A
1, the odd number is determined at the timing when the PWM modulation circuit 3A inputs the multi-valued digital data Y according to the clock CK ₁ , and when the odd number is H level, the even level is D level.
Output to the enable terminal E of the flip-flop 22. The multilevel digital data Y input by the PWM modulation circuit 3A is -1, -2, -2, -1, 0, +1, + in time series.
When changing to 2, +1, 0, -1, -2, -1, the output of the odd number discrimination circuit 21 is H, L, L, H, L, H, L,
It changes as H, L, H, L, H.

On the other hand, the D-flip-flop 22 is forcibly reset for a certain period of time by an H-level reset signal input from a power-on reset circuit (not shown) immediately after the power is turned on. The inverted output terminal of the flip-flop 22 is initialized to the H level, and the D terminal input is at the H level. Here, it is assumed that the reset signal drops to the L level when the ΔΣ modulation noise shaping circuit 2 starts to output the first −2.

After that, when the clock CK ₁ is input at the timing of R ₁ when the PWM modulation circuit 3A inputs the first −2 of the multilevel digital data Y, the odd number discrimination result immediately before that is an odd number (−1). Since the input of the enable terminal E is H level and the D-flip-flop 22 is operable, the inverting output terminal is inverted to L level,
PWM modulation circuit 3A corresponds to the first Y = -1 PWM
During the modulation output, the L level switching control signal is output to the analog switches SW ₁ and SW ₂ to switch to the f side.

Next, the PWM modulation circuit 3A outputs the second -2 signal.
When the clock CK ₁ is input at the timing of R ₂ for inputting, the immediately preceding odd number discrimination result is an even number (−2), and the input of the enable terminal E is at L level, the inverting output terminal remains at L level, PWM modulation circuit 3A is the first Y
The analog switches SW ₁ and SW ₂ are left on the f side while the PWM modulation output corresponding to = -2 is being performed. PW
When the clock CK ₁ is input at the timing of R ₃ when the second M −1 is input to the M modulation circuit 3A, the immediately preceding odd number determination result is an even number (−2) and the input at the enable terminal E is at the L level. The inverting output terminal remains L level,
PW corresponding to the second Y = -2 by the PWM modulation circuit 3A
While performing M modulation output, analog switch SW ₁ ,
Leave SW ₂ on the f side.

Next, when the clock CK ₁ is input at the timing of R ₄ when the PWM modulator 3A inputs the first 0, the immediately preceding odd number discrimination result is an odd number (−1), and the enable terminal E is at H level. Therefore, the inverting output terminal is inverted to the H level, and the analog switches SW ₁ and SW ₂ are switched to the e side while the PWM modulation circuit 3A is performing the PWM modulation output corresponding to the second Y = −1. Next, when the clock CK ₁ is input at the timing of R ₅ when the PWM modulation circuit 3A first inputs +1, the immediately preceding odd number determination result is even (0), and the input of the enable terminal E is at L level. The inverting output terminal remains at the H level, and the analog switches SW ₁ and SW ₂ are left at the e side while the PWM modulation circuit 3A is performing the PWM modulation output corresponding to the first 0.

Similarly, while the PWM modulation circuit 3A is performing the PWM modulation output corresponding to the first +1, since the immediately preceding odd number discrimination result is an odd number (+1), the analog switches SW ₁ and SW ₂ are set to the f side. switching, then to remain while performing PWM modulation output PWM modulation circuit 3A corresponding to the first +2, odd discrimination result of the immediately preceding even number (+2) so the analog switch SW _1, SW ₂ of the f side Then, while the PWM modulation output corresponding to the next Y = + 1 and 0 is being performed, the analog switches SW ₁ and SW ₂ are switched to the e side, and the PWM corresponding to the next Y = −1 and −2.
During modulation output, analog switches SW ₁ , S
Switch W ₂ to the f side.

As described above, the switching control circuit 20A is
Until then, for example, the analog switches SW ₁ and SW ₂ have been switched to the e side, and the a terminal output of the PWM modulation circuit 3A is input to the buffer amplifier 4 ₁ and the b terminal output is input to the buffer amplifier 4 ₂ . At this time, when an odd Y value of −1 or +1 is input to the PWM modulation circuit 3A, the analog switches SW ₁ and SW ₂ are switched to the f side with a delay of 1T, and the a terminal output of the PWM modulation circuit 3A is buffered. 4 ₂ and the b terminal output is buffer amplifier 4
Input to ₁ . After that, when an odd Y of −1 or +1 is input to the PWM modulation circuit 3A again, the analog switches SW ₁ and SW ₂ are returned to the e side with a delay of 1T, and PWM
The a-terminal output of the modulation circuit 3A is input to the buffer amplifier 4 ₁ , and the b-terminal output is input to the buffer amplifier 4 ₂ .

As a result, the PWM modulation output of the PWM modulation circuit 3A for the odd number -1 or +1 appearing in the multi-valued digital data Y is the analog switch SW ₁ , S last time.
Buffer amplifiers 4 ₁ , 4 with W ₂ switched to the e side
_If it was input to ₂ , this time, analog switch S
W _1, SW ₂ and is input to the buffer amplifier 4 _1, 4 ₂ in a state of switching to f side, conversely, last buffer amplifier 4 ₁ in a state of switching the analog switch SW _1, SW ₂ toward f, 4 _If it is input to _2, it is input to the buffer amplifiers 4 ₁ and 4 ₂ with the analog switches SW ₁ and SW ₂ switched to the e side this time.
The combination of the connections between the terminals a and b of the PWM modulation circuit 3A and the buffer amplifiers 4 ₁ and 4 ₂ is cyclically switched every time.

As is apparent from FIG. 12, multi-value digital
When the data Y is an odd number of -1 and +1 the PWM modulation circuit
Output of a terminal and b terminal when 3A PWM-modulates Y
The pulse width of the force is different and the analog switch S
W₁, SW₂Is switched to the e side, addition
Sampling of PWM modulation output seen at the output point of circuit 6A
Period T (= 1 / 32f_S) Average voltage E is the straight line in FIG.
P goes off from L to the minus side₂Or P_FourNext to Anna
Log switch SW₁, SW₂Has been switched to the f side
When the average voltage E is outside the straight line L in FIG.
Q₂Or Q_FourBecomes Here, multilevel digital
Addition times for odd -1 or +1 appearing in data Y
Sampling frequency of PWM modulation output seen at the output point of path 6A
Period T (= 1 / 32f _S), The average voltage E in FIG.₂
Or P_FourAnd Q₂Or Q_FourTo switch to
Then, the buffer amplifier 4₁, 4₂Output voltage error of successive phase
Will be killed. On the other hand, the multivalued digital data Y
When -2, 0, +2, the PWM modulation circuit 3A is PWM
The pulse widths of the a-terminal output and b-terminal output when modulated are the same.
Same as analog switch SW₁, SW₂Switching
Sampling of PWM modulation output regardless of position
Period T (= 1 / 32f_S), The average voltage E is the straight line in FIG.
It rides on L and there is no error.

As shown in j of FIG. 5, PWM is performed during 10T.
The original multi-valued digital data Y that has been modulated and output is chronologically −
1, -2, -2, -1, 0, +1, +2, +1, 0,-
When the odd value appears odd number of times, the average voltage E ′ during 10T seen at the output point of the adding circuit 6A is 2.3625 (V), which is more than the ideal value. 0.
Only 01875 (V) large. Further, as shown in k of FIG. 5, the original multi-valued digital data Y PWM-modulated during 10T is -2, -2, -1, 0, + in time series.
1, +2, +1, 0, -1, -2, and when the odd value appears even times, the average voltage E'for 10T seen at the output point of the adder circuit 6A is The value becomes 2.25 (V), which matches the ideal value 2.25 (V).

The output of the analog low-pass filter 7 is 2
The added value of the PWM modulation signal output from each of the buffer amplifiers 4 ₁ and 4 ₂ is traced back from the present time to the past, and in a period much longer than the sampling period T (= 1/32 f _S ) of the multilevel digital data. It is equivalent to the crossed average. Therefore, even if the output voltages of the buffer amplifiers 4 ₁ and 4 ₂ when the H level or the L level is input have the difference shown in the formula (3) or (4), the PWM modulation circuit 3A
Is switched between the output terminals a and b of the PWM modulation circuit 3A and the buffer amplifiers 4 ₁ and 4 ₂ each time an odd number −1 or +1 of the multilevel digital data Y is input, the analog The output of the low pass filter 7 is
When the H level or the L level is input, the output voltages of the buffer amplifiers 4 ₁ and 4 ₂ have substantially the same ideal value as that when there is no difference, and the D / A conversion accuracy is significantly improved.

According to this embodiment, the value of the output of each system of the PWM modulation circuit 3A has the same pulse width -2,
Every time multi-valued digital data Y other than 0 and +2 is input to the PWM modulation circuit 3A, one-to-one connection between the outputs of the two systems of the PWM modulation circuit 3A and the two buffer amplifiers 4 ₁ and 4 ₂ is performed. Since the combination is cyclically switched, the analog low-pass filter 7 is added to the adder circuit 6A.
Because it has a function of averaging the output of the circuit constants of the buffer amplifier 4 _1, 4 _2, circuit characteristics, even if there are variations in the output voltage value between the buffer amplifier 4 _1, 4 ₂ by variations in power supply voltage, etc. , By switching the 1: 1 connection combination of the two outputs of the PWM modulation circuit 3A and the two buffer amplifiers 4 ₁ , 4 ₂ at a switching speed much higher than f _C , each buffer amplifier 4 ₁ , The variations in the output voltage value between 4 ₂ are canceled out, and the average voltage of the added value of the outputs of the buffer amplifiers 4 ₁ and 4 ₂ during the D / A conversion operation varies in the output voltage value of each buffer amplifier. The value is almost the same as when operated in the absence state, and an output with extremely high D / A conversion accuracy can be obtained from the analog low-pass filter 7, and the D / A of the ΔΣ modulation noise shaper system
The capacity of the conversion device can be further increased.

In the embodiment of FIG. 1, the switching control circuit 20 switches the switching circuit 10 every time the PWM modulation circuit 3A inputs one value of the multivalued digital data Y. The time series of Y happens to be -2, -1, 0, +1, +2, +1, 0,-.
When the odd number and the even number appear alternately, when the PWM modulation circuit 3A outputs the PWM modulation for the odd values −1 and +1 among them, the analog switch SW ₁ , SW ₂ is always e side (or f side)
Will be switched to the buffer amplifier 4 ₁ , 4
The output voltage error of ₂ is no longer canceled. However, according to the embodiment of FIG. 4, the time series of the multivalued digital data Y is -2, -1, 0, +1, +2, +1, 0, -1,-.
2 and -1, even if the PWM modulation circuit 3A has an odd value of Y
Each time the PWM modulation output corresponding to is output, the analog switches SW ₁ and SW ₂ are alternately switched between the e side and the f side to cancel the output voltage error of the buffer amplifiers 4 ₁ and 4 ₂ . High D / A conversion accuracy can always be realized.

In the embodiment shown in FIG. 4, the output of each system of the PWM modulation circuit 3A has the same pulse width.
Each time the multi-valued digital data Y other than 2, 0 and +2 is input to the PWM modulation circuit 3A, 2 of the PWM modulation circuit 3A is input.
The combination of the output of the system and the one-to-one connection of the _two buffer amplifiers 4 ₁ and 4 ₂ is cyclically switched (the analog switches SW ₁ and SW ₂ are e → f → e →
f → ...) or may be switched randomly (analog switches SW ₁ and SW ₂ are switched to e).
→ f → f → e → f → e → e → f → ... Further, the cutoff frequency f _C of the Arona glow pass filter 7 may be set higher than f _S / 2 if it is 32 f _S / 2 or less (in this case, the attenuation amount of the analog low pass filter 7 is, for example, 2 f). or set to be approximately -90dB in _{C, and} may be set to be approximately -90dB at a certain frequency in the range of 32f _S / 2~32f _S). In short, the cutoff frequency f _C of the analog low-pass filter 7 is set to be smaller than 32 f _S / 2, and the multi-value digital data other than the value in which the output of each system of the PWM modulation circuit 3A has the same pulse width. Is PWM
Accumulated time when modulation output is performed (Y = -1 is P
When WM modulated output is cumulatively viewed or Y =
(When accumulating when +1 is PWM modulated output)
In addition, the output of any system of the PWM modulation circuit 3A may be switched so as to be input to the buffer amplifiers 4 ₁ and 4 ₂ with almost equal probability.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a circuit diagram of a D / A converter according to the present invention, and the same components as those in FIG. 1 are designated by the same reference numerals. 1 is 16 bits, sampling frequency f
Input digital audio data D ₁ of _S is over-sampled 4 times, 17 bits, sampling frequency 4
digital filter for outputting the digital data D ₂ of f _S, 2B performs ΔΣ modulation scheme noise shaper to digital data _{D 2, -3, -2, -1,0} , + 1,
Sampling frequency F _S = 32 that takes 7 values of +2 and +3
A ΔΣ modulation noise shaping circuit which outputs multi-valued digital data Y of f _S , 3B has output terminals of three systems a, b, and c, and multi-valued digital data Y is output as Y value and each system. This is a PWM modulation circuit that performs PWM modulation so as to be proportional to a value obtained by adding the pulse widths of two systems and outputs the PWM modulation.

Specifically, the PWM modulation circuit 3B outputs the PWM modulation signal of the combination pattern shown in the leftmost column I of FIG. 7 from each output system according to the value of the digital data Y. . The 1 / 32f _S as the period T, Y = pulse width of a and b and c when -3 both zero (F pattern), the pulse width of a time Y = -2 is T /
2, the pulse widths of b and c are both zero (G pattern), Y =
When −1, the pulse widths of a and b are T / 2, the pulse width of c is zero (H pattern), when Y = 0, the pulse widths of a, b and c are both T / 2 (I pattern), Y = + 1, the pulse width of a is T, the pulse widths of b and c are both T / 2 (J pattern), the pulse widths of a and b are T, and the pulse width of c is T / 2 (when Y = + 2. K pattern), a and b when Y = + 3
The pulse widths of c and c are both T (L pattern).

As shown in FIG. 9, the PWM modulation circuit 3B has an input cycle of 32f from a timing control circuit (not shown).
_The multivalued digital data Y is read and the PWM modulation output is performed according to the clock CK ₀ of _S · n. The PWM modulation circuit 3B takes in (inputs) the multivalued digital data Y at the timing of R _i in FIG. 9 in CK ₀ , and PW corresponding to Y with a delay of the sampling cycle T (= 1/32 f _S ).
Output the M-modulated signal. 4 ₁ to 4 ₃ are P for each system
A buffer amplifier through which the WM modulated signal is passed, and 6B, resistors R _{1 to} R ₃ for addition, and R _f1 and R forming a feedback system.
and _f2, a summing circuit comprising an operational amplifier 5, adds the output voltage of the buffer amplifier ₄₁ to _3. 7 is a cutoff frequency f lower than f _S / 2 with respect to the output of the adder circuit 6B.
It is an analog low-pass filter that extracts the low-frequency component at _C and outputs an analog audio signal. The analog low-pass filter 7 has an attenuation amount of 32 f _S at −90 d, for example.
It is set to be about B (note that the analog low-pass filter 7 reduces the attenuation amount at u · f _S by −90 dB).
You may set so that it may become a degree. However, u is 1, 2,
4,8,16,24, etc., one real value in the range 1-32).

[0050] 10B is a switching circuit provided between the PWM modulation circuit 3B and a buffer amplifier ₄₁ to _3, except the values which the output of each system is all the same pulse width of the PWM modulation circuit 3B -2 , -1, + 1, + multilevel digital data Y 2 values each time it is input to the PWM modulation circuit 3B, 1 and 3 lines of output and three buffer amplifiers ₄₁ to ₃ of the PWM circuit 3B Switch the combination of the one-to-one connection. Of the switching circuit 10B, SW ₁₀ is three inputs (e, f, g terminal), an analog switch 1 output, the output terminal a of the input side e terminal PWM modulation circuit 3B, f terminal output terminal b, The g terminal is connected to the output terminal c, and the output side is connected to the input side of the buffer amplifier 4 ₁ . SW _{20 is} also an analog switch with 3 inputs (e, f, g terminals) and 1 output, and the e terminal on the input side is PWM
The output terminals b and f of the modulation circuit 3B are connected to the output terminals c and g of the output terminal a, and the output side thereof is connected to the input side of the buffer amplifier 4 ₂ . SW _{30 is} also an analog switch having 3 inputs (e, f, g terminals) and 1 output, and on the input side, the e terminal is the output terminal c, f terminal of the PWM modulation circuit 3B, the output terminal a, and the g terminal is the output terminal b. And the output side is connected to the input side of the buffer amplifier 4 ₃ .

20B is a switching control circuit, which is a PWM
Cycle 1/32 synchronized with the PWM modulation operation of the modulation circuit 3B
In accordance with the clock CK ₁ of f _S , the PWM modulation circuit 3B
2, -1, + 1, + every time multivalued digital data Y 2 values are entered, randomly switching substantially in conjunction with analog switches SW ₁₀ to SW _30, an output of each path of the PWM modulation circuit 3B are all When the PWM modulation output of certain multi-valued digital data other than the values having the same pulse width is cumulatively viewed (when Y = -2 is PWM modulation output, or when = -1 when PWM output is cumulatively viewed, or Y = + 1 is PWM
When modulated output is cumulatively viewed, or Y = +
2 when PWM output is cumulatively viewed)
The output of any of the system of the PWM circuit 3B also switched as input with approximately equal probability to the buffer amplifier ₄₁ to _3, to cancel the output voltage error of the buffer amplifier ₄₁ to _3.

In the switching control circuit 20B, 30 is an adder, which adds the multivalued digital data Y output from the ΔΣ modulation noise shaping circuit 2B and the output of the latch circuit described later. 31 is an arithmetic unit for calculating and outputting the remainder (mod3) obtained by dividing the output x of the adder 30 by 3;
2 is a latch circuit that latches the output z of the arithmetic unit 31 at the timing when the clock CK ₁ is input to the latch strobe terminal RS, 33 is a decoder, and the multi-valued digital data Y output from the ΔΣ modulation noise shaping circuit 2B And the output y of the latch circuit 32 are read at the timing when the clock CK ₁ is input, and depending on the combination of (Y, y), 2 bits “LL” and “L” are displayed as shown in FIG.
H ", and converted into a control signal CD which takes a value of either" HH ", the switching control of the analog switches SW ₁₀ to SW ₃₀ outputs to the switching circuit 10B.

[0053] The decoder 33 Y is -3,0, when + 3, regardless of the value of y, outputs "LL" as the control signal CD, by switching the analog switches SW ₁₀ to SW ₃₀ to e position, PWM Output terminals ac of the modulation circuit 3B
And inputs the output to the buffer amplifier ₄₁ to ₃ each (see column II of FIG. 7). In addition, Y is -2, -1,
If y is 0 at +1 and +2, the analog switches SW _{10 to} SW ₃₀ are switched to the e position, but y is 1
If so, switch to f position and PWM modulation circuit 3B
The outputs from the output terminals a to c are input to the buffer amplifiers 4 ₂ , 4 ₃ and 4 ₁ (column III in FIG. 7), and if y is 2, the PWM modulation circuit 3 is switched to the g position.
The outputs from the output terminals a to c of B are input to the buffer amplifiers 4 ₃ , 4 ₁ and 4 ₂ (column IV in FIG. 7). The other components are configured exactly as in FIG.

Next, the operation of the above-described embodiment will be described with reference to FIGS. FIG. 9 shows the PWM modulation circuit 3B,
A time chart showing the operations of the switching control circuit 20B and the switching circuit 10B. FIG.
6 is a diagram showing the relationship between the value of ## EQU1 ## and the average voltage E during the sampling period T (= 1 / 32f _S ) of the multivalued digital data Y seen at the output point of the adder circuit 6B.

[0055] Each output voltage of the buffer amplifier ₄₁ to ₃ when H level is _{input, V 1 (H) ~V 3} (H),
Buffer amplifiers 4 ₁ to 4 ₃ when L level is input
And the output voltage of each is V ₁ (L) to V ₃ (L). Circuit constants, circuit characteristics of the buffer amplifier ₄₁ to _3, for the variation in power supply voltage or the like, [Delta] V between V ₁ (H) and V ₂ (H)
_A difference of ₁₂ (H) occurs, and ΔV ₁₃ is generated between V ₁ (H) and V ₃ (H).
A difference of (H) occurs, and ΔV ₁₂ (L) is generated between V ₁ (L) and V ₂ (L).
Difference occurs, ΔV ₁₃ (L) between V ₁ (L) and V ₃ (L)
Difference occurs, V ₁ (H) = V ₂ (H) + ΔV ₁₂ (H) ·· (5) V ₁ (H) = V ₃ (H) + ΔV ₁₃ (H) · · (6) V ₁ ( L) = V ₂ (L) + ΔV ₁₂ (L) ··· (7) V ₁ (L) = V ₃ (L) + ΔV ₁₃ (L) ··· (8). Here, as an example, V ₁
(H) = 5 (V), V ₂ (H) = 4.5 (V), V ₃ (H) =
4 (V), ΔV ₁₂ (H) = 0.5 (V), ΔV ₁₃ (H) =
0.5 (V), V ₁ (L) = 0.5 (V), V ₂ (L) = 1
(V), V ₃ (L) = 1.5 (V), ΔV ₁₂ (L) = −0.
5 (V) and ΔV ₁₃ (L) = − 1 (V).

After the device starts the D / A conversion operation when the power is turned on, the multilevel digital data Y output from the ΔΣ modulation noise shaping circuit 2B is as shown in FIG.
The PWM modulation circuit 3B reads (inputs) one data at a time of R _i according to the clock CK ₁ ,
After being PWM-modulated, the PWM modulation signal from the output terminals a, b, and c has the relationship between the value of the multi-valued digital data Y and the pulse width of a, b, and c as shown in column I of FIG. It is output with a delay of 1T. Here, 12T
The original multi-valued digital data Y of the PWM modulation output between -3, -3, -2, -2, -1, -1, -1,
It is assumed that the values are 0, +1, +2, +2, and +2.

Immediately after the power is turned on, the latch circuit 32 is forcibly reset for a certain period of time by an H-level reset signal input from a power-on reset circuit (not shown). The output of the latch circuit 32 is It is initialized to L level. Here, it is assumed that the reset signal drops to the L level when the ΔΣ modulation noise shaping circuit 2B starts to output the first −3. At this time, the adder 30
Has an output x of -3 and an output z of the calculator 31 is 0. When the clock CK ₁ is input to the switching control circuit 20B at the timing of R _{0 when} the PWM modulation circuit 3B inputs the first −3 of the multilevel digital data Y, the decoder 3
3 is the combination of (Y, y) input at that time is (-
3,0), so it outputs a control signal CD of "LL", to switch the analog switches SW ₁₀ to SW ₃₀ of the switching circuit 10B to the e side. On the other hand, the latch circuit 32 latches 0 output from the arithmetic unit 31 and outputs it.

Next, when the ΔΣ modulation noise shaping circuit 2B outputs the second -3, x = -3 and z = 0, and the PWM modulation circuit 3B inputs the second -3 R ₁ When the clock CK ₁ is input at the timing of, the decoder 33 inputs (Y, y) at that time again to (-
3, 0), so set analog switches SW _{10 to} SW ₃₀ to e
On the other hand, the latch circuit 32 latches z = 0 and outputs it. ΔΣ modulation noise shaping circuit 2B
When the first -2 is output, x = -2, z = + 1, and when the clock CK ₁ is input at the timing of R ₂ when the PWM modulation circuit 3B inputs the first -2, the decoder 33 causes Since (Y, y) input in (2, 0) is (-2, 0), the analog switches SW _{10 to} SW ₃₀ are left on the e side, while the latch circuit 32 outputs +1.

Next, when the ΔΣ modulation noise shaping circuit 2B outputs the second −2, x = −1 and z = + 2.
In, R ₃ to PWM modulation circuit 3B to enter the second -2
When the clock CK ₁ is input at the timing of, the decoder 33 changes the input (Y, y) to (−2, +).
Since 1), the analog switches SW _{10 to} SW ₃₀ are switched to the f side, and the latch circuit 32 outputs +2. When the ΔΣ modulation noise shaping circuit 2B outputs the first −1, x = + 1 and z = + 1, and the PWM modulation circuit 3B inputs the first −1 at the timing of R ₄ and the clock CK.
_{When 1} is input, the decoder 33 outputs the control signal CD of “HH” because the (Y, y) input at that time is (−1, +2), and the analog switches SW _{10 to} SW ₃₀ are turned on.
Then, the latch circuit 32 outputs 1.

Next, when the ΔΣ modulation noise shaping circuit 2B outputs the second −1, x = 0 and z = 0, and the PWM modulation circuit 3B inputs the second −1 R ₅
When the clock CK ₁ is input at the timing of, the decoder 33 changes the input (Y, y) to (−1, +).
1) So, switching the analog switch SW ₁₀ to SW ₃₀ toward f by outputting a control signal CD for "HL", the latch circuit 32 outputs 0. When the ΔΣ modulation noise shaping circuit 2B outputs the third −1, x = −1, z =
+2 next, when the clock CK ₁ at the timing of R ₆ to PWM modulation circuit 3B inputs the third -1 is input, the decoder 33 is entered at that time (Y, y) are (-1, 0) So analog switch SW _{10 to} SW ₃₀
To the e side, and the latch circuit 32 outputs 2.

Next, when the ΔΣ modulation noise shaping circuit 2B outputs 0, x = + 2 and z = + 2, and P
When the clock CK ₁ is input at the timing of R _{7 when} the WM modulation circuit 3B inputs 0, the decoder 33 inputs (Y, y) at that time (0, +2), and therefore the analog switches SW _{10 to} SW. _{Leaving 30} on the e side, the latch circuit 32 outputs +2. When the ΔΣ modulation noise shaping circuit 2B outputs the first +1 x = + 3, z = 0
And the PWM modulation circuit 3B inputs the first +1 R
_{When the} clock CK ₁ is input at the timing of ₈ , the decoder 33 changes the input (Y, y) to (+1, +
Because of 2), the analog switches SW _{10 to} SW ₃₀ are switched to the g side, and the latch circuit 32 outputs 0.

Next, when the ΔΣ modulation noise shaping circuit 2B outputs the first +2, x = + 2 and z = + 2, and the PWM modulation circuit 3B inputs the first +2 R ₉
When the clock CK ₁ is input at the timing of, the decoder 33 changes the input (Y, y) to (+2, 0).
Therefore, the analog switches SW _{10 to} SW ₃₀ are switched to the e side, and the latch circuit 32 outputs 2. When the ΔΣ modulation noise shaping circuit 2B outputs the second +1, x = + 4, z = + 1, and the PWM modulation circuit 3B inputs the second +1 at the timing of R ₁₀ and the clock CK ₁
Is input, the decoder 33 switches the analog switches SW _{10 to} SW ₃₀ to the g side because the (Y, y) input at that time is (+2, +2), and the latch circuit 32 is +.
1 is output.

Next, when the ΔΣ modulation noise shaping circuit 2B outputs the third +2, x = + 3 and z = 0, and the PWM modulation circuit 3B inputs the third +2 R
_{When the} clock CK ₁ is input at the timing of ₁₁ , the decoder 33 inputs (Y, y) at that time to (+2, +
Because of 1), the analog switches SW _{10 to} SW ₃₀ are switched to the f side, and the latch circuit 32 outputs 0.

Thus, the switching control circuit 20B is
When the PWM circuit 3B is -3,0 inputs multilevel digital data Y of one of the values + 3, the analog switch SW ₁₀ to SW ₃₀ as a position e, a of the PWM modulation circuit 3B, b, c The PWM modulation signal corresponding to Y output from the terminal is divided into buffer amplifiers 4 ₁ ,
Input to 4 ₂ and 4 ₃ . On the other hand, when the PWM modulation circuit 3B inputs the multi-valued digital data Y having any value of -2, -1, +1, +2, the analog switch SW _10-
When the SW ₃₀ is interlocked and randomly switched to one position of e, f, g, and when switched to the f side, the PWM modulation signal corresponding to Y output from the terminals a, b, c of the PWM modulation circuit 3B. Buffer amplifier 4 ₂ for each system
When inputting to 4 ₃ and 4 ₁ and switching to g side, PW
The PWM modulation signals corresponding to Y output from the a, b, and c terminals of the M modulation circuit 3B are input to the buffer amplifiers 4 ₃ , 4 ₁ , and 4 ₂ for each system.

Assuming that the analog switches SW _{10 to} SW _{30 of} the switching circuit 10B are all fixed to the e side, the value of the multivalued digital data Y and the output point of the adder circuit 6B are checked. Average voltage E during the sampling period T (1 / 32f _S ) of the PWM modulation signal corresponding to Y
The relationship (Y, E) of (V) is P as shown in A of FIG.
₁ (-3, ₁ ), P ₂ (-2, 1.75), P ₃ (-
1, 2.33), P ₄ (0, 2.75), P ₅ (+1,
_{3.5), P 6 (+2,4.08)} , P 7 (+3,4.
5) and P ₁ , P ₄ , P ₇ ride on the straight line L,
P ₂ , P ₃ , P ₅ , and P ₆ deviate from the straight line L to the plus side of E by 0.167 (V). The original multi-valued digital data Y PWM-outputted during a certain period much longer than T, for example, 10T in FIG.
When changing from 2, -2, -1, -1, -1, 0, +1, +2, +2, 10 at the output point of the adder circuit 6B
The average voltage E ′ during T is 2.59 (V), which is larger than the ideal value by 0.131 (V).

Further, assuming that the analog switches SW _{10 to} SW _{30 of} the switching circuit 10B are all fixed to the f side, the value of the multivalued digital data Y and the output point of the adding circuit 6B are checked. The relationship (Y, E) of the average voltage E (V) during the sampling period T (1 / 32f _S ) of the PWM modulation signal corresponding to Y is Q ₁ (−3) as shown in B of FIG. , 1), Q ₂ (-2, 1.58), Q ₃
(−1,2), Q ₄ (0,2.75), Q ₅ (+1,
3.33), Q ₆ (+2, 3.75), Q ₇ (+3)
4.5), Q ₁ , Q ₂ , Q ₄ , Q ₅ , and Q ₇ ride on the straight line L, but Q ₃ and Q ₆ deviate from the straight line L to the minus side of E by 0.17 (V). The original multi-valued digital data Y PWM-modulated during a certain period much longer than T, for example, 10T in FIG.
When changing from −2, −1, −1, −1, 0, +1, +2, +2, the average voltage E ′ during 10T seen at the output point of the adding circuit 6B is 2.374 ( V), which is smaller than the ideal value by 0.085 (V).

Further, assuming that the analog switches SW _{10 to} SW _{30 of} the switching circuit 10B are all fixed to the g side, the value of the multivalued digital data Y and the output point of the adding circuit 6B are checked. The relationship (Y, E) of the average voltage E (V) during the sampling period T (1 / 32f _S ) of the PWM modulation signal corresponding to Y is as shown in C of FIG.
S ₁ (-3, ₁ ), S ₂ (-2, 1.42), S ₃ (-
1, 2.17), S ₄ (0, 2.75), S ₅ (+1,
3.17), S ₆ (+2, 3.92), S ₇ (+3)
4.5), S ₁ , S ₃ , S ₄ , S ₆ , and S ₇ ride on the straight line L, but S ₂ and S ₅ deviate from the straight line L to the minus side of E by 0.16 (V). The original multi-valued digital data Y PWM-modulated during a certain period much longer than T, for example, 10T in FIG.
When changing from −2, −1, −1, −1, 0, +1, +2, +2, the average voltage E ′ during 10T seen at the output point of the adder circuit 6 is 2.411 ( V), which is smaller than the ideal value by 0.048 (V).

However, in this embodiment, in the switching control circuit 20B, the PWM modulation circuit 3B is -3, 0, +.
When the multi-valued digital data Y of any value of 3 is input, the analog switches SW _{10 to} SW ₃₀ are set to the position of e, but the PWM modulation circuit 3B is -2, -1, +1,
When the multi-valued digital data Y of any value of +2 is input, the analog switches SW _{10 to} SW ₃₀ are interlocked and randomly switched to one position of e, f, g, so that the multi-valued digital data Y is 1 Each time data is input to the PWM modulation circuit 3B, the value of the multilevel digital data Y is converted into the average voltage E according to A of FIG.
It is converted into the average voltage E according to B of 0 or converted into the average voltage E according to C of FIG.

Therefore, PW is performed during 10T shown in FIG.
The original multilevel digital data Y output by M modulation is -3, -2, -2, -1, -1, -1, 0, +1, + in time series.
When it changes to 2, +2, the average voltage E ′ during 10T seen at the output point of the adding circuit 6B is 2.458 (V).
Becomes 0.001 (V) from the ideal value of 2.459 (V)
It is only small, and is closer to the ideal value than when there is no switching circuit 10B. The voltage averaged over a period longer than 10 T becomes closer to the ideal value.

The output of the adder circuit 6A is extracted by the analog low-pass filter 7 only as a component having a cut-off frequency f _C or less, which is slightly lower than f _S / 2, and is output as an analog audio signal. Analog low pass filter 7
The output of the added value of the PWM signal outputted from the three buffer amplifiers ₄₁ to ₃ back from the current time in the past, the sampling period of the multi-valued digital data T (= 1
/ 32f _s ) is averaged over a much longer period. Therefore, the buffer amplifier ₄₁ to the _third output voltage when H level or L level is input,
(5) even if there is a difference indicated to (8), that the combination of connection between the output terminal a~c the buffer amplifier ₄₁ to the _third PWM modulation circuit 3B is switched from time to time, analog low-pass filter 7 output becomes a value close substantially the same ideal as when there is no difference in the output voltage of the buffer amplifier ₄₁ to ₃ when H level or L level is input, D
The / A conversion accuracy is improved.

[0071] According to an aspect of this embodiment, PWM modulation circuit between the output terminal a~c the buffer amplifier ₄₁ to the _third 3B, PWM modulation circuit 3 lines of output and three buffer amplifiers 3B 4 A switching circuit 10B capable of switching a one-to-one connection with ₁ to 4 ₃ is provided, and the switching control circuit 20B follows a clock CK ₁ having a cycle of 1 / 32f _S synchronized with the PWM modulation operation of the PWM modulation circuit 3B. , Every time the multi-valued digital data Y other than the values −3, 0, and +3 at which the output of each system of the PWM modulation circuit 3B has the same pulse width is input to the PWM modulation circuit 3B, the three systems of the PWM modulation circuit 3B the combination of one-to-one connection between the output a~c and three buffer amplifiers 41 _{to 3} and to switch at random.

The analog low-pass filter 7 is an adder circuit 6
Because it has a function of averaging the output of B, the circuit constants of the buffer amplifier ₄₁ to _3, circuit characteristics, the variation in power supply voltage or the like if there are variations in the output voltage value between the buffer amplifier ₄₁ to ₃ also, the average voltage of the sum of the output of the buffer amplifier ₄₁ to ₃ in the D / a conversion operation becomes a value close to the case of operating in the absence of variation in the output voltage values of the respective buffer amplifiers, analog An output with extremely high D / A conversion accuracy can be obtained from the low-pass filter 7,
The ability of the D / A conversion device that the ΔΣ modulation noise shaping circuit 2B outputs seven values can be significantly increased.

In the embodiment shown in FIG. 6, the output of each system of the PWM modulation circuit 3B has the same pulse width.
Each time the multi-valued digital data Y other than 3, 0 and +3 is input to the PWM modulation circuit 3B, 3 of the PWM modulation circuit 3B is input.
The output outputs a to c of the system and the three buffer amplifiers 4 ₁ to 4 ₃ are randomly switched in a one-to-one connection combination, but the switch positions are e → f → g → e → f.
→ g → e → ... By switching, PWM modulation circuit 3
B outputs from three systems a to c and three buffer amplifiers 4 ₁ to
The combination of one-to-one connection with 4 ₃ is cyclically switched, and the switch position is e → g → f → e.
By switching from → g → f → e → ・ ・, the outputs ac of the three systems of the PWM modulation circuit 3B and the three buffer amplifiers 4
The combination of 1 to 1 connection with ₁ to 4 ₃ may be switched in a stepwise manner. Also, the cutoff frequency f _C of the Arona glow pass filter 7 may be set higher than f _S / 2 if it is 32 f _S / 2 or less (in this case,
The attenuation amount of the analog low pass filter 7 is, for example, 2f.
Set it to be about -90 dB at _{C or} 32 f _S
/ 2～32F at a certain frequency in the range of _S may be set to be about -90 dB).

The point is that the cutoff frequency f _C of the analog low-pass filter 7 is set smaller than 32 f _S / 2, and the output of each system of the PWM modulation circuit 3B has the same pulse width. Value digital data is PWM
Accumulated time when modulation output is performed (Y = -2 is P
Accumulated time when output by WM modulation, or Y
= -1 when PWM modulation output is cumulatively viewed, or when Y = +1 is PWM modulation output cumulatively, or when Y = +2 is PWM modulation output cumulatively to when viewed), the output of any system of the PWM circuit 3B also may be switched as input with approximately equal probability to the buffer amplifier ₄₁ to _3.

When multivalued digital data Y of values {-3, 0, +3} for which the outputs of the respective systems of the PWM modulation circuit 3B all have the same pulse width is input to the PWM modulation circuit 3B, the switching circuit 10B. Each analog switch SW ₁₀
Although the SW ₃₀ is always switched to the e position, it may be switched to the f or g position or may be left at the position immediately before.

Even when the PWM modulation circuit has m or more outputs of 4 or more and m or more buffer amplifiers, m analog switches each having m input terminals are similarly provided. It is possible to switch the output of the m-system of the PWM modulation circuit and the one-to-one connection of the m buffer amplifiers by a switch position so that the output of each system of the PWM modulation circuit has the same pulse width. Each time multi-valued digital data other than the above value is input to the PWM modulation circuit, the combination of the one-to-one connection between the m-system output of the PWM modulation circuit and the m buffer amplifiers is randomly or cyclically You may make it switch.

[0077]

According to the present invention, the variation of the output voltage value between the buffer amplifiers is changed by switching the combination of the output of the m system of the PWM modulation circuit and the one-to-one connection of the m number of buffer amplifiers. The average voltage of the added value of the outputs of the buffer amplifiers that cancel each other during the D / A conversion operation can be set to a value close to that when the output voltage values of the buffer amplifiers are operated without variation, and the analog low-pass filter D /
It is possible to obtain an output with high A conversion accuracy.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a D / A conversion device according to a first embodiment of the present invention.

FIG. 2 is a time chart explaining operations of the PWM modulation circuit, the switching circuit, and the switching control circuit in FIG.

FIG. 3 is a diagram illustrating the operation of the switching circuit of FIG.

FIG. 4 is a circuit diagram of a D / A conversion device according to a second embodiment of the present invention.

5 is a time chart explaining operations of the PWM modulation circuit, the switching circuit, and the switching control circuit in FIG.

FIG. 6 is a circuit diagram of a D / A conversion device according to a third embodiment of the present invention.

7 is a diagram illustrating an operation of the switching circuit of FIG.

FIG. 8 is an explanatory diagram illustrating an operation of the switching control circuit of FIG.

9 is a time chart explaining operations of the PWM modulation circuit, the switching circuit, and the switching control circuit in FIG.

10 is a diagram illustrating the operation of the switching circuit of FIG.

FIG. 11 is a circuit diagram of a conventional D / A conversion device.

FIG. 12 is a time chart illustrating the operation of FIG. 11.

13 is a diagram illustrating the operation of FIG. 11. FIG.

[Explanation of symbols]

1 oversampling circuit 2 and 2b .DELTA..SIGMA modulation noise shaping circuit 3A, 3B PWM modulation circuit ₄₁ to _third buffer amplifier 6A, 6B addition circuit 7 analog low-pass filter 10,10B switching circuit 20, 20A, 20B switching control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-4-21215 (JP, A) JP-A-3-104420 (JP, A) JP-A-5-327512 (JP, A) JP-A-5- 335963 (JP, A) JP-A-8-1554058 (JP, A) JP-A-9-186601 (JP, A) JP-A-10-308671 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 3/02 H03M 1/08 H03M 1/82

Claims (4)

(57) [Claims] 1. Multi-valued digital data having a sampling frequency F _S , which has n output values and has n values, is input, and the value of the multi-valued digital data and the output pulse width of each system are set to m. The PWM modulation circuit that performs PWM modulation so that the value added by the system is proportional to m, and m of the PWM modulation circuit
M buffer amplifiers that individually input the output of the system,
An adder circuit that adds the outputs of m buffer amplifiers and a cutoff frequency f that extracts the low-frequency component of the output of the adder circuit
_An analog low-pass filter with _C smaller than F _S / 2,
In the D / A conversion circuit including the, the combination of the one-to-one connection between the m-system output of the PWM modulation circuit and the m buffer amplifiers is fixed or variable switching higher than the cutoff frequency f _C of the analog low-pass filter. A D / A conversion circuit characterized in that a switching circuit for switching at a speed is provided. 2. The multi-valued digital data is data which is oversampled by an oversampling circuit and then passed through a ΔΣ modulation noise shaping circuit to be noise shaped by a ΔΣ modulation method. The described D / A conversion circuit. 3. Multi-valued digital data having a sampling frequency F _S , which has m number of output systems and takes n values, is input, and the value of the multi-valued digital data and the output pulse width of each system are set to m. The PWM modulation circuit that performs PWM modulation so that the value added by the system is proportional to m, and m of the PWM modulation circuit
M buffer amplifiers that individually input the output of the system,
An adder circuit that adds the outputs of m buffer amplifiers and a cutoff frequency f that extracts the low-frequency component of the output of the adder circuit
_An analog low-pass filter with _C smaller than F _S / 2,
A D / A conversion circuit including a switching circuit for switching a combination of 1-to-1 connection between the output of the m-system of the PWM modulation circuit and the m buffer amplifiers, and the switching circuit is provided for each system of the PWM modulation circuit. Whenever multi-valued digital data other than the values where the outputs of all have the same pulse width are input to the PWM modulation circuit, m of the PWM modulation circuit is input.
The D / A conversion circuit is characterized in that a combination of one-to-one connection between the system output and m buffer amplifiers is switched. 4. The multi-valued digital data is data which has been subjected to noise shaping by a ΔΣ modulation method after being oversampled by the oversampling circuit and then passed through a ΔΣ modulation noise shaping circuit. The described D / A conversion circuit.