KR20010055300A - High speed analog digital converter using counter - Google Patents

Abstract

PURPOSE: A high speed analog-to-digital converter is provided to convert an analog signal into a digital signal after generating a tooth wave according to an n-bit counted value and detecting the level of the analog signal according to the tooth wave. CONSTITUTION: A clock generator(10) generates a clock signal(CLK) of a predetermined period. An N-bit counter(20) performs an n-bit count operation in response to an output signal(CLK) of the clock generator(10). A tooth wave generator(30) generates a tooth wave in response to the counted value of the N-bit counter(20). An amplifier(40) inversely amplifies an output signal of the tooth wave generator(30) according to a ratio of resistors(60,70). A comparator(50) compares an analog signal(VIN) with the amplified tooth wave as a reference voltage. A latch part(80) latches an output of the N-bit counter(20) and outputs a digital signal(OUT) according to an output of the comparator(50).

Description

HIGH SPEED ANALOG DIGITAL CONVERTER USING COUNTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter, and more particularly, to a high speed AD converter using a counter that generates a sawtooth wave based on a value counted in N bits, and detects and converts an analog signal level according to the sawtooth wave into a digital signal. It is about.

FIG. 1 is a block diagram showing the structure of an AD converter using a conventional approximation register. As shown therein, an analog signal V _IN is compared according to a reference signal V _ref , and thus "high potential" or "low potential". Comparator 1 for outputting a; Sequential approximation that stores the output of the comparator 1 sequentially from the most significant bit (MSB) and then outputs it, and outputs it as a digital signal when the output of the comparator 1 is stored up to the least significant bit (LSB). A Successive Approximation Registor (SAR) 3; It consists of a digital-to-analog converter (2) for outputting the reference signal (V _ref ) obtained by converting the output of the step approximation register (3) into an analog signal to the comparator (1). do.

When the operation of the AD converter is first started, the outputs of the successive approximation registers 3 are all initialized to zero, and the output of the digital-to-analog converter 2 converts half of the power supply voltage VDD into the reference signal V _ref . To the negative terminal of the comparator 1.

Next, when the analog signal V _IN to be converted into a digital signal is input to the positive terminal of the comparator 1, the comparator 1 is analog signal V _IN according to the reference signal V _ref . a, in comparison here is less than the analog signal (V _iN) a reference signal (V _ref) than is greater on the "high potential", the analog signal (V _iN) a reference signal (V _ref) successively a "low potential" approximating Output to register (3).

Then, the successive approximation register 3 stores the output of the comparator 1 in the most significant bit MSB, reads it again, and outputs it to the digital-to-analog converter 2, and the digital-to-analog converter 2 This is converted into a new reference signal V _ref and output to the comparator 1.

The comparator 1 compares the analog signal V _IN with the new reference signal V _ref of the digital-to-analog converter 2 and outputs "high potential" or "low potential" according to the result. do.

Here, the output of the comparator 1 is output to the next bit of the most significant bit MSB of the successive approximation register 3, that is, the MSB-1 th bit, and then to the next digital-to-analog converter 2 to output a new reference signal V. _ref ), where the successive approximation register 3 repeats the above process until the data is stored in the least significant bit (LSB), and finally the value filled up to the least significant bit (LSB) is the analog signal ( V _IN ) becomes a digital signal converted to digital.

However, as described above, when the number of output bits of the AD converter increases, the digital-to-analog converter inside the AD converter must output a voltage corresponding to twice the desired number of bits, thereby implementing this as a MOS transistor. In this case, there is a problem that the output of the AD converter is limited and the area occupied by the AD converter increases during layout.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and generates a sawtooth wave based on a value counted in N bits, and uses a counter to detect and convert the level of an analog signal according to the sawtooth wave into a digital signal. The purpose is to provide a fast AD converter.

1 is a block diagram showing the configuration of an AD converter using a conventional approximation register.

2 is a block diagram showing the configuration of a fast AD converter using the present invention counter.

FIG. 3 is a waveform diagram showing an output waveform of each signal in FIG. 2; FIG.

*** Description of the symbols for the main parts of the drawings ***

10: clock generator 20: N bit counter

30: sawtooth generator 40: amplifier

50: comparator 60,70: resistance

80: latch portion

The present invention for achieving the above object is a clock generator for outputting a clock of a predetermined period; An N bit counter for binary counting N bits by the output of the clock generator; A sawtooth wave generator for receiving the output counted from the N-bit counter to generate a sawtooth wave; An amplifier for non-inverting and amplifying the output of the sawtooth generator to a predetermined level; A comparator for comparing a sawtooth wave amplified to a predetermined level by the amplifier as a reference voltage and an analog signal input thereto; And latching the counted output of the N-bit counter and then outputting it as a digital signal according to the output of the comparator.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a block diagram showing the configuration of the fast AD converter using the counter of the present invention, and a clock generator 10 for outputting a clock CLK of a predetermined period as shown therein; An N bit counter 20 for binary counting N bits by an output CLK of the clock generator 10; A sawtooth wave generator 30 for receiving the output counted by the N-bit counter 20 and generating a sawtooth wave; An amplifier (40) for non-inverting amplifying the output of the sawtooth generator (30) to a predetermined level in accordance with the ratio of resistors (60, 70); A comparator (50) for comparing the sawtooth wave amplified by the amplifier (40) to a reference voltage with an analog signal (V _IN ); According to the present invention configured to latch the output counted by the N-bit counter 20, and then output it as a digital signal OUT according to the output of the comparator 50, according to the present invention The operation and operation of one embodiment will be described in detail with reference to the accompanying drawings.

First, the N-bit counter 20 performs N-bit binary counting to output the counted value to the sawtooth generator 30 and the latch unit 80 by a clock CLK of a predetermined period output from the clock generator 10. At this time, the reset signal RST is disabled.

In this case, when the analog signal V _IN is digitally converted into an N bit digital signal OUT, the N bit counter 20 outputs a binary counted value through the N output terminals to the sawtooth generator 30. Assuming that the analog signal V _IN is converted into a 4-bit digital signal, the N-bit counter 20 is the same as that of FIG. 3 (b) for a clock CLK of a predetermined period as shown in FIG. Similarly, the clocked CLK multiplied by 2 times to the Nth output stage, the clocked CLK multiplied by 4 times to the N-1st output stage, the clocked CLK multiplied 8 times to the N-2nd output stage, N-3 The 16th multiplied clock CLK is output to the node A at the first output terminal.

That is, the N-bit counter 20 outputs a binary counted value through four output stages.

Then, the sawtooth generator 30 composed of the R-2R network receives the value counted to 4 bits from the N-bit counter 20 to generate a sawtooth wave, and the generated sawtooth wave through the node B the positive terminal of the amplifier 40 Output as (+).

Here, the sawtooth wave output from the sawtooth wave generator 30 is in the form of a dull sawtooth wave in which the ground voltage GND and the power supply voltage VDD are unstable, as shown in circle a and circle b in FIG. 40 non-inverts and amplifies the dull sawtooth wave to a predetermined level according to the ratio of the resistors 60 and 70 fed back to the negative terminal (-), and the positive terminal (+) of the comparator 50 through the node C. Will output

In this case, the comparator 50 receives the analog signal V _IN at the negative terminal (−) and the output of the amplifier 40 at the positive terminal (+), as shown in FIG. If the output of the signal 40 is higher than the analog signal V _IN , as shown in (e) of FIG. 3, "high potential" is output at the intersection point of the two signals and continues until another intersection point is met.

In addition, the latch unit 80 latches the counting output of the N-bit counter 20, and then, at the point in time when the comparator 50 outputs a "high potential", the latch unit 80 outputs a counting value corresponding to the point in time. )

That is, as shown in FIG. 3 (f), when the comparator 50 outputs "high potential", the latch unit 50 is a digital signal (11 (1011) "," 6 (0110) ", respectively. OUT) is output.

Therefore, when the N-bit counter 20 operates at high speed or increases the number of bits of the counting value, the high-resolution and high-speed AD converter can be implemented.

As described above, the present invention generates a sawtooth wave based on a value counted by N bits, detects a level of an analog signal according to the sawtooth wave, and converts the signal into a digital signal, thereby reducing the layout area of the AD converter and using a smaller layout area. There is an effect that the AD converter can be on chip.

Claims (1)

A clock generator for outputting a clock of a predetermined period; An N bit counter for binary counting N bits by the output of the clock generator; A sawtooth wave generator for receiving the output counted from the N-bit counter to generate a sawtooth wave; An amplifier for non-inverting and amplifying the output of the sawtooth generator to a predetermined level; A comparator for comparing a sawtooth wave amplified to a predetermined level by the amplifier as a reference voltage and an analog signal input thereto; And a latch unit configured to latch the counted output of the N-bit counter and output the digital signal according to the output of the comparator.