JPS61280670A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61280670A
JPS61280670A JP10207585A JP10207585A JPS61280670A JP S61280670 A JPS61280670 A JP S61280670A JP 10207585 A JP10207585 A JP 10207585A JP 10207585 A JP10207585 A JP 10207585A JP S61280670 A JPS61280670 A JP S61280670A
Authority
JP
Japan
Prior art keywords
film
diffusion
doped
semiconductor
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10207585A
Other languages
Japanese (ja)
Inventor
Tokuo Sekine
関根 徳男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10207585A priority Critical patent/JPS61280670A/en
Publication of JPS61280670A publication Critical patent/JPS61280670A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain diffused regions which have different depths in a same diffusion process by employing doped oxide which is doped with a high concentration impurity of the same conductive type. CONSTITUTION:After an opposite conductive type epitaxial layer 2 is deposited on a semiconductor substrate 1, a silicon oxide film 3 is formed and the first gate diffusion aperture 4 and the second gate diffusion aperture 5 are drilled. Then the first semiconductor films 6 are formed. After that, the second semiconductor film 7 which is doped with a high concentration impurity of the same conductive type is formed above the region for a deep diffused layer to be formed in the epitaxial layer 2. As a diffusion process is carried out after the doped oxide 7 which is doped with a high concentration impurity of the same conductive type is further formed on the polycrystalline silicon film 6 corresponding to a deep diffused layer 8, the quantity of the impurity is larger on this polycrystalline silicon film 6 than on the other polycrystalline silicon film 6 by the quantity of the impurity in the doped oxide 7 so that the diffused regions which have different depths can be obtained in the same diffusion process. Finally, after the diffusion process is carried out, the doped oxide film 7 is removed and the polycrystalline silicon films 6 to be used as electrodes 6 are etched to have the predetermined shapes.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は半導体装置の製造方法であり、特に同一基板内
に異なる拡散深さの領域を有する半導体装置の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device having regions of different diffusion depths within the same substrate.

(ロ)従来の技術 上述の如く本発明は同一基板内に異なる拡散深さの領域
を有する半導体装置の製造方法に関するもので、特にこ
こではデュアルゲート・ジャンクシ璽ン・FETを用い
て説明をする。
(B) Prior Art As mentioned above, the present invention relates to a method of manufacturing a semiconductor device having regions with different diffusion depths within the same substrate, and in particular, the explanation will be given here using a dual-gate junction FET. .

第4図に前記デュアルゲート・ジャンクシ田ン・FET
の断面図を示す。このFETの特徴は2つのゲート領域
を有し、第1ゲート(8)と第2ゲート(9)の拡散深
さが異なっており、こ、の拡散深さの差は精度良く制御
する必要がある。また微細パターンでかつ拡散が浅い構
造となっているので、前記2つのゲー・ト領域(8)(
9)形成には工夫が必要である。
Figure 4 shows the dual gate junction FET.
A cross-sectional view is shown. The feature of this FET is that it has two gate regions, and the diffusion depths of the first gate (8) and the second gate (9) are different, and this difference in diffusion depth must be precisely controlled. be. In addition, since the structure has a fine pattern and shallow diffusion, the two gate regions (8) (
9) Formation requires some ingenuity.

一般には第2図(イ)に示す如く一導電型の半導体基板
(1)に逆導電型のエピタキシャル層(2)を積層した
後、蝕刻法を用いて酸化膜(3)に第1ゲート拡散孔(
4)と第2ゲート拡散孔(5)を形成する。
Generally, as shown in Figure 2 (a), after laminating an epitaxial layer (2) of the opposite conductivity type on a semiconductor substrate (1) of one conductivity type, a first gate diffusion layer is formed in the oxide film (3) using an etching method. Hole (
4) and a second gate diffusion hole (5) are formed.

次に第2図(ロ)に示す如く第2ゲート拡散孔(5)に
不純物透過防止膜(ト)(例えばフォトレジスト)を被
覆し、P形不純物(例えばボロン)をイオン注入する。
Next, as shown in FIG. 2(B), the second gate diffusion hole (5) is covered with an impurity permeation prevention film (T) (eg, photoresist), and P-type impurities (eg, boron) are ion-implanted.

従って前記P形不純物は第1ゲート領域(8)のみにイ
オンが注入される。
Therefore, the P-type impurity ions are implanted only into the first gate region (8).

続いて第2図(ハ)に示す如く前記フォトレジスト(イ
)を除去した後に再度前記P形不純物を第1ゲート領域
(8)と第2ゲート領域(9)にイオン注入する。
Subsequently, as shown in FIG. 2(c), after removing the photoresist (a), the P-type impurity is ion-implanted into the first gate region (8) and the second gate region (9) again.

従って前記第1ゲート領域(8)と前記第2ゲート(9
)に注入されたイオン注入量に差が生じる。
Therefore, the first gate region (8) and the second gate region (9)
) there is a difference in the amount of ions implanted.

最後に第2図に)に示す如く熱拡散処理を施し、電極(
ロ)を形成する。従って第1ゲート領域(8)の方が第
2ゲート領域(9)より深く拡散できる。またこの拡散
深さの差はイオン注入量にて制御が可能である。
Finally, heat diffusion treatment is performed as shown in Figure 2), and the electrode (
b) to form. Therefore, the first gate region (8) can be diffused deeper than the second gate region (9). Further, this difference in diffusion depth can be controlled by changing the amount of ion implantation.

また別の方法として特公昭60−8623号公報(第3
図G())に示す如く一導電をの半導体基板(1)に逆
導電型のエピタキシャル層(2)を積層した後、蝕刻法
を用いて酸化膜(3)に第1ゲート拡散孔(4)と第2
ゲート拡散孔(5)を形成する。
Another method is Japanese Patent Publication No. 60-8623 (No. 3
As shown in FIG. ) and the second
A gate diffusion hole (5) is formed.

次に第3図(ロ)に示す如く前記半導体基板(2)上に
不純物を含まないポリシリコン(6)を積層した後、第
2ゲート領域(9)と対応する前記ポリシリコン膜(6
)上に不純物透過防止膜(ト)(例えばシリコン酸化膜
やフォトレジスト)を形成する。その後P形不純物をイ
オン注入する。ここで不純物透過防止膜(至)の下のポ
リシリコン(6)中に注入されるイオン量は相対的に少
なくなる。
Next, as shown in FIG. 3(b), polysilicon (6) containing no impurities is laminated on the semiconductor substrate (2), and then the polysilicon film (6) corresponding to the second gate region (9) is laminated on the semiconductor substrate (2).
) An impurity permeation prevention film (g) (for example, silicon oxide film or photoresist) is formed on the film. After that, P-type impurity ions are implanted. Here, the amount of ions implanted into the polysilicon (6) under the impurity permeation prevention film (6) becomes relatively small.

最後に第3図(ハ)に示す如く熱拡散処理を施し、電極
(6)としてはポリ、シリコン膜(6)を蝕刻してその
まま使う。
Finally, as shown in FIG. 3(C), thermal diffusion treatment is performed, and the poly-silicon film (6) is etched and used as it is as an electrode (6).

(ハ)発明が解決しようとする問題点 第2図(イ)乃至第2図(ロ)または第3図(イ)乃至
第3図(ハ)で説明した方式に於ては第1ゲート領域(
8)と第2ゲート領域(9)の拡散深さの制御は可能で
あるが下記の欠点を有している。
(c) Problems to be solved by the invention In the method explained in FIGS. 2(a) to 2(b) or FIGS. 3(a) to 3(c), the first gate region (
8) and the diffusion depth of the second gate region (9) can be controlled, but it has the following drawbacks.

まず第2図乃至第2図に)の方法に於ては(1)シリコ
ン基板(2)に直接イオン注入するので結晶欠陥を誘起
しリーク電流を増加させる、(2)ゲート拡散領域(8
)(9)が浅いのでアルミニウム・スパイクを発生しや
すい、(3)コストのかかるイオン注入を2回用いてい
る等の欠点を有している。
First, in the method shown in Figures 2 and 2), (1) ions are directly implanted into the silicon substrate (2), which induces crystal defects and increases leakage current;
) (9) is shallow, so aluminum spikes are likely to occur; and (3) costly ion implantation is used twice.

また第3図(イ)乃至第3図(ハ)の方法に於ては(1
)不純物透過防止膜(ト)はわずかな膜厚の差で半導体
基板(2)中へ入る不純物量が急激に変動するため、膜
厚の制御に精度が必要である、(2)第3図(ハ)の如
くポリシリコン膜(6)を電極として使うが、抵抗を小
さくするためにコストのかかるイオン注入を極めて多く
する必要がある等の欠点を有している。
Furthermore, in the methods shown in Figures 3 (a) to 3 (c), (1
) The impurity permeation prevention film (g) requires precision in controlling the film thickness because the amount of impurities entering the semiconductor substrate (2) changes rapidly due to a slight difference in film thickness. (2) Figure 3 Although the polysilicon film (6) is used as an electrode as in (c), it has drawbacks such as the need for extremely large amounts of costly ion implantation in order to reduce the resistance.

に)問題点を解決するための手段 本発明は斯る欠点を鑑みてなされたものであり、前記半
導体基板(2)上に形成された深い拡散領域(8)に対
応する一導電型の不純物をドーグした第1半導体膜(6
)上に更に同一導電型の高濃度の不純物をドープl〜だ
第2半導体膜(7)を付着した後に加熱処理をして前記
半導体膜(7)より前記半導体基板(2)へ拡散処理す
ることで解決するものである。
B.) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and includes an impurity of one conductivity type corresponding to the deep diffusion region (8) formed on the semiconductor substrate (2). The first semiconductor film (6
), a second semiconductor film (7) doped with impurities of the same conductivity type at a high concentration is deposited, and then heat treatment is performed to diffuse the semiconductor film (7) into the semiconductor substrate (2). This will solve the problem.

(ホ)作用 一導電をの不純物を適正濃度にドープした第1半導体膜
(6)、例えばポリシリコン膜に於て、前記半導体基板
(2)に形成される深い拡散領域(8)に対応する前記
ポリシリコン膜(6)上に更に同一導電型の高濃度の不
純物をドープした第2半導体膜(7)、例えばドープド
・オキサイドを付着した後に拡散処理をすると、前記深
い拡散領域(8)を形成する拡散源の方がドープド・オ
キサイドの分だけ不純物量が多いため、同一拡散で深さ
の異なる拡散領域が可能となる。
(e) A first semiconductor film (6) doped with conductive impurities at an appropriate concentration, for example a polysilicon film, corresponding to the deep diffusion region (8) formed in the semiconductor substrate (2). When a second semiconductor film (7) doped with impurities of the same conductivity type at a high concentration, for example, doped oxide, is deposited on the polysilicon film (6) and then subjected to a diffusion process, the deep diffusion region (8) is formed. Since the diffusion source to be formed has a larger amount of impurities corresponding to the doped oxide, diffusion regions with different depths can be formed by the same diffusion.

一方前記ポリシリコン膜(6)上部に形成された第2半
導体膜(7)は第1半導体膜(6)からのアウト・ディ
フユージ冒ン防止膜となり、かつ前記第2半導体膜(7
)から高濃度の不純物が第1半、導体膜(6)へ拡散さ
れるので電極(6)となる第1半導体膜(6)のシート
抵抗を小さくすることができる。
On the other hand, the second semiconductor film (7) formed on the polysilicon film (6) serves as an out-diffusion prevention film from the first semiconductor film (6), and the second semiconductor film (7)
) is diffused into the first half, the conductor film (6), so that the sheet resistance of the first semiconductor film (6), which becomes the electrode (6), can be reduced.

またイオン注入をしないので結晶欠陥の発生がなくリー
ク電流やアルミニウム・スパイクの発生を防止する。
Furthermore, since ion implantation is not performed, no crystal defects occur, and leakage current and aluminum spikes are prevented.

(へ)実施例 以下に本発明に関する半導体装置の製造方法の一実施例
を第1図(イ)乃至第1図(ハ)を参照しながら説明す
る。ここではデュアル・ゲート・ジャンクション・FE
Tを用いて説明するが、他の半導体装置でも同様である
(F) Embodiment An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 1(A) to 1(C). Here, dual gate junction FE
Although the description will be made using T, the same applies to other semiconductor devices.

第1図(イ)に示す如くまず一導電型の半導体基板(1
)に逆導電型のエピタキシャル層(2)を積層した後、
熱酸化法等を用いて前記半導体基板(2)上にシリコン
酸化膜(3)を形成し、写真蝕刻法を用いて前記シリコ
ン酸化膜(3)に第1ゲート拡散孔(4)と第2ゲート
拡散孔(5)を開孔する。
As shown in FIG. 1(a), first, a semiconductor substrate of one conductivity type (1
) after laminating an epitaxial layer (2) of opposite conductivity type,
A silicon oxide film (3) is formed on the semiconductor substrate (2) using a thermal oxidation method or the like, and a first gate diffusion hole (4) and a second gate diffusion hole (4) are formed in the silicon oxide film (3) using a photolithography method. A gate diffusion hole (5) is opened.

次に第1図(ロ)に示す如く前記半導体基板(2)上に
一導電型の不純物、例えばボロンをドープした第1半導
体膜(6)、例えばポリシリコン膜を形成する。
Next, as shown in FIG. 1(B), a first semiconductor film (6), such as a polysilicon film, doped with an impurity of one conductivity type, such as boron, is formed on the semiconductor substrate (2).

その後前記半導体基板(2)に形成される深い拡散領域
(ここでは第1ゲート領域(8)に対応するポリ・ンリ
コン膜(6))上に更に同一導電製の不純物であるボロ
ンを高濃度にドープした第2半導体膜(7)、例えばド
ープド・オキサイド膜を形成する。
After that, boron, which is an impurity made of the same conductivity, is further added to a high concentration on the deep diffusion region (in this case, the polyimide film (6) corresponding to the first gate region (8)) formed in the semiconductor substrate (2). A second doped semiconductor film (7) is formed, for example a doped oxide film.

本工程は本発明の特徴とするところであり深い拡散領域
(8)に対応する前記ポリシリコン膜(6)上に更に同
一導電型の筒績度の不純物をドープしたドープド・オキ
サイド(7)を付着した後に拡散処理をするので、この
ドープド・オキサイド内の不純物量だけ多くなり、同一
拡散で深さの異なる拡散が可能となる。
This step is a feature of the present invention, in which a doped oxide (7) doped with an impurity of the same conductivity type is deposited on the polysilicon film (6) corresponding to the deep diffusion region (8). Since the diffusion process is performed after this, the amount of impurities in the doped oxide increases, making it possible to perform diffusion to different depths with the same diffusion.

またイオン注入をしないので結晶欠陥の発生がなくリー
ク電流を防止できる。更にはポリシリコンを使用するこ
とにより、電極形成によるアルミニウム・スパイクの発
生も防止できる。
Furthermore, since ion implantation is not performed, no crystal defects occur and leakage current can be prevented. Furthermore, by using polysilicon, it is possible to prevent aluminum spikes from occurring due to electrode formation.

最後に第1図(ハ)に示す如く拡散処理をした後にドー
プド・オキサイド(7)を除去し、電極(6)として使
う前記ポリシリコン(6)を所定の形状に蝕刻する。
Finally, after performing a diffusion process as shown in FIG. 1(C), the doped oxide (7) is removed and the polysilicon (6) used as the electrode (6) is etched into a predetermined shape.

本工程は本発明の特徴とするところであり、前記ポリシ
リコン膜(6)上に形成されたドープド・オキサイド(
7)は第1半導体膜(6)の不純物が外部へ出てゆく、
いわゆるアウト・ディフュージョン防止膜となる。また
ドープド・オキサイド(7)内の不純物の一部は電極(
6)となるポリシリコン膜(6)内へ拡散されるため、
このポリシリコン膜(6)のシート抵抗をより小さくす
ることができる。
This step is a feature of the present invention, in which the doped oxide (
7) is when impurities in the first semiconductor film (6) go out to the outside.
It becomes a so-called out-diffusion prevention film. Also, some of the impurities in the doped oxide (7) are absorbed by the electrode (
6) because it is diffused into the polysilicon film (6),
The sheet resistance of this polysilicon film (6) can be further reduced.

(ト)発明の効果 本発明は以上の説明からも明らかな如<、(1)同一導
電型の高濃度の不純物をドープしたドープド・オキサイ
ド(7)を使用することで同一拡散で深さの異なる拡散
が可能となる。(2)イオン注入をしないため結晶欠陥
の発生がなくリーク電流を防止できる。また電極形成に
よるアルミニウム・スパイクの発生も防止できる。更に
はイオン注入をしないためコストの低下が可能となる。
(G) Effects of the Invention As is clear from the above description, the present invention has the following advantages: (1) By using doped oxide (7) doped with highly concentrated impurities of the same conductivity type, the depth can be increased by the same diffusion. Different diffusions are possible. (2) Since ion implantation is not performed, no crystal defects occur and leakage current can be prevented. It is also possible to prevent aluminum spikes from occurring due to electrode formation. Furthermore, since no ion implantation is required, costs can be reduced.

(3)またドープド・オキサイド(7)はポリシリコン
膜(6)のアウト・ディフュージョン防止膜となるため
、ポリシリコン膜(6)の不純物を有効に活用できる。
(3) Furthermore, since the doped oxide (7) serves as an out-diffusion prevention film for the polysilicon film (6), the impurities in the polysilicon film (6) can be effectively utilized.

(4)ドープド・オキサイド(7)の不純物がポリシリ
コン膜(6)内へ拡散をするためシート抵抗をより小さ
くすることができる。(5)また不純物透過防止膜←O
は厚膜精度を必要としたが本発明に於ては精度を必要と
せず製造工程を簡略化できる。
(4) Since the impurity of the doped oxide (7) diffuses into the polysilicon film (6), the sheet resistance can be further reduced. (5) Also, impurity permeation prevention film←O
Although thick film precision was required in the present invention, precision is not required in the present invention and the manufacturing process can be simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(イ)乃至第1図(ハ)は本発明の一実施例であ
る拡散深さの異なる領域をもつ半導体装置の製造方法を
示す断面図、第2図(イ)乃至第2図に)および第3図
(イ)乃至第3図(ハ)は従来用いられた拡散深さの異
なる領域をもつ半導体装置の製造方法を示す断面図、第
4図はデュアル・ゲート・ジャンクションFETである
。 主な図番の説明 (1)は−導電型の半導体基板、 (2)は逆導電型の
エピタキシャル層、(3)はシリコン酸化膜、 (4)
は第1ゲート拡散孔、(5)は第2ゲート拡散孔、(6
)は第1半導体膜、 (7)は第2半導体膜、 (8)
は第1ゲート領域、 (9)は第2ゲート領域である。 出願人 三洋電機株式会社 外1名 代理人 弁理士  佐 野 静 夫 第1図イ 第1図口 第1図ハ 第2図イ 第2図口 第2図二 第3図イ 第31″lO1゜  6 第3図ハ δ     9 隼4図
1(A) to 1(C) are cross-sectional views showing a method for manufacturing a semiconductor device having regions with different diffusion depths, which is an embodiment of the present invention, and FIGS. 2(A) to 2(C) ) and FIGS. 3(a) to 3(c) are cross-sectional views showing a conventional method for manufacturing a semiconductor device having regions with different diffusion depths, and FIG. be. Explanation of the main drawing numbers (1) is - conductivity type semiconductor substrate, (2) is opposite conductivity type epitaxial layer, (3) is silicon oxide film, (4)
is the first gate diffusion hole, (5) is the second gate diffusion hole, and (6) is the second gate diffusion hole.
) is the first semiconductor film, (7) is the second semiconductor film, (8)
is the first gate region, and (9) is the second gate region. Applicant Sanyo Electric Co., Ltd. and 1 other representative Patent attorney Shizuo Sano 6 Figure 3 C δ 9 Hayabusa Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)所定の不純物をドープした半導体膜を用いて半導
体基板内に少なくとも2つ以上の拡散深さの異なる拡散
領域を形成する半導体装置の製造方法に於いて、前記半
導体基板上に形成される深い拡散領域に対応する一導電
型の不純物をドープした第1半導体膜上に更に同一導電
型の高濃度の不純物をドープした第2半導体膜を付着し
た後に加熱処理をして前記半導体膜より前記半導体基板
へ拡散処理することを特徴とした半導体装置の製造方法
(1) In a method for manufacturing a semiconductor device, in which at least two diffusion regions having different diffusion depths are formed in a semiconductor substrate using a semiconductor film doped with a predetermined impurity, the semiconductor device is formed on the semiconductor substrate. A second semiconductor film doped with impurities of the same conductivity type at a high concentration is deposited on the first semiconductor film doped with impurities of one conductivity type corresponding to the deep diffusion region, and then heat-treated to make the semiconductor film thinner than the semiconductor film. A method for manufacturing a semiconductor device characterized by performing a diffusion process on a semiconductor substrate.
JP10207585A 1985-05-14 1985-05-14 Manufacture of semiconductor device Pending JPS61280670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10207585A JPS61280670A (en) 1985-05-14 1985-05-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10207585A JPS61280670A (en) 1985-05-14 1985-05-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61280670A true JPS61280670A (en) 1986-12-11

Family

ID=14317650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10207585A Pending JPS61280670A (en) 1985-05-14 1985-05-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61280670A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008053534A (en) * 2006-08-25 2008-03-06 Sanyo Electric Co Ltd Junction type fet and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008053534A (en) * 2006-08-25 2008-03-06 Sanyo Electric Co Ltd Junction type fet and manufacturing method thereof

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