JPS60140763A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control a distance between a gate electrode and a high impurity- concentration region easily while obtaining a drain region, etc. through double diffusion by diffusing and forming a shallow low impurity-concentration region to the surface layer section of a semiconductor substrate on both sides of the gate electrode while using the gate electrode shaped on the substrate as a mask, oxidizing the gate electrode and diffusing and forming the deep high impurity- concentration region while employing an oxide film shaped on the side wall of the gate electrode as a mask. CONSTITUTION:A gate oxide film 12, a polycrystalline Si film 13, an SiO2 film 14 and an oxidation-resistance film 15 are laminated and applied on a P type Si substrate 11, the laminated films are formed to a predetermined pattern, and the films 15 and 14 are removed to expose the film 13. N<-> type implantation layers 16 are shaped through ion implantation while using the film 13 as a mask, and an SiO2 film 17 is formed extending over the surfaces of the implantation layers 16 from a side wall under the film 13 through heat treatment in a high-temperature high-pressure oxygen atmosphere. N type ions are implanted while using the films 13 and 17 as masks, and deep N<+> type source region 18 and drain region 19 coupled with previously formed shallow implantation layers 16 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing fine elements useful for semiconductor devices, particularly for high-density, highly integrated semiconductor devices.

Conventional Structures and Problems Semiconductor devices have recently become more densely packed and have higher performance, and as a result, there has been an increasing demand for the development of semiconductor devices with fine structures. Conventionally, the source and drain of a MOS type semiconductor device are generally formed by diffusing a predetermined type of impurity having a conductivity type opposite to that of the substrate. The distance between the source and drain, that is, the gate length, has become finer, especially 2μ.
In the short channel MO8 of less than m, the gate voltage to cut off the current between the source and the drain becomes high, and high energy electrons (hot electrons) are injected from the drain region through the thin gate oxide film, and the source, There was a problem in changing the gate voltage to control the current between the drains. In order to solve this problem, impurities are doubly diffused into the source and drain regions.

In other words, a low concentration impurity diffusion layer is formed in the area in contact with the gate electrode to prevent hot electron effects and short channel effects, and a high concentration impurity layer is formed in other areas to lower the resistance of the source and drain regions. A method of forming layers in layers has been proposed.

A method of manufacturing the MO3 type semiconductor device having the double diffusion layer described above will be explained below with reference to FIGS. 1 and 2. 1st
In the figure, after forming a gate oxide film 2 and a gate electrode 3 such as a polycrystalline silicon film on a semiconductor substrate 1 of -conductivity type, e.g., P-type, using them as a mask, impurities of the opposite conductivity type to the substrate in the phosphorus corner are reduced. Impurity diffusion layer 4
(A).

Next, after forming an insulating film 6 such as a silicon dioxide film on the entire surface,
The insulating film 5 is etched by a so-called anisotropic dry etching method in which the etching rate is high only in the vertical direction. At this time, since the insulating film 6 is thick from the surface of the substrate 1 at the end of the gate electrode pattern, the insulating film 5 on the flat part of the substrate 1 is etched to expose the semiconductor substrate 1. After that, the insulating film 6 is also formed on the edge of the gate electrode pattern.
Part 6 remains. Using the gate electrode 3' and the insulating film 6 as a mask, an impurity such as arsenic is diffused at a high concentration to form a low resistance impurity layer 7 (B). Next, interlayer insulating film 8 and metal wiring 9 are formed (C).

In this method, the distance between the high concentration impurity layer 7 and the gate electrode 3' is determined by the total thickness of the gate oxide film and the gate electrode, the thickness of the insulating film 5, and the amount of anisotropic etching. It was difficult to form the distance to an arbitrary length with good reproducibility.

As another method, as shown in FIG.
Then, a high concentration impurity layer 7 is formed using the photosensitive resin film or insulating film 1o formed on the gate electrode as a mask (
A). Next, after etching the mll wall of the gate electrode 3 to make the pattern 1 of the gate electrode 3' narrower (B), the upper insulating film 10 is removed, and a low concentration layer is formed using the gate electrode pattern 3I as a mask. There is a method of forming the impurity layer 4 (C). In this method, the distance between the gate electrode 31 and the high concentration diffusion layer is
Since it is determined by the etching amount of the side wall of the gate electrode 3, there is a problem that it is difficult to form it with good reproducibility.

Purpose of the Invention In view of these conventional drawbacks, the present invention provides a method for manufacturing a semiconductor device having a double diffusion doin, which allows easy control of the distance between the gate electrode and the high concentration diffusion region, and which can be formed with good reproducibility. The purpose is to provide

Structure of the Invention The present invention involves forming a low concentration impurity layer on a substrate using a polycrystalline silicon gate electrode pattern as a mask, and then forming the impurity layer in a high-pressure oxidizing atmosphere or the like in which the oxidation rate of the polycrystalline silicon is faster than the spread of the impurity layer. The method is characterized in that after the sidewalls of the polycrystalline silicon electrode pattern are oxidized, a high concentration impurity layer is formed on the substrate using the oxidized electrode pattern and the oxidized sidewalls as a mask to form the source and drain.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. The oxidizable film 16 is sequentially formed (A). Next, after forming a predetermined pattern on the multilayer film, an impurity of a conductivity type opposite to that of the substrate, such as arsenic, is implanted using an ion implantation method to form a low concentration impurity layer 16.
The Monkey that forms the Monkey). The substrate is treated in a high-temperature, high-pressure oxygen atmosphere to form a silicon dioxide film 17 on the sidewall of the polycrystalline silicon film 13.
form. At this time, the polycrystalline silicon film pattern width is narrowed on one side by an amount equivalent to approximately the thickness of the sidewall silicon oxide film.
The total pattern width of the polycrystalline silicon film and the sidewall silicon oxide film is wider than the polycrystalline silicon film pattern width before oxidation. The thickness of the film 17 formed in this step can be formed with good controllability. Next, using the polycrystalline silicon film pattern 13 that will become the gate electrode and the sidewall silicon oxide film 17 as a mask, impurities of the opposite conductivity type to the substrate, such as phosphorus, are implanted, and the source and drain 18.1
(C) Next, the oxidation-resistant film 15 is removed.D) An opening is formed in the silicon dioxide film 20 on the semiconductor substrate, and a wiring layer 21 is formed to form a semiconductor device. Do (E
).

The second embodiment will be explained with reference to FIG. 4.

- Sequentially forming a silicon dioxide film 12, a polycrystalline silicon film 13, and an oxidation-resistant film 15 on a conductive semiconductor substrate 11 (A)
. A predetermined pattern is formed on the three-layer film (B).

Next, the polycrystalline silicon film pattern 13 is placed in a high temperature oxygen atmosphere.
A silicon dioxide film 17 is formed on the sidewalls and the exposed semiconductor substrate, and using the polycrystalline silicon film pattern/13 and the sidewall silicon oxide film 17 as a mask, a high concentration impurity layer of the opposite conductivity type to that of the substrate is formed to form the source, drain 18. form 19. Next, the sidewall silicon oxide film 17 is removed, and the polycrystalline silicon film pattern 1 is removed.
3 as a mask, an impurity layer 16 of a conductivity type opposite to that of the substrate is formed at a low concentration (D). It goes without saying that at this time, the oxidation-resistant film 15 may be left and used as a mask when forming the impurity layer. Next, an interlayer insulating film 3 such as a silicon dioxide film is applied to the entire surface.
0 and after forming an opening, a wiring layer 21 is formed to form an MO8 type conductor device shown in (E).

Effects of the Invention In the method of the present invention, unlike conventional methods, the distance between the high concentration impurity layer and the gate electrode is determined by the sidewall arsenic oxide film of the polycrystalline gate electrode. The film thickness can be formed arbitrarily with good reproducibility. Also,
In particular, in the second embodiment, since the low concentration impurity layer is formed using the gate electrode as a mask, there is little overlap between the impurity layer and the gate electrode, and a semiconductor device with good characteristics can be obtained.

[Brief explanation of drawings]

Figures 1 (A) to (C) and Figures 2 (A) to (c) are cross-sectional views of the manufacturing process of a conventional MOS transistor having a double diffusion layer; Figures 3 (A) to (E); 4(A) to (E) are sectional views showing the manufacturing process of the embodiment of the present invention of the same transistor. 11... Semiconductor substrate, 13... Polycrystalline silicon film pattern, 16... Impurity layer, 17...
...Side wall silicon oxide film, 18.19...Source, drain region. Name of agent Patent attorney Toshio Nakao 1 person 6 8 Figure 3 11;

Claims (1)

[Claims] a step of forming a low concentration impurity layer on the semiconductor substrate using a predetermined pattern of the gate electrode formed on the semiconductor substrate as a mask; a step of oxidizing the gate electrode; and a gate formed on the gate electrode and the sidewalls of the gate electrode. 1. A method of manufacturing a semiconductor device, comprising: forming a highly concentrated impurity layer using an oxide film of an electrode as a mask.