JPH02278737A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve current driving capacity by expanding a gate electrode consisting of a first conductive film and a second conductive film up to the upper part of an n<-> diffusion layer consisting of a first impurities. CONSTITUTION:A phosphorus-implantation layer 6 is formed within a silicon substrate 1 through a first polysilicon film 3 and a gate oxide film 2, phosphorus is doped to a second polysilicon film 7 and a first polysilicon film 3 for eliminating a damaged layer 4, phosphorus is activated for the phosphor-implantation layer 6 within the silicon substrate 1 for forming the n<-> diffusion layer 6'. Then, for a second polysilicon film 7 and a first polysilicon film 3, the gate oxide film 2 is exposed by reactive ion etching, arsenic ion is implanted with the first polysilicon film 3 and the second polysilicon film 7 of the gate electrode as a mask for forming an arsenic implantation layer 8, and arsenic is activated and diffused to form an n<+> diffusion layer 8'. Thus, an n<-> diffusion layer 6' is formed at the inside of the gate electrode, thereby preventing hot carrier resistance from being reduced.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing an LDD-MOSFET.

(Prior art) The conventional manufacturing method of LDD-MOSFET is shown in Fig. 2 (a).
) to (e) illustrate examples of n-channel type.

First, as shown in FIG. 2(a), a P-type silicon substrate 1
A gate oxide film 12 and a gate electrode 13 made of a polysilicon film are formed on the silicon substrate 11, and using the gate electrode as a mask, phosphorus ions are introduced into the silicon substrate 11 at a dose of 1013 aa.
A phosphorus implantation layer 14 is formed by implanting ions to a depth of about -".

Next, as shown in FIG. 2B, the silicon substrate 11 is heat-treated to activate the implanted phosphorus to form an n-diffusion layer 14', and then to form an n-diffusion layer 14' on the gate electrode 13 and gate oxide film 12. A CVD oxide film 15 is then formed.

Next, the CVD oxide film 15 is etched by anisotropic etching to form a side wall 15' on the side wall of the gate electrode 13, as shown in FIG.

Using the same sidewall 15' as a mask, arsenic ions are implanted into the silicon substrate at a dose of about 10''a++-'' to form an arsenic implanted layer 16. FIG. 2(d) is a cross-sectional view showing the state after arsenic ion implantation.

Finally, the silicon substrate 11 is heat treated to activate the implanted arsenic and form an n'' diffusion layer 16', completing the LDD-MOSFET shown in FIG. 2(8).

(Problems to be Solved by the Invention) However, when an LDD-MOSFET is manufactured using the conventional manufacturing method as shown in FIG.

Since a part of the n-diffusion layer is formed outside the gate electrode, there are disadvantages such as a decrease in current driving ability and a decrease in hot carrier resistance.

(Means for Solving the Problems) The present invention has been made to solve the above problems, and includes a step of forming a first conductive film on a conductive type semiconductor substrate via an insulating film. , a step of forming a damaged layer in the surface side region of the first conductive film by ion implantation, a step of removing a desired region of the damaged layer by anisotropic etching, and a step of removing the damaged layer. ion-implanting a first impurity of a conductivity type opposite to that of the substrate into the semiconductor substrate through the first conductive film and the insulating film; and implanting a second conductive impurity onto the remaining first conductive film. a step of anisotropically etching the second conductive film and the first conductive film until the insulating film in the region into which the first impurity is implanted is exposed; The method further includes a step of ion-implanting a second impurity having a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the first and second conductive films as masks.

(Function) In the method for manufacturing a semiconductor device of the present invention, it is possible to extend the gate electrode made of the first conductive film and the second conductive film to the top of the n-diffusion layer made of the first impurity. Become.

(Example) N-channel type LDD by the method of manufacturing a semiconductor device of the present invention
- An example of fabricating a MOSFET is shown in FIG.

As shown in FIG. 1(a), a P-type silicon substrate 1 is thermally oxidized to form a gate oxide film 2 with a thickness of approximately 200 densities, and then a first polyimide film 2 with a thickness of approximately 4000 densities is formed by low pressure CVD. In the first step to form the silicon film 3, phosphorus ions are accelerated onto the first polysilicon film 3 at an energy of approximately 200 keV and a dose of approximately I.
The damage layer 4 is formed from the surface of the first polysilicon film 3 to a depth of approximately 3,000 nm by implanting under the condition of "X 10101 sa".

Next, as shown in FIG. 1(b), a photoresist 5 as an etching mask is formed on the damaged layer 4 by a normal lithography method.

Next, as shown in FIG. 1(C), using the photoresist 5 as a mask, the damaged layer 4 is removed by reactive ion etching.
Etch almost vertically. At this time, by utilizing the difference in etching speed between the polysilicon film damaged by ion implantation and the undamaged polysilicon film, it is possible to terminate the etching when the damaged layer 4 is almost completely removed. Become. Since the thickness of the damaged layer 4 formed by ion implantation is uniform, it is possible to leave the first polysilicon film 3 of uniform thickness after etching by utilizing the above-mentioned difference in etching speed.

In the case of this embodiment, the thickness of the first polysilicon film 3 remaining after removing the damaged layer 4 is about 1000. After this, with the photoresist 5 remaining, phosphorus ions are accelerated at an energy of about 120 keV and a dose of about 1X10''C1.
Phosphorus is injected into the silicon substrate 1 through the remaining first polysilicon film 3 and gate oxide film 2 under conditions of 1-'' to form a phosphorus injection layer 6.

Next, after removing the photoresist 5, as shown in FIG.
A polysilicon film 7 is formed by a low pressure CVD method, and then heat-treated at a temperature of about 900° C. in a POCC3 atmosphere to add phosphorus to the second polysilicon film 7 and first polysilicon film 3 by about 10 am-. Dope. At this time, damage to the damaged layer 4 is removed by heat treatment. Further, phosphorus is activated in the phosphorus injection layer 6 in the silicon substrate 1 and becomes an n- diffusion layer.

Next, the second polysilicon film 7 and the first polysilicon film 3 are etched anisotropically by about 3,000 times using reactive ion etching, and the etching is terminated when the gate oxide film 2 is exposed. FIG. 1(e) is a diagram showing the state after this, in which the remaining first polysilicon film 3 and second polysilicon film 7 become the gate electrode of the MOSFET. The gate length of this gate electrode is approximately as shown in Figure 1(c).
The width of the remaining damaged layer 4 (=width of the photoresist 5) is twice the thickness of the second polysilicon film 7.

In the case of this embodiment, if the photoresist widths are o, s, and m, the gate length is 0.8+0.2X 2 =1.2-. Also, gate fi! The thickness of pi is approximately 3,000 people.

Next, as shown in FIG. 1(f), using the gate electrode (first polysilicon film 3 and second polysilicon film 7) as a mask, arsenic ions are accelerated at an energy of about 60 keV and a dose of about 5 XIO"am- (Arsenic is implanted into the silicon substrate 1 under conditions 71 to form the arsenic implanted layer 8.

Finally, the silicon substrate 1 is heat-treated at a temperature of about 900° C. to activate and diffuse the implanted arsenic to form an n+ diffusion layer 8'.
MOSFET is completed.

(Effect of the invention) As is clear from the above explanation, according to the present invention, FIG.
This has the effect of easily manufacturing an LDD-MOSFET in which an n-diffusion layer is formed inside the gate electrode as shown in g).

[Brief explanation of drawings]

Figures 1(a) to (g) show LDD-MOSFETs of the present invention.
Fig. 2 (a) is a process-order cross-sectional view for explaining the manufacturing method of
) to (a) are step-by-step cross-sectional views for explaining a conventional method for manufacturing an LDD-MOSFET. 1...Silicon substrate, 2...Gate oxide film,
3... First polysilicon film, 4... Damage layer,
5... Photoresist, 6... Phosphorus injection layer, 6'... n'' diffusion layer, 7... Second polysilicon film, 8... Arsenic injection layer, 8'... n
o Diffusion layer. Patent applicant Matsushita Electronics Co., Ltd. Figure 2

Claims (1)

[Claims] A step of forming a first conductive film on a semiconductor substrate of one conductivity type via an insulating film, a step of forming a damaged layer on the surface side region of the first conductive film by ion implantation, a step of anisotropically etching and removing a desired region of the layer; and a step of etching a first conductive film having a conductivity type opposite to that of the substrate into the semiconductor substrate through the first conductive film from which the damaged layer has been removed and the insulating film. a step of ion-implanting an impurity, a step of forming a second conductive film on the remaining first conductive film, and a step of forming the second conductive film and the first conductive film into Anisotropic etching is performed until the insulating film in the region where the impurity is implanted is exposed, and a second conductive film of a conductivity type opposite to that of the substrate is etched into the semiconductor substrate using the remaining first and second conductive films as masks. 1. A method for manufacturing a semiconductor device, comprising the step of ion-implanting an impurity.