JPH04297037A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent an offset of a transistor due to a gate bird's beak and to prevent a punch through by increasing a gate strength and an element isolation strength. CONSTITUTION:A polycrystalline silicon film 3 is deposited on a semiconductor substrate 1 and then a silicon dioxide film is formed and a side wall 5 which is constituted of a silicon nitride film is formed on the side face of the silicon dioxide film. An exposed area of the polycrystalline silicon film 3 and the semiconductor substrate 1 under the silicon nitride film 5 are gate-oxidized simultaneously and then a gate electrode 7 is buried in there. The silicon dioxide film is removed with the polycrystalline silicon film 3 formed first being used as a stopper and thus a buried gate MOSFET is fabricated.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a semiconductor device including a fine buried gate type MOSLSI and a method for manufacturing the same.

0003

2. Description of the Related Art Along with the miniaturization of MOSLSIs, gate oxide films are becoming thinner. Therefore, how to form a gate electrode with a fine line width on a thin gate oxide film will become important in the future. Buried gate type M
OSFET is promising. 9 and 10 show a typical manufacturing method of a buried gate type MOSFET. The outline and problems that occur during the manufacturing process will be explained below with reference to FIGS. 9 and 10.

FIGS. 9 and 10 show the MOSFE of MOSLSI.
It shows a cross-sectional view of the T portion. An element isolation oxide film 52 is formed in the element isolation region on a P-type silicon substrate 51, and a polycrystalline silicon thin film 54 is formed in the element part through the thermal oxide film 53 and in the element isolation region through the element isolation oxide film 52.
is formed all over. A CVDSiO2 film 55 is stacked thereon, and the CVDSiO2 film 55 is removed from a region where a gate electrode is to be formed in a subsequent step (FIG. 9(A)).

The polycrystalline silicon thin film 54 exposed in the area where the gate electrode is to be formed and the thermal oxide film 5 below it.
3 is removed by wet etching. Gate oxidation is performed to form a gate oxide film 56 in a region where a gate electrode is to be formed (FIG. 9(B)). A groove in the CVDSiO2 film 55 is placed in the area where the gate electrode is to be formed. A polycrystalline silicon gate electrode 57 is formed by an etch-back method (
Figure 9(C)).

The CVDSiO2 film 55 is removed by soaking it in NH4F solution (FIG. 9(D)). As shown in FIG. 9D, when the CVDSiO2 film 55 is removed, a portion of the gate oxide film 56 below the polycrystalline silicon gate electrode 57 is also removed at the same time. This means that the gate electrode 5
A problem arises in that the breakdown voltage between the silicon substrate 7 and the silicon substrate 51 is lowered. Similarly, as shown in FIG. 9(D), C
When removing the VDSiO2 film 55, the device isolation oxide film 5
2 is also partially removed at the same time. This causes a problem of lowering the isolation breakdown voltage between different elements.

Next, as shown in FIG. 10A, the polycrystalline silicon thin film 54 is removed, but at this time the gate electrode 57
Since the semiconductor substrate 51 is exposed at the edge portion, the substrate at that portion is scraped to form a groove 62 in the substrate. Groove 62
The surface is oxidized to prevent the silicon substrate 51 from being exposed in the area. At this time, a gate bird's beak 63 is formed. When the gate bird's beak 63 occurs, there is a problem that the transistor becomes offset (Fig. 10
(B)).

An n-type heavily doped diffusion layer 59 serving as a source and a drain is formed, and an interlayer insulating film 60 and metal wiring 61 are formed to obtain a semiconductor device (FIG. 10C). Figure 10(C)
As shown in FIG. 2, since the silicon substrate 51 is scraped by the edge of the gate electrode 57, the diffusion layer 59 at that portion becomes deeper. This causes a problem in that current leaks in a deep portion from the gate electrode 57 toward the substrate even when the transistor is off, that is, punch-through occurs.

[0009]

As explained above, there are the following three problems when manufacturing a buried gate MOSFET using the conventional technology. The first problem is
When the CVDSiO2 film is removed, a portion of the gate oxide film and device isolation oxide film below the polycrystalline silicon gate electrode are also partially removed, reducing gate breakdown voltage and device isolation breakdown voltage.

The second problem is that the semiconductor substrate is scraped at the edge portion of the gate electrode, and when that portion is oxidized, a gate bird's beak is formed. When a gate bird's beak occurs, there is a problem in that the transistor becomes offset. The third problem is that the exposed semiconductor substrate at the edge of the gate electrode is scraped, creating a groove in the substrate, which deepens the source and drain diffusion layers, resulting in punch-through. .

The present invention solves all of the above three problems, and realizes a buried gate MOSFET without lowering the gate breakdown voltage or element isolation breakdown voltage, without causing punch-through of the transistor, and without causing offset. The purpose is to

[Configuration of the invention]

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a gate electrode, a sidewall of a silicon nitride film formed on the side surface of the gate electrode, and a sidewall of a silicon nitride film formed on the side surface of the gate electrode. The gate electrode includes a polycrystalline silicon film and a silicon dioxide film formed by oxidizing the polycrystalline silicon film in contact with the lower part of the silicon nitride film sidewall, and the gate electrode includes The feature is that the silicon film is in direct contact with both silicon dioxide films formed by oxidation.

[0014]

[Operation] This invention deposits a polycrystalline silicon film on a semiconductor substrate in which elements are isolated, deposits a silicon dioxide film on a desired portion of the polycrystalline silicon film, and deposits silicon nitride on the side surface of the silicon dioxide film. A sidewall made of a film is formed. The exposed portion of the polycrystalline silicon film in contact with the lower portion of the silicon nitride sidewall and the semiconductor substrate are simultaneously oxidized to form a gate oxide film, and a gate electrode is formed in a desired portion by etching back. Thereafter, the silicon dioxide film is removed using the first formed polycrystalline silicon film as a stopper.

[0015]

[Example] Practical examples of the present invention will be explained below. 1 to 4 are manufacturing process diagrams of a first embodiment applied to a MOS integrated circuit. An element isolation insulating film 2 is formed on a p-type silicon substrate 1 by, for example, the LOCOS method (FIG. 1(A)). A polycrystalline silicon thin film 3 and a CVDSiO2 film 4 are deposited with uniform thickness on the surface (FIG. 1(B)). Regarding the area where the gate electrode is to be formed in the subsequent process, C
Remove the VDSiO2 film 4. For example, it is possible to use the polycrystalline silicon thin film 3 as an etching stopper film and apply photolithography and anisotropic etching of the CVDSiO2 film 4. A channel impurity is doped into the channel portion of the transistor by ion implantation or the like (FIG. 1C).

A sidewall 5 made of a silicon nitride film is formed on the etched side surface of the CVDSiO2 film 4. For example, it is possible to apply anisotropic etching of a silicon nitride film using the polycrystalline silicon thin film 3 as an etching stopper film (FIG. 2(A)). The polycrystalline silicon thin film 3 exposed in the region where the gate electrode is to be formed is removed. In order to avoid damaging the region where the gate electrode is to be formed, a method that can be considered in this step is to oxidize the exposed portion of the polycrystalline silicon thin film 3 and then perform wet etching with NH4F (Figure 2 (B)). ). Since the channel portion of the semiconductor substrate 1 is exposed, gate oxidation is performed in a short time to form a thin gate oxide film 6 (FIG. 2(C)).

Polycrystalline silicon 7 serving as a gate electrode material is deposited over the entire surface. A dummy resist 8 is placed on a region where a polycrystalline silicon gate electrode 7 is to be formed over a wide area, such as a contact portion with a gate electrode. The dummy resist 8 serves to prevent the polycrystalline silicon gate electrode 7 from disappearing in a large pattern portion during etchback (FIG. 3(A)). The polycrystalline silicon gate electrode 7 is etched back until the surface of the CVDSiO2 film 4 is exposed to form a buried gate electrode (see FIG. 3).
B)). The CVDSiO2 film 4 is removed by NH4F wet etching or the like. In the conventional example. A problem arose in that the gate oxide film 6 was removed in this step, but the problem occurred in FIG.
As shown in C), in the present invention, the gate oxide film 6 and the element isolation oxide film 2 are not etched away, and it can be seen that the conventional problems have been solved. An n-type impurity for forming a low concentration source/drain diffusion layer is implanted into the polycrystalline silicon thin film 3 by accelerating ions 9 (FIG. 3(C)).

The exposed portion of polycrystalline silicon thin film 3 is removed. Either oxidation and peeling is performed as in the case of FIG. 2(B), or dry etching is used (FIG. 4(A)). N-type impurity 1 for forming high concentration source/drain diffusion layer
The source and drain regions are doped with 0 by ion implantation (FIG. 4B). Annealing for activation is performed to form low concentration source/drain 11 by diffusion from polycrystalline silicon thin film 3 and to activate high concentration source/drain 11. By such a method, the transistor can be formed into an LDD structure in a self-aligned manner with respect to the gate electrode. An interlayer insulating film 13 and metal wiring 14 are formed to obtain a desired semiconductor device (FIG. 4(C)).

According to this embodiment, all three problems occurring in conventional buried gate MOSFETs can be solved. Furthermore, the MOSFET can be made into an LDD structure. Reliability can be improved during miniaturization. Another advantage is that the finished dimension of the gate (in the channel direction) is shorter than the resist pattern dimension formed using lithography technology by the amount of the silicon nitride film sidewall 5, so it is possible to form a gate that is finer than the lithography limit. This point can be raised. Another advantage is that the channel, gate, source and drain can be formed in a self-aligned manner.

FIGS. 5 to 8 are manufacturing process diagrams of the second embodiment. An element isolation insulating film 2 is formed on a p-type silicon substrate 1 by, for example, the LOCOS method (FIG. 5(A)). Thermal oxide film 15, polycrystalline silicon thin film 3, and CVDS on the surface
The iO2 film 4 is deposited to a uniform thickness (Fig. 5(B)).
). As in the first embodiment, the CVDSiO2 film 4 is removed and the channel portion is doped with impurities (Fig. 5(C)).
).

Sidewall 5 made of silicon nitride film
(Fig. 6(A)). Polycrystalline silicon thin film 3 and thermal oxide film 15 exposed in the area where the gate electrode is to be formed
remove. Unlike the first embodiment, the polycrystalline silicon thin film 3 can be removed by dry etching or wet etching since there is a thermal oxide film 15 underneath, or the same method as in the first embodiment can be used. (Figure 6(B))
. 6(C) to FIG. 7(B) are the same steps as FIG. 2(C) to FIG. 3(B) in the first embodiment.

When the CVDSiO2 film 4 is removed by NH4F wet etching or the like, the gate oxide film 6 and the element isolation oxide film 2 are etched, as shown in FIG. It can be seen that the conventional problems have been solved without any problems. Unlike the first embodiment, since there is a thermal oxide film 15 under the polycrystalline silicon thin film 3,
Impurities cannot be diffused from the polycrystalline silicon thin film 3 to the low concentration source/drain portions. In other words, in the second embodiment, the prerequisite is not to use the LDD structure (Fig. 7
(C)).

The exposed portion of polycrystalline silicon thin film 3 is removed. Either oxidation and peeling is performed as in the case of FIG. 2(B), or dry etching or wet etching is used (FIG. 8(A)). An n-type impurity 10 for forming a highly concentrated source/drain diffusion layer is doped into the source/drain region by ion implantation (FIG. 8(B)). Annealing for activation is performed to activate the highly doped source/drain 11. Interlayer insulating film 13 and metal wiring 14 are formed to obtain a desired semiconductor device (FIG. 8(C)).

According to this embodiment, all three problems occurring in conventional buried gate MOSFETs can be solved. Furthermore, the same as in the first embodiment. It has the advantage of being able to form gates that are finer than the lithography limit, and that the channel, gate, source and drain can be formed in self-alignment. One point that the second embodiment is superior to the first embodiment is that the polycrystalline silicon thin film can be easily removed. Another point is that the source/drain high concentration diffusion layer 11 is formed from the outside of the silicon nitride film sidewall for a fine gate, so the junction depth of this diffusion layer 11 is not made shallow. One of the advantages is that it is possible to realize long MOSFETs.

[0025]

As explained above, in the semiconductor device according to the present invention, since the silicon nitride film sidewall is formed on the side surface of the gate electrode, the gate oxide film and the field oxide film are removed when the silicon dioxide film is removed. It is possible to prevent the polycrystalline silicon film from being removed at the same time, and to prevent the semiconductor substrate from being etched at the same time when the polycrystalline silicon film is removed. These prevent the gate breakdown voltage from decreasing.
It becomes possible to manufacture a buried gate MOSFET in which the transistor does not become offset and punch-through can be prevented.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a manufacturing process showing a first embodiment of the present invention.

FIG. 2 is a manufacturing process sectional view showing a first embodiment following FIG. 1;

3 is a manufacturing process sectional view showing the first embodiment following FIG. 2. FIG.

FIG. 4 is a manufacturing process sectional view showing the first embodiment following FIG. 3;

FIG. 5 is a manufacturing process sectional view showing a second embodiment of the present invention.

6 is a manufacturing process sectional view showing a second embodiment following FIG. 5. FIG.

7 is a manufacturing process sectional view showing a second embodiment following FIG. 6. FIG.

8 is a manufacturing process sectional view showing a second embodiment following FIG. 7. FIG.

FIG. 9 is a sectional view of a manufacturing process showing a conventional example.

10 is a manufacturing process sectional view showing a conventional example following FIG. 9. FIG.

[Explanation of symbols]

1 p-type silicon substrate 2 element isolation insulating film 3 polycrystalline silicon film 4 CVDSiO2 film 5 silicon nitride film sidewall 6 gate insulating film 7 polycrystalline silicon gate electrode 8 resist 9 n-type impurity ion for forming low concentration source and drain 1
0 High concentration n-type impurity for forming source and drain 11
High concentration source/drain 12 Low concentration source/drain 13 Interlayer insulating film 14 Metal wiring 15 Thermal oxide film

Claims (2)

[Claims] 1. A gate electrode, a silicon nitride film sidewall formed on the side surface of the gate electrode, a polycrystalline silicon film in contact with the lower part of the silicon nitride film sidewall, and a polycrystalline silicon film in contact with the lower part of the silicon nitride film sidewall. and a silicon dioxide film formed by oxidizing the polycrystalline silicon film, and the gate electrode is directly connected to both the sidewalls of the silicon nitride film and the silicon dioxide film formed by oxidizing the polycrystalline silicon film. A semiconductor device characterized by being in contact with each other. 2. A step of depositing a polycrystalline silicon film on a device-isolated semiconductor substrate, a step of depositing a silicon dioxide film on a desired portion of the polycrystalline silicon film, and a step of depositing a silicon dioxide film on a side surface of the silicon dioxide film. A method for manufacturing a semiconductor device, comprising the steps of forming a sidewall made of a silicon nitride film, and simultaneously oxidizing a portion of the polycrystalline silicon film in contact with a lower portion of the silicon nitride sidewall and a semiconductor substrate.