JPH01123416A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form two semiconductor layers having mutually opposite conductivity type active regions without overlapping, by performing doping with impurities when a plurality of semiconductor layers are formed in region, which is at a specified distance from a boundary line between the intended two semiconductor layers. CONSTITUTION:An oxide film 2 and a nitride film 3 are sequentially formed on a silicon substrate 1. Etching is performed with a resist mask 4 as a mask. At this time, the surface region of the substrate 1 is exposed from a boundary line, which is separated from an intended boundary line X between an N-type well layer and a P-type well layer, by a specified distance (d). N-type impurity ions are implanted, and an N-type ion implanted layer 5 is formed. When heat treatment is performed, the N-type impurities, which are implanted into the substrate 1, are diffused in the lateral direction, and an N-type well layer 51 is formed. P-type impurity ions are implanted, and a P-type ion implanted layer 7 is formed. When heat treatment is performed, the P-type impurities, which are implanted into the substrate 1, are diffused in the lateral direction, and a P-type well layer 71 is formed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a C-MO device.
S (Comp 1 emen t a ry-M
etal Oxide Sem1conduct.

The present invention relates to a method of manufacturing a complementary semiconductor device such as r).

r Prior Art] In recent years, semiconductor devices have come to be used in a wide range of fields, and there has been a strong demand for lower power consumption and higher speed. In response to such demands, complementary semiconductor devices such as C-MO8 are becoming widely used.

In conventional C-MOS technology, N
The mainstream technology was to form a type well layer, and to form a P-type well layer on an N-type semiconductor substrate (single-well technology). However, as miniaturization progresses, a technology is being introduced to form two well layers, a P-type well layer and an N-type well layer, in a P-type or N-type semiconductor substrate.

In this way, the technology of forming both P-type and N-type well layers on a semiconductor substrate (fin-well technology) is effective as a means of suppressing bunch-through when forming short channel transistors with short gate lengths. . For example, N
In order to suppress bunch-through of channel type transistors, it is necessary to increase the concentration of P-type impurities in the semiconductor substrate. However, if the concentration of P-type impurities in the semiconductor substrate is increased, more N-type impurities must be introduced in order to form an N-type well layer in the semiconductor substrate. This causes great difficulty in manufacturing semiconductor devices.

Therefore, without changing the impurity concentration in the semiconductor substrate,
It is effective to increase the concentration of P-type impurities only in the region where the N-channel transistor is to be formed. In other words, a technique (fin-well technique) that not only forms an N-type well layer in a P-type semiconductor substrate but also forms a P-type well layer is extremely effective.

2A to 2E are partial cross-sectional views showing, in order of steps, a method for forming an N-type well layer and a P-type well layer in a semiconductor substrate in a conventional method for manufacturing a C-MO5 semiconductor device. be.

First, referring to FIG. 2A, a thin oxide film 2 and a thin nitride film 3 are sequentially formed on a silicon substrate 1. As shown in FIG. Thereafter, a resist film 4 for patterning a predetermined portion of the surface of the silicon substrate 1 is formed and etched to expose only a region where an N-type well layer will be formed. As shown by arrow A, N-type impurity ions such as P10 are implanted. By doing so, the silicon substrate 1 is exposed only in the exposed area.
An N-type ion implantation layer 5 is formed on the surface layer.

Next, referring to FIG. 2B, the resist film 4 is removed.

Thereafter, heat treatment is performed to diffuse the implanted N-type impurity and form an N-type well layer 51. A thick oxide film 6 is formed on the N-type well layer 51.

Referring to FIG. 2C, after the nitride film 3 is removed, arrow B
By implanting P-type impurity ions such as B+, a P-type ion implantation layer 7 is formed under the thin oxide film 2 as shown in FIG.

Thereafter, as shown in FIG. 2D, the implanted P-type impurity is diffused to form a P-type well layer 71.

Referring to FIG. 2E, oxide film 2.6 is removed.

The N-type well layer 51 and the P-type well layer 71 thus formed have an overlapping region 8. If the pre-designed boundaries between both well layers are indicated by X, the overlapping region 8 is
The N-type well layer 51 extends laterally from the boundary line X by a distance dl, and the P-type well layer 71 extends laterally from the boundary line X by a distance d2.

[Problems to be Solved by the Invention] As described above, according to the conventional manufacturing method, a region where the N-type well layer and the P-type well layer overlap is formed. In this overlapping region, a portion occurs where the P type and the N type complement each other. Therefore, in this overlapping region, there is a portion that exhibits conductivity characteristics that are neither P-type nor N-type. Therefore, if an active element is formed in this portion, there is a problem in that a predetermined target characteristic cannot be obtained.

Therefore, the present invention was made to solve the above-mentioned problems, and has active regions of mutually opposite conductivity types. It is an object of the present invention to provide a method for manufacturing a complementary semiconductor device that can form both semiconductor layers without overlapping them.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention provides a method for manufacturing a semiconductor device when forming a plurality of semiconductor layers having mutually opposite conductivity types in the same semiconductor substrate. The method includes the step of doping impurities of respective conductivity types into regions defined by another boundary line separated by a predetermined distance from the boundary line.

[Function] The method for manufacturing a semiconductor device according to the present invention includes doping of impurities performed when forming a plurality of semiconductor layers having mutually opposite conductivity types in the same semiconductor substrate. This is done within an area separated by a predetermined distance from the line.

Therefore, even after doping the impurities, the lateral diffusion of the impurities due to the heat treatment will cause the m
Formed without lH.

[Embodiments of the Invention] FIGS. 1A to 1E are partial cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention, particularly a method for forming a well layer, in order of steps.

First, referring to FIG. 1A, a thin oxide film 2 and a thin nitride film 3 are sequentially formed on a silicon substrate 1. As shown in FIG.

Thereafter, a resist film 4 for patterning a predetermined portion of the surface of the silicon substrate 1 is formed. By etching this resist film 4 as a mask, only a predetermined surface area of the silicon substrate 1 is exposed. At this time,
A predetermined surface area of the silicon substrate 1 is exposed at a boundary line separated by a predetermined distance d from the desired boundary line X between the N-type well layer and the P-type well layer. Then arrow A
As shown in the figure, N-type impurity ions such as P10 are implanted. An N-type ion-implanted layer 5 is formed in a predetermined surface layer of the silicon substrate 1 .

Next, referring to FIG. 1B, resist film 4 is removed. By performing the heat treatment, the N-type impurity implanted into the silicon substrate 1 is diffused in the lateral direction, and the N-type well layer 5 is
1 is formed. A thick oxide film 6 is formed on the N-type well layer 51.

Referring to FIG. 1C, after the nitride film 3 is removed, buttering is performed at a boundary line separated by a predetermined distance d2 from a predetermined boundary line X between the N-type well layer and the P-type well layer. A resist film 4 is formed. P-type impurity ions such as B+ are implanted as shown by arrow B using the resist film 4 as a mask. A P-type ion implantation layer 7 is formed under the thin oxide film 2 in a region not covered by the resist film 4.

Referring to FIG. 1D, resist film 4 is removed.

Thereafter, by performing heat treatment, the P-type impurity implanted into the silicon substrate 1 is laterally diffused, and a P-type well layer 71 is formed.

Then, as shown in FIG. 1E, by removing the oxide film 2.6, the N-type well layer 51 and the P-type well layer 71 are formed in the silicon substrate 1 without overlapping.

In the above embodiment, the predetermined distance d, d2 is 0.7 to 0°9·(D
, D2) is preferable.

This is because the lateral diffusion distance (d) after impurity implantation is within the range of 0.7D to 0.9D with respect to the depth (D) of the well layer.

Note that even if the N-type well layer and the P-type well layer are formed to have an overlapping region by a conventional manufacturing method,
It is also possible to avoid the problem by not forming active elements in the overlapping region. It indicates a concentration other than the predetermined impurity concentration of the well layer within the ff [region, and when an active element is formed on this area, the active element will be an active element formed on the well layer other than this area. This is because they exhibit different characteristics. Therefore, preferably, by not forming a diffusion region for forming an active element within a range of at most d-0.9D from the designed boundary line between the P-type well layer and the N-type well layer, It is possible to avoid this problem.

[Effects of the Invention] As described above, according to the present invention, in a method for manufacturing a complementary semiconductor device, a plurality of semiconductor layers having mutually opposite conductivity types can be formed without overlapping regions. , it becomes possible to operate all the active elements formed in those semiconductor layers according to the set values.

[Brief explanation of the drawing]

1A, 1B, 1C, 1D, and 1E are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps; FIGS. 2A, 2B, and 2C; figure,
FIGS. 2D and 2E are partial cross-sectional views showing a conventional method for manufacturing a semiconductor device in the order of steps. In the figure, 1 is a silicon substrate, 2.6 is an oxide film, 3 is a nitride film, 4 is a resist film, 5 is an N-type ion implantation layer, 7 is a P-type ion implantation layer, 8 is an overlapping region, and 51 is an N-type The well layer 71 is a P-type well layer. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type are formed on a semiconductor substrate having a main surface;
A method for manufacturing a complementary semiconductor device in which a semiconductor layer of a conductivity type and a semiconductor layer of a second conductivity type have active regions of mutually opposite conductivity types, Doping a first conductivity type impurity into a region defined by a first boundary line separated by a predetermined distance from an intended boundary line between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. forming a semiconductor layer of the first conductivity type by diffusing the doped impurity of the first conductivity type by heat treatment; and forming a second boundary separated by a predetermined distance from the target boundary line. doping a second conductivity type impurity into a region defined by the line; and diffusing the doped second conductivity type impurity by heat treatment to form the second conductivity type semiconductor layer. A method for manufacturing a semiconductor device, characterized in that regions in which the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are formed do not overlap. (2) The predetermined distance (d) is the depth of the semiconductor layer (
D) is within a maximum range of 0.9D. (3) The step of doping with impurities is performed by forming a resist film for patterning a predetermined portion of the main surface and using the resist film as a mask. A method for manufacturing a semiconductor device. (4) The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is a fin-well type complementary MOS transistor.