JPS6126699B2 - - Google Patents

Info

Publication number
JPS6126699B2
JPS6126699B2 JP56070287A JP7028781A JPS6126699B2 JP S6126699 B2 JPS6126699 B2 JP S6126699B2 JP 56070287 A JP56070287 A JP 56070287A JP 7028781 A JP7028781 A JP 7028781A JP S6126699 B2 JPS6126699 B2 JP S6126699B2
Authority
JP
Japan
Prior art keywords
memory
memory bank
bank
cpu
dma controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56070287A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57185552A (en
Inventor
Seijiro Hirayama
Shinji Yamane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP56070287A priority Critical patent/JPS57185552A/ja
Publication of JPS57185552A publication Critical patent/JPS57185552A/ja
Publication of JPS6126699B2 publication Critical patent/JPS6126699B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
JP56070287A 1981-05-08 1981-05-08 Switching device for memory bank in microcomputer system Granted JPS57185552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56070287A JPS57185552A (en) 1981-05-08 1981-05-08 Switching device for memory bank in microcomputer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56070287A JPS57185552A (en) 1981-05-08 1981-05-08 Switching device for memory bank in microcomputer system

Publications (2)

Publication Number Publication Date
JPS57185552A JPS57185552A (en) 1982-11-15
JPS6126699B2 true JPS6126699B2 (enrdf_load_stackoverflow) 1986-06-21

Family

ID=13427111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56070287A Granted JPS57185552A (en) 1981-05-08 1981-05-08 Switching device for memory bank in microcomputer system

Country Status (1)

Country Link
JP (1) JPS57185552A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015757A (ja) * 1983-07-06 1985-01-26 Fujitsu Ltd メモリ制御回路
JPS6037057A (ja) * 1983-08-04 1985-02-26 Fujitsu Kiden Ltd ダイレクトメモリアクセスによるメモリ格納方式

Also Published As

Publication number Publication date
JPS57185552A (en) 1982-11-15

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