JPS61264401A - Selection control output circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of a selection control output circuit by stopping the supply of power to an output relay when one or more drive signals are significant in a normal mode where the output relay is not working and applying interlocking. CONSTITUTION:A selection control output circuit is formed by connecting a fixed mark decoding/spot decomposing part 25 consisting of a writing control part 8, a data memory 9, etc. to a master controller 1 consisting of a microprocessor 2 and a memory 3. The part 25 also includes a fixed mark detecting/spot decomposing part 16, an output relay driver 17, a normalcy detecting part 18, an abnormality detecting part 20, an output relay power supply control part 22 and an output relay 26. While the control contents decided previously from an item list are written into the memory 3 in the controller 1. Thus the part 22 stops the supply of power to the relay 26 according to the abnormality detecting signal 21 given from the part 20 as long as even a single driver 17 is significant in a normal mode. This prevents the malfunction of an external device to be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a selective control output circuit of a remote monitoring and control device, and relates to a method of detecting an internal abnormality in the circuit and stopping the output.

[Conventional technology]

2nd f! lJ is Mitsubishi Electric Corporation MELFI, EX module h overview ql (October 1978, C0FZ-40!
JEZZ-IL-4124, C0FZ-41: JEZZ
4L-4125) is a block diagram of a conventional selection control output circuit.

In the figure, 1 is a master controller consisting of a microprocessor 2 and a memory 3 connected to it.

7 is a write pulse 4 output from this master controller 1, an address 5. A constant mark decoding section 7 is constituted by a constant mark decoding section that takes in data 6, a constant mark verification section 12, a constant mark decoded signal 13, and a point decomposition section 15. The constant mark decoding section 7 corresponds to the module C0FZ-40 in the above document, and the point decomposition section 15 corresponds to the module C0FZ-41 in the above document.

Also, Figure 3 is a detailed data diagram showing the format of data output from the master controller.V% Figure 4 is a code table showing the constant mark codes of groups and points handled in the constant mark relay 11 and constant mark verification. The diagram shown in FIG. 5 is also a diagram showing a code table of constant mark codes for control.

Next, the operation will be explained. First, master controller 1 sends write pulse 4, address 5. Data 6 is output to constant mark decoding section 7. here.

The constant mark decoding unit 7 has a self-address, and the write control unit 8 compares this self-address with the address 5 output from the master controller 1 to detect a match, and receives the write pulse 4. When the writing controller 8
outputs a command to the data memory 9 to store the data 6. - This output is input to the constant mark relay driver 10, and then the constant mark relay 11 is driven. The output of the constant mark relay 11 due to this drive is taken into the constant mark verification section 12, and the output content is transferred to the constant mark verification section 12.
In step 2, constant mark verification is performed by comparing with the constant mark code table for groups and points in Figure 4 and the constant mark code table for control in Figure N5.

As a result, the above output content is replaced with "normal" or /161 to 410, etc. in FIGS. 4 and 5, and is output to the point decomposition unit 15 as the constant mark decoded signal 13. In response to this output, the output relay 14 outputs one of the point-resolved signals P1o-P+ to operate the external equipment to be controlled. However, in the constant mark test described above, if the output content from the constant mark relay 11 corresponds to "normal" in FIGS. 4 and 5, the output relay does not operate.

[Problem that the invention seeks to solve]

Since the conventional selection control output circuit is configured as described above, when an abnormality such as a short circuit occurs in the constant mark verification section 12 and the constant mark decoded signal 13 is a "normal" signal, one output relay is activated. When the above operation is performed, there is a problem in that the external equipment to be controlled is also operated according to the output.

This invention was made to solve the above-mentioned problems, and if one or more output relays are about to operate when they receive a "normal" signal (a signal in which all of them are not operating), To provide a selection control output circuit that does not drive any of the output relays even when receiving the signal, thereby preventing erroneously driving external equipment to be controlled.

[Means for solving problems]

The selection control output circuit according to the present invention supplies power to the output relays if one or more signals from the master controller are significant for driving the output relays during "normal" times when all output relays do not operate. (to shut down the device without stopping), and use an interlock to prevent it from driving external equipment to be controlled.

[For production]

The output relay power supply control section in this invention stops the power supply to the output relay if even one output relay driver becomes significant during "normal" time based on the abnormality detection signal from the abnormality detection section. Controlled equipment will not malfunction.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, the same reference numerals as in FIG. 3 indicate the same or corresponding parts. 16 is constant mark verification/point decomposition part, 17
is the output relay driver. 18 is a normal detection unit (detection means) that detects a "normal" signal based on the output of the data memory 9, 19 is a normal detection signal, and 20 is an abnormal state detected based on the output of the output relay driver and the normal detection signal 19. Abnormality detection section (detection means), 21 is an abnormality detection signal, 22 is an output relay power control section (output stop means) that controls the power supply to the υ output relay 26 according to the command of the abnormality detection signal 21
, 24 is a constant mark decoding/point decomposition signal, 25 is a constant mark decoding/point decomposition unit, and 26 is an output relay.

Next, the operation will be explained. In the memory 3 in the master controller 1, control contents determined in advance according to an item table are written. here.

First, similar to the operation of the conventional example, the microprocessor 2 in the master controller 1 reads the contents of the memory 3,
The write pulse 4, address 5, and data 6 based on the data format shown in FIG. 3 are output to the fixed mark decoding/point decomposition unit 25. The constant mark decoding/point decomposition unit 25 compares its own address with the input address 5, and when the addresses match, the write control unit 8 stores the data 6 in the data memory 9 according to the input write pulse 4. Outputs the command to The output data (first data) of the data memory 9 is output to the constant mark verification section/point decomposition section 16 and also to the normality detection section 18 . Thereafter, the constant mark verification/point decomposition section 16 performs constant mark verification according to the Gunken point constant mark code table shown in FIG. 4 and the control constant mark food table shown in FIG. The input data (first data) is developed by the constant mark verification/point decomposition section 16 and output to the output relay driver 17. Furthermore, output relay driver 1
7 outputs the constant mark decoding/point resolution signal 24 (second data) to the output relay 2B and also outputs it to the abnormality detection section 20. On the other hand, the normality detection section 18 detects whether the output data from the data memory 9 is a "normal" signal, and the normality detection signal 19 detected as a result is outputted to the abnormality detection section 20. In the abnormality detection unit 20, when the constant mark decoding/point resolution signal 24 is a "normal" signal and the normal detection signal 18 is significant, the output of the output relay driver 17, that is, the input signal of the output relay 26 (second data) If one or more of the constant mark decoding/point resolution signals 24 becomes significant,
It is regarded as an abnormality and the abnormality detection signal 21 is made significant. The output relay power control unit 22 confirms that the abnormality detection signal 21 has become significant, and stops (turns off) the power supply to the output relay power supply [23] and disables the output relay 26 so that it does not operate. Put it in working condition. Therefore, even if the output of the output relay driver 17 becomes significant, the output relay does not operate. The output relay power supply control unit 220 circuit element is, for example, a transistor or FIT.

Anything that has a power supply opening/closing function such as a thyristor or relay may be used.

[Effects of the Invention] As described above, according to the present invention, if a condition occurs in which the output relay operates during "normal" times when the output relay should not operate, the power supply to the output relay is stopped. Since the output relay is configured to stop, it is possible to obtain a highly reliable selection control output circuit without causing the output relay to operate erroneously in the event of an abnormality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a selection control output circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional selection control output circuit, and FIG. 3 is data showing a data format output from a master controller. Detailed drawings: Figure 4 shows a code table showing constant mark codes for groups and points; Figure 5 shows a code table for constant mark codes for control; Master controller, 2 is a microprocessor, 4 is a write pulse, 5 is an address, 6 is data, 18 is a normal detection section, 19 is a normal detection signal, 20
21 is an abnormality detection section, 21 is an abnormality detection signal, 22 is an output relay power supply control section, and 26 is an output relay. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent Applicant Mitsubishi Electric Co., Ltd. Procedural Amendment (Voluntary) 1985...Representation by the Director-General of the Japan Agency Name of Patent Application No. 107201 1982 Representative of the person who does the selection control output circuit Moriya Shiki Claims column 6 of the subject specification: Contents of amendment (1) Amend the attached patent claims. (2) Correct the attached circular, Figure 2. 7. List of attached documents (1) One document (two copies) stating the amended scope of claims
) One or more documents stating the amended figure 2. Claims after the amendment (11) A document stating the amended figure 2 (taking in data etc. from a master controller having 11 microprocessors, developing the data and driving a plurality of output relays, Detection means for detecting an abnormality from first data from the master controller and second data after the first data is expanded, in a selection control output circuit of a remote monitoring and control device that operates an external controlled device. and an output stop that takes in an abnormality detection signal output when an abnormality is detected by this detection means, and sets all the output relays to a non-operating state so that the external controlled equipment does not operate, thereby stopping the output in the event of an abnormality. (2: The detection means detects the output of the soldering device when the data from the master controller is in a "normal" state in which all the output relays are not operated. an abnormality detection section that outputs an abnormality detection signal when at least one input signal input to the relay is significant; and the output stop means supplies power to all of the output relays when the abnormality detection signal is input. 2. The selection control output circuit according to claim 1, further comprising an output relay power supply control section for stopping the output relay.

Claims (2)

[Claims] (1) In a selection control output circuit for remote monitoring control that takes in data etc. from a master controller having a microprocessor, expands the data, drives a plurality of output relays, and operates an external device to be controlled, the master controller a detection means for detecting an abnormality from first data from the source and second data after the first data is expanded; and an abnormality detection signal outputted when an abnormality is detected by the detection means. A selection control output circuit comprising: an output stop means for stopping all of the output relays in a non-operating state so that the external controlled device does not operate, and stopping the output in the event of an abnormality. (2) When the data from the master controller is a "normal" state in which all the output relays are not operated, the detection means detects when at least one input signal input to all the output relays is significant. In addition to comprising an abnormality detection section that outputs an abnormality detection signal, the output stop means includes an output relay power control section that stops power supply to all the output relays when the abnormality detection signal is input. A selection control output circuit according to claim 1.