JPS61180338A - Interruption input device - Google Patents

Abstract

PURPOSE:To obtain an interruption input device containing a self-diagnosis function which can detect quickly a trouble a simple constitution, by checking periodically each interruption input accepting circuit through a CPU. CONSTITUTION:An interruption input accepting circuit 32 supplies an interruption signal through an input/output device and delivers the interruption data D1-Dn and an interruption interrupting signal to a CPU1. Then the circuit 32 receives the factor reset signals R1-Rn from the CPU1. A check data output circuit 33 supplies the check data to the input side of the circuit 32 by the signal sent from the CPU1. The 1st switch SW1 controls the actuation of the circuit 33 which is driven by the signal given from the CPU1. While the 2nd switch SW2 is connected to a common line of the input/output device and controls the actuation of an input/output circuit with the signal given from the CPU1. The CPU1 checks periodically the circuit 32 to check quickly the troubles of those circuits.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention fl, Ilo (Inputoutput
) The present invention relates to an interrupt input device that transmits an interrupt signal output from a combiator (CPU) to a combiator (CPU). More specifically, the present invention relates to an interrupt input device having a self-diagnosis function.

(Prior Art) There have been various interrupt input devices in the past, but none of them have been configured to be able to discover the faulty @ of the interrupt input device itself.

(Problems to be Solved by the Invention) The interrupt input device functions when an interrupt input is requested, and if this device malfunctions, the interrupt function will not work, significantly reducing the reliability of the system.

Although it is possible to improve reliability by duplicating the interrupt input device, there is a problem in that the configuration becomes complicated. The present invention has been made in view of these problems in the prior art, and its purpose is to provide an interrupt input device that has a simple configuration and has a self-diagnosis function that can quickly discover failures. This is what we are trying to achieve.

(Means for Solving the Problems) The present invention that solves the above-mentioned problems is based on an interrupt signal output from an input/output device. an interrupt input reception circuit that inputs and outputs interrupt data and an interrupt interlat signal to the computer, and receives a factor reset signal from the computer; and a check mark on the input side of the interrupt input reception circuit according to the signal from the computer. A check data output circuit for inputting data; a first switch driven by a signal from the combination unit; and a first switch for controlling operation/non-operation of the check data output circuit; and a first switch connected to the common line of the input/output device. and a second switch that controls the operation or non-operation of the input/output circuit by a signal from the computer.

(Example) FIG. 1 is a configuration block diagram showing an example of an apparatus according to the present invention. In the figure, 1 is a CPU, which is like a general combinator or microcomputer. 21 + 22 e 2 n is an input circuit that outputs an interrupt input signal, for example, when a contact is used and the contact changes from an OFF state to an ON state, or when the DC voltage level changes from 'H# level to 1L level. An interrupt is requested when the value changes to . 3 [CPU 1
This is an interrupt input device of the present invention provided between the input circuits 21 to 2n and each of the input circuits 21 to 2n. In this interrupt input device 3, 31
32 is an input terminal to which an interrupt input signal is applied; 32 is an interrupt manual acceptance circuit that inputs the interrupt signal applied to the input terminal 31; this circuit is configured including a latch circuit;
Interrupt data D and interrupt interlat signal I to PU1
It outputs T and also receives a factor reset signal R1 from the CPU1. 33i chip data output circuit,
For example, it is configured to include a transistor Tr that functions as a switching element, and inputs check data to the input side of the corresponding interrupt input circuit 32 in response to a signal from the CPUI. Each interrupt input reception circuit 32, each check data output circuit 33ij, each input circuit 21, 22, etc.
- A plurality of (n) numbers from 1 to 2n are provided corresponding to 2n. The first switch SWI U is commonly connected to the emitter of the transistor Tr of each check data output circuit 33, and controls the operation or non-operation of each check data output circuit. 34 is a drive circuit for the first switch SW1, to which a signal from the CPU1 is applied. sw2 is a second switch to which the common lines of the input circuits 21 to 2n are connected in common, and controls the operation and non-operation of each input circuit. 35 is a drive circuit for the second switch sw2, for example, a latch circuit is used, and a signal from the CPUI is applied.

36 is a circuit that reads the on/off state of the first switch sw1, 37 is a circuit that reads the on/off state of the second switch sw2, and the read signals are applied to the CPUI. The second switch turns off the common line during the time when the operation of the device is being checked, and does not accept interrupt requests from the people output circuits 21 to 2n.

In the device configured in this manner, the CPU 1 checks each interrupt manual acceptance circuit 32 at regular intervals to quickly discover failures in each of these circuits.

The details of the operation will be explained below according to the flowchart shown in FIG.

First of all, the CPUI has 1. Second switch SW
1. Drive SW2 to OFF via each drive circuit 34, 35, and output OFF data to each check data output circuit 33 (Step 1, hereinafter referred to as SP).
). Next, the first. second switch sw1,
The on/off state of sw2 is read through each reading circuit 36,371 (SF3). Next, it is determined whether the first and second switches are on or off (sp3). SP1 so far~
SP3 is a preparation process for checking. In sp3, if it is determined to be off (YES), each switch sw
1. Assuming that sw2 is normal, the process moves to sp5, and if it is determined to be on (No), the process moves to sp4, where a message indicating that the switch is defective is output to, for example, a printer (not shown). .

In sp5, interrupt data D, ~Dnt- outputted from each interrupt input acceptance circuit 32 is read, and in SP6,
It is determined whether each of the interrupt data D, . . . , read in sp5 are all off. If the answer is YES, the process moves to 5PjQ, and if the answer is NO, it is determined in sp7 whether or not an interrupt has occurred using the interrupt interwoven signal IT, and if an interrupt has occurred, the normal interrupt handling routine is called in spB. Execute interrupt processing. If it is determined in SP7 that there is no interrupt, the process moves to SP9, where it is determined that the data in the 1' state is defective, that is, the interrupt input receiving circuit outputting the data in the 1' state is Outputs a message indicating that it is defective.

sp5 to SP9 are steps for confirming that each interrupt input reception circuit is not interrupted.

In 5pio, turn on the first switch swi 1, then read the on/off state of the first switch SW (
spll), fs to determine if swl is on
p12). At 5P12, swl is on (YES
] If it is determined that swi is off (NO), a message is output as swi is defective (open) (SP131°spl 4,
Set to interrupt check mode, and then output ON data to all check data output circuits 33 (spl5)
, Then, after waiting for a predetermined time t (about mS or μs) (SP16), off data is output to all of the check data output circuits 33, and the first switch 5W
11 (spl 7). Next, 5P18
At step SP20, it is determined whether or not an interrupt has occurred, and if it is determined that no interrupt has occurred, a message indicating that the interrupt control is defective is output (SP20). When it is determined that an interrupt has occurred, the interrupt input data D and ~Dn from each interrupt input reception circuit 32 are read (SP2o), and then it is checked whether or not all of the relevant interrupt input data D and ~Dn are on. Judge (5P21). Here, if even one data is off, the relevant data is output and the fc interrupt input reception circuit is considered to be defective. output a message indicating (
5P22). At 5p21, if the data D, ~Dn are all on (YES), the process moves to 5P25VC, where the reset signal R9, ~Rn is sent to the valley interrupt input reception circuit 33.
Output and read the interrupt data D to ~ (5
P24), it is determined whether the read data D, -Dn are all off (5P25). Here, if there is any ON data, the interrupt input receiving circuit that outputs the ON data is considered defective and outputs a message to that effect (5P26).

The above steps 5P10 to 5P25 are steps for checking each interrupt input reception circuit.

In S P25, if data D and ~Dn are all off, interrupt check mode should be canceled. 5P27)
The second switch sw21 is turned on (5P28), and the state of this switch sw2 is read (sp29). Then, it is necessary to judge whether the second switch sw2 is on or not. s p 3
0), if sw2 is off, it is assumed that this switch SW2 is defective, and a message to that effect is output (S
P31). Also, if SW2 is on, the interrupt input device [
It is determined that all of 3 are operating normally, and the process moves to 5P32 to proceed to normal interrupt processing. Above 5P27~5P32
is a process for preparing to accept regular interrupts from outside.

In addition, in the flowchart of FIG. 2, the input circuits 21 to 2n
This assumes a case where a contact signal is input from the input circuit, but it can also be applied to a case where a one-shot signal is input from each input circuit. In this case, it can be dealt with by deleting steps such as SP7.8PQ and 5P18 in the flowchart of FIG.

(Effects of the Invention) As explained above, according to the present invention, a failure of the interrupt input device itself can be quickly discovered by performing the operations shown in the flowchart of FIG. 2 at regular intervals. A highly reliable system can be realized with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of the apparatus according to the present invention, and FIG. 2 is a flowchart showing an example of the operation. 1"・CPU, 21~2n - Input circuit 3... Interrupt input device 31... Input terminal 32...
・Interrupt input reception circuit

Claims (1)

[Claims] an interrupt input reception circuit that inputs an interrupt signal output from an input/output device, outputs interrupt data and an interrupt interrupt signal to a computer, and receives a factor reset signal from the computer; a check data output circuit that inputs check data to the input side of the interrupt input reception circuit; a first switch that is driven by a signal from the computer and controls the operation or non-operation of the check data output circuit; an interrupt input device comprising: a second switch connected to a common line of the output device and controlling operation/non-operation of the input/output circuit according to a signal from the computer;