JPS5775303A - Peventing device for erroneous control of controller - Google Patents

Peventing device for erroneous control of controller

Info

Publication number
JPS5775303A
JPS5775303A JP15084880A JP15084880A JPS5775303A JP S5775303 A JPS5775303 A JP S5775303A JP 15084880 A JP15084880 A JP 15084880A JP 15084880 A JP15084880 A JP 15084880A JP S5775303 A JPS5775303 A JP S5775303A
Authority
JP
Japan
Prior art keywords
output
control
input
relay
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15084880A
Other languages
Japanese (ja)
Inventor
Takeshi Ito
Kazutada Taniguchi
Kouichi Tsuchikura
Hironobu Watanabe
Noritoshi Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JAPANESE NATIONAL RAILWAYS<JNR>
Hitachi Ltd
Japan National Railways
Nippon Kokuyu Tetsudo
Original Assignee
JAPANESE NATIONAL RAILWAYS<JNR>
Hitachi Ltd
Japan National Railways
Nippon Kokuyu Tetsudo
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JAPANESE NATIONAL RAILWAYS<JNR>, Hitachi Ltd, Japan National Railways, Nippon Kokuyu Tetsudo filed Critical JAPANESE NATIONAL RAILWAYS<JNR>
Priority to JP15084880A priority Critical patent/JPS5775303A/en
Publication of JPS5775303A publication Critical patent/JPS5775303A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00—Safety arrangements
    • G05B9/02—Safety arrangements electric

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To prevent the erroneous control due to a fault of an input/output device, by carrying out all inputs and outputs with binary signals along with a number of input/output points, receiving the control command input at an internal logical memory and delivering the internal arithmetic result to the control device via an external output relay. CONSTITUTION:A control command input 2, if exists, is received at a control command input DI point 3 and supplied to a logical memory A. The memory A is set at logic ''1'' with the input 2 to drive the 1st control output DO point 4 and then to actuate the 1st control output relay 5. The state of the relay 5 is fetched into a DI point 6, and the coincidence and dissidence are always monitored by a comparison monitoring circuit D between the points 4 and 6. At the same time, a timer B is actuated by the logic ''1'' output of the memory A, and the counting is started for the lapse of time. When no fault arises at a constant comparison monitoring circuit E for the 2nd control output relay, a constant detecting circuit F for an application suppressing relay and a control machinery detecting circuit G respectively until the lapse of the time set at the timer B, no suppression signal H is delivered from an input/output fault deciding circuit H.
JP15084880A 1980-10-29 1980-10-29 Peventing device for erroneous control of controller Pending JPS5775303A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15084880A JPS5775303A (en) 1980-10-29 1980-10-29 Peventing device for erroneous control of controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15084880A JPS5775303A (en) 1980-10-29 1980-10-29 Peventing device for erroneous control of controller

Publications (1)

Publication Number Publication Date
JPS5775303A true JPS5775303A (en) 1982-05-11

Family

ID=15505694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15084880A Pending JPS5775303A (en) 1980-10-29 1980-10-29 Peventing device for erroneous control of controller

Country Status (1)

Country Link
JP (1) JPS5775303A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61264401A (en) * 1985-05-20 1986-11-22 Mitsubishi Electric Corp Selection control output circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48103977A (en) * 1972-04-13 1973-12-26
JPS52147288A (en) * 1976-06-02 1977-12-07 Hitachi Ltd Misoperation prevention equipment
JPS55108057A (en) * 1979-02-13 1980-08-19 Toshiba Corp Duplex control unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48103977A (en) * 1972-04-13 1973-12-26
JPS52147288A (en) * 1976-06-02 1977-12-07 Hitachi Ltd Misoperation prevention equipment
JPS55108057A (en) * 1979-02-13 1980-08-19 Toshiba Corp Duplex control unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61264401A (en) * 1985-05-20 1986-11-22 Mitsubishi Electric Corp Selection control output circuit

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