JPS63268333A - Data reception controller - Google Patents

Abstract

PURPOSE:To facilitate the repair or extension of an input/output device by providing a means detecting an input control command signal in an input/output instruction to the input/output device and a control means keeping the state of data input inhibition and release so as to eliminate the abnormal operation due to noise. CONSTITUTION:An input control command INH/CANS is provided to an input/ output instruction sent from a central controller 1 to an input/output device 3, and the device 3 is provided with an input control means 32 applying a data input inhibition INH from a processor bus 4 and a data input inhibit release CANS and a detection means 31 detecting the input control command to command the data input inhibition INH or the data input inhibit release CANS to the control means 32. Thus, the input inhibit and its release are attained by an instruction from a central processing unit, and the flexible operation is attained for the repair or extension of the input/output device. Moreover, malfunction due to the coincidence of its own address with the noise on the bus 4 is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data reception control device, and particularly to a data reception control device suitable for use in an input/output device in an information processing system.

[Conventional technology] FIG. 5 is a partial configuration diagram of a conventional information system.

In the figure, 1 is a central control unit, 2 is a main memory, and 4 is a central controller.
is a processor bus, and 5 (5a to 5n) is an input/output device, through which the central control unit 1 transfers data between the main storage device 2 and the input/output device 5. 50 is the ■/○ address verification means of the manual blade device 5;
Reference numeral 51 denotes a control means for controlling operations within the input/output device 5.

In the above configuration, when the central control unit 1 transfers required data between the input/output device 5 and the main storage device 2 via the processor bus 4, first, the input/output data is input to/output from the input/output device via the processor bus 4. Convey orders.

In this case, the input/output command from the central control unit 1 includes an instruction code (ORD) and an I/O command that specifies the input/output device 5 to be data transferred from among the plurality of input/output devices 5, as shown in FIG.
10 addresses (IOA), and a read/write instruction (R/W) that instructs the input/output device 5 to write or read data to the main storage device 2.

Next, each input/output device 5 connected to the processor bus 4 receives an input/output command transmitted from the central controller 1, and the I10 address verification means 50 determines that the r/○ address (IOA) is the white output device. Analyze whether or not to specify 5. If it is determined that the white output device 5 has been designated, the control means 51 is activated. This control means 51 performs a format check of the input/output command, for example, a parity check, and analyzes the read/write instruction (R/W) in the input/output command if there is no error. If reading is instructed, data is sequentially stored in the register in the read control means 51 from the main memory device 2.

The detailed data transfer operation is not related to the present invention and will therefore be omitted.

As described above, conventional information systems do not include a data reception control device that prohibits or cancels the prohibition of input/output command analysis and data reception processing for input/output devices.

[Problems to be solved: Since the conventional information system described above does not have a data reception control device, as long as ■/○ addresses match,
Input/output devices operated based on input/output instructions. Therefore, when connecting or disconnecting connectors connected to the processor bus or turning on/off the power of any input/output device, the multiple input/output devices of the device are affected by noise from the processor bus, and this noise information is If the address matches the own I10 address, there is a problem in that an abnormal operation occurs based on an erroneous command in the noise information.

The present invention has been made in view of the above problems, and does not cause abnormal operation based on incorrect commands from noise information, and allows for highly flexible operation when repairing failures or expanding input/output devices. The purpose of this invention is to provide a data reception control device that can improve system reliability.

[Means for Solving Problems] In order to achieve the above object, the data reception control device of the present invention includes a detection means for detecting an input control instruction signal included in an input/output command, and a data input control device based on the output of the detection means. and input control means for maintaining the prohibited state and the prohibited state.

[Example code] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a partial configuration diagram of an information system to which a data reception control device according to an embodiment of the present invention is applied.

In the figure, 3 (3a to 3n) is an input/output device,
The input/output commands transmitted from the central control device 1 to the input/output device 3 include 11 input control instructions (INH/CANS). Further, inside the input/output device 3, 31 is a detection means for detecting an input control instruction (I NH/CANS) included in an input/output instruction from the processor bus 4, and 32 is a detection means for detecting data input inhibition and data input based on the input control instruction. This is input control means for canceling input inhibition.

In this case, based on instructions from the central controller 1, a processor bus 4 is connected between the main memory 2 and the input/output device 3.
In an information processing system that transfers data via a processor bus 4, an input control instruction (INH/CANS) is provided in an input/output command transmitted from a central controller 1 to an input/output device 3, and a Prohibition of data entry (I
The input control means 32 detects the input control instruction (INH/CANS) included in the input/output command transmitted from the central control unit l, and performs the input control means 32 for canceling data input prohibition (NH) and data input inhibition (CANS). Data input prohibited (INH)
and detection means 31 for instructing either data input prohibition release (CANS).

2 is a block diagram showing the input/output device 3 in FIG. 1 in more detail, FIG. 3 is a timing chart showing operation waveforms in the input/output device 3 in FIG. 2, and FIG. 4 is a block diagram showing the input/output device 3 in FIG. 2. FIG. 3 is a diagram showing the configuration.

In FIG. 2, 310 is a decoding circuit, . . . 311
．． 316 is flip-prop, 314°315 is AND
The gate circuits 312 and 313 are delay circuits, and these constitute the detection means 31. Also, 320,321
is an AND gate circuit and constitutes the input control means 32.

In the above configuration, when the central control unit 1 prohibits the input/output device 3 from inputting data, it sends an input control instruction (, NH/CANS) is set to data input inhibit mode (INH).

In this case, in each input/output device 3 connected to the processor bus 4, the decoding circuit 310 receives the input/output command transmitted from the processor bus 4, and enters the data input prohibition mode.
INH) is detected, the flip-flop 311 is set by the output line a, and the output Q of the flip-flop 311 is set.
is input to the AND gate circuit 315 via the output line C via the delay circuit 313.

On the other hand, the central control device 1 outputs the same command after 500 m5 has elapsed. When the input/output device 3 receives an input/output command in which the data input inhibit mode (INH) is set again after 500 m5 has elapsed, the AND gate circuit H315 sets the flip-flop 316 through the output line d. The output d of the flip-flop 316 is ANDed by the output line Q.
The signal is input to gate circuits 320 and 321 to inhibit data input from processor bus 4. That is, data from the processor bus 4 is not transmitted to the control means 34 and the I10 address verification means 33.

On the other hand, when the central control device 1 cancels the data input prohibition of the input/output device 3, it sends an input control instruction (■NH/CANS) to the input/output device 3 via the processor bus 4 in the data input prohibition cancellation mode. Transmits input/output commands set to (CANS).

In this case, in each input/output device 3 connected to the processor bus 4, when the decoding circuit 310 receives the input/output command transmitted from the processor bus 4 and detects the data input inhibition release mode (CANS), the output line f The flip-flop 311 is reset by. flip flop 31
The output Φ of 1 is input to an AND gate circuit 314 via an output line via a delay circuit 312.

As in the previous case, the central control unit 1 has 500 tn
The same command is output after s has elapsed. When the input/output device 3 receives an input/output command in which the data input prohibition release mode (CA'NS) is set again after 500 rn s have elapsed, the AND gate circuit 314 resets the flip-flop 31 (3) using the output line i. The output Q of the flip-flop 316 is input to the AND gate circuits 320 and 321 via the output line Ω, allowing data input from the processor bus 4.
It is possible to input data from the input/output device 3 to the control means 34 and the I10 address verification means 33.

As is clear from the above description, according to this embodiment, the central controller 1 sends an input control instruction (INH/CANS) to either the data input prohibition mode (INH) or the data input prohibition release mode (CANS). Depending on the setting, it is possible to inhibit data input from the processor bus 4 to the input/output device 3 or cancel the inhibition of data input. Also,
Because it operates with double input/output commands spaced at regular intervals, malfunctions due to noise are extremely rare.

Note that FIG. 2 is only one embodiment of the present invention, and the configuration of input/output commands, for example, is not limited to what is shown in the figure, and many other modifications may be considered, but in any case However, the effect of the present invention remains unchanged. In addition, input/output device 3
The configuration of is not limited to that shown in the drawings, and many other modifications may be considered, but the effects of the present invention remain the same in any case.

[Effects of the Invention] As explained above, the present invention makes it possible to prohibit data input to an input/output device and to release the prohibition by commands from a central control unit, thereby improving the effectiveness of the input/output device when repairing a failure or expanding the input/output device. This has the effect of enabling flexible operation and improving system reliability.

[Brief explanation of the drawing]

FIG. 1 is a partial configuration diagram of an information system to which a data reception control device according to an embodiment of the present invention is applied, and FIG.
3 is a timing chart of the data reception control device in FIG. 2, FIG. 4 is a diagram showing input/output commands of the reception control device in FIG. 1, and FIG. 5 is a conventional FIG. 6 is a diagram illustrating input/output commands of the reception control device of FIG. 5. FIG. 31: Detection means 32: Input control means

Claims (2)

[Claims] (1) In a data reception control device that controls data reception based on an input/output command, there is a detection means for detecting an input control instruction signal included in the input/output command, and a prohibition of data input based on the output of this detection means. What is claimed is: 1. A data reception control device comprising: input control means for maintaining the state and the prohibition release state. (2) The data reception control device according to claim 1, wherein the detection means includes a delay detection circuit that detects coincidence of input/output commands sent out at regular intervals.