JPS6226741B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to preventing malfunction of an output circuit that converts a digital output signal into a signal form necessary for a controlled object.

Generally, there is a digital control device including an output circuit as shown in FIG. In the figure, 1 is a central processing unit (CPU), 2 is a memory that stores programs and data, 3 is a bus consisting of data signals, address signals, and control signals, 4 is an input signal, and 5 is a controller that controls the input signal 4. 6 is an input control circuit that controls the input circuit 5 according to instructions from the CPU 1; 7 is an output circuit that converts the digital output signal into a signal form necessary for the controlled object; 8 is an instruction from the CPU 1. 9 is an output signal.

In the digital control device shown in FIG.
The output circuit 7 was shown in FIG. In the figure, 10 is a memory that latches the input signal and maintains the output based on the activation signal, 11 is a matching circuit that detects the match between the self address and the address signal from CPU 1, and 12 is an AND circuit, which controls the output. It is part of circuit 8. Further, 3a is a data signal (supposed to be composed of 8 bits), 3b is an address signal, and 3c is a control signal.
This is the activation signal. The output circuit 7 is composed of the following circuits. 13 is a switching element, 1
4-1 to 14-8 are transistors, 15-1 to 1
5-8 is an output relay, 15-1a to 15-8a are normally open contacts of output relays 15-1 to 15-8, 16
1 is a power supply that energizes the output relays 15-1 to 15-8, and 17 is a terminal for supplying a signal form necessary for the controlled object.

Next, the operation will be explained. cpu1 to bus3
An 8-bit data signal 3a, an address signal 3b, and an activation signal 3c are sent out as pulse signals of "1" and "0" through the circuit. The matching circuit 11 receives the data signal 3
It is determined whether or not a is an output control signal using the address signal 3b, and if it matches the self address, the gate of the AND circuit 12 is opened. On the other hand, the activation signal 3c is a data signal 3a and an address signal 3b.
It is sent from CPU 1 a little later than that and is sent to AND circuit 1.
Added to 2. When the gate of the AND circuit 12 is open, the data signal 3a applied to the memory 10 is latched as a start signal for the memory 10. The latched contents of memory 10 are the next CPU
The output is maintained until it is rewritten by the data signal from 1.

The data signal 3a stored in the memory 10 as described above is transmitted to the switching element 1 of the output circuit 7.
Transistor 1 corresponding to each as the input signal of 3
4-1 to 14-8 are turned on and off to drive output relays 15-1 to 15-8. The driven output relays have corresponding normally open contacts 15-1a to 15-8a.
is closed, and a signal is output from the supply terminal 17 to the controlled object.

The output circuit of a conventional digital control device is configured as described above, so if a signal bit error occurs due to a hardware failure, including the bus 3 and output control circuit 8, resulting in a malfunction, the plant being controlled will be affected. There was a risk of a serious accident. especially,
In systems where reliability is required, in order to prevent output malfunctions, a two-step output control method is used in which the output signal is processed again as an input signal and is output as an output signal only when the result matches the previous output signal. However, this method requires a large number of input/output circuits in order to re-input the output signal, and has the disadvantage that the output response becomes poor, making the device larger, more expensive, and lowering performance.

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional circuit, and provides an output circuit that can prevent malfunctions by using a check signal synchronized with a data signal.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, 10a is a memory included in the output control circuit 8 that latches the input signal in response to the activation signal 3c and maintains the output. 3d is a control signal and is a check signal synchronized with the data signal 3a, for example, 1 bit, which performs a parity check together with the data signal 3a (in this case, it is assumed that the number of 9-bit "1"s is even and normal). )I do. 1
3a is a switching element, 16-1 is a voltage obtained by converting the power supply 16 for energizing the output relay to an appropriate value using voltage dividing resistors 18-1 and 19-1 when the transistor 14-1 is off; 16-2 to 3a; 16-8 also 16-1
Similarly, voltage dividing resistors 18-2 to 18-8, 19-2
~ Voltage divided by 19-8, 20-1 ~ 20-
8 is a diode for backflow prevention, and 21 is a voltage 16-1 to 16 based on an input signal from the data signal 3a.
-8 is a detection circuit that performs a parity check using "1" and "0" and the check signal 3d, and 22 is a detection relay that is driven when an abnormality is detected in the detection circuit 21, and from output relays 15-1 to 15-8. 22b, which has a fast response time, is a normally closed contact that opens when the detection relay 22 is driven.

Next, the operation of the embodiment will be explained. The CPU 1 outputs a data signal 3a and a check signal 3d for detecting bit errors in synchronization. This check signal 3d is stored in the memory 10d in the same way as the data signal 3a and is applied to the detection circuit 21. On the other hand, the data signal 3 stored in the memory 10
a is an input signal to the transistors 14-1 to 14 of the switching element 13a in the output circuit 7.
-8 is turned on and off. Transistor 14-
Voltage 16-1 as 1 to 14-8 turn on and off
“1” and “0” from ~16-8 are applied to the detection circuit 21, and output relays 15-1 to 15-8
is driven.

The detection circuit 21 performs a parity check using the input check signal 3d and voltages 16-1 to 16-8. For example, if the number of 9-bit "1"s is odd, it is determined that a bit error has occurred in the data signal 3a. Based on the judgment, the detection relay 22 is driven. The driven detection relay 22 is connected to the power supply 1 for energizing the output relay.
6, the normally closed contact 22b is opened. In other words, the detection relay 22 having a fast response time operates before the output relays 15-1 to 15-8 are driven to close the normally open contacts, thereby preventing erroneous output. Detection circuit 2
When the result of step 1 is normal, the corresponding normally open contacts 15-1a to 15-8a are closed by the driven output relay, and a signal is output from the supply terminal 17 to the controlled object.

In the above embodiment, the check signal 3d and the detection circuit 21 have a parity check function, but the present invention is not limited to the parity check, and other detection means that utilize a check signal and a data signal may be used.

Furthermore, it goes without saying that the transistors 14-1 to 14-8, the output relays 15-1 to 15-8, and the detection relay 22 only need to operate as switches.

As described above, according to the present invention, the output data and the check signal added to this data are verified at the final stage, and it is determined whether or not to output the data according to the verification result, so that the check signal synchronized with the data signal is The signal can be used to prevent malfunctions, the device is inexpensive, and it has the effect of providing high precision and high speed response.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital control device including an output circuit, FIG. 2 is a circuit diagram showing a conventional output circuit, and FIG. 3 is a circuit diagram showing an embodiment of the output circuit according to the present invention. In the figure, 3a is a data signal, 3b is an address signal, 3c is a start signal, 3d is a check signal,
9 is an output signal, 10 and 10a are memories, 11 is a coincidence circuit, 12 is an AND circuit, 13a is a switching element, 14-1 to 14-8 are transistors, 1
5-1 to 15-8 are output relays, 15-1a to 1
5-8a is a normally open contact, 16 is a power supply, 16-1 to 1
6-8 is the divided voltage, 17 is the supply terminal, 18
-1 to 18-8, 19-1 to 19-8 are voltage dividing resistors, 20-1 to 20-8 are diodes, 21 is a detection circuit, 22 is a detection relay, and 22b is a normally closed contact. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A central processing unit that synchronously outputs a data signal and a check signal for detecting bit errors, a final output switching element that operates in accordance with the data signal, and a final output switching element that controls the output of this final output switching element. Detection for detecting the on/off state of the final output switching element by applying a power source other than the power supply to the final output switching element, and determining the quality of the output data based on the detected data and the check signal. and a control means for controlling a common line of the final output switching element according to a determination result of the detection means.