JPH0157437B2 - - Google Patents
Info
- Publication number
- JPH0157437B2 JPH0157437B2 JP56010454A JP1045481A JPH0157437B2 JP H0157437 B2 JPH0157437 B2 JP H0157437B2 JP 56010454 A JP56010454 A JP 56010454A JP 1045481 A JP1045481 A JP 1045481A JP H0157437 B2 JPH0157437 B2 JP H0157437B2
- Authority
- JP
- Japan
- Prior art keywords
- refresh operation
- refresh
- activation
- storage device
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000004913 activation Effects 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 description 10
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000007429 general method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
本発明は、リフレツシユ動作を必要とする記憶
装置に対して、安定したリフレツシユ動作の実施
を可能としたリフレツシユ制御方式に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a refresh control method that makes it possible to perform a stable refresh operation on a storage device that requires a refresh operation.
ICメモリ等、リフレツシユ動作を必要とする
記憶装置に対して、従来は１つのリフレツシユ動
作起動装置によりリフレツシユ動作を起動してい
るのが普通である。このため、該リフレツシユ動
作起動装置の障害により、リフレツシユ動作起動
信号が記憶装置に印加されなくなつた場合、リフ
レツシユ動作は起動されなくなり、単一部の障害
で記憶装置に記憶されている全ての記憶情報が失
なわれるという欠点があつた。一方、リフレツシ
ユ動作を必要とする記憶装置に対して複数のリフ
レツシユ動作起動装置を持つたものもあるが、こ
の場合も、複数のうちの１つのリフレツシユ動作
起動装置のみを指定して、この指定されたリフレ
ツシユ動作起動装置のみがリフレツシユ動作を起
動し、その他のリフレツシユ動作起動装置は予備
として待機させ、動作中の装置が故障すると、予
備の装置に切替える構成をとつているため、予備
のリフレツシユ動作起動装置に切替わる間、記憶
装置のリフレツシユ動作は起動されなくなり、上
述と同様に、記憶装置に記憶されている全ての記
憶情報が失なわれることになる。 Conventionally, for a storage device such as an IC memory that requires a refresh operation, a single refresh operation activation device is used to activate the refresh operation. Therefore, if the refresh operation activation signal is no longer applied to the storage device due to a failure in the refresh operation activation device, the refresh operation will no longer be activated, and all memories stored in the storage device will be lost due to a failure in a single part. The drawback was that information was lost. On the other hand, some storage devices that require refresh operations have multiple refresh operation activation devices, but in this case as well, only one of the multiple refresh operation activation devices can be specified, and this specified Only the refresh operation activation device that has been used activates the refresh operation, and the other refresh operation activation devices are kept on standby as backups.If the operating device breaks down, the system switches to the backup device, so the backup refresh operation activation device is configured to During the switching to the device, the refresh operation of the storage device will not be activated, and all storage information stored in the storage device will be lost, similar to the above.
本発明は上記従来の欠点を解決するため、複数
のリフレツシユ動作起動装置から同時にリフレツ
シユ動作を起動することにより、リフレツシユ動
作起動装置のすべてがリフレツシユ動作起動がで
きなくなるまでは記憶装置に対するリフレツシユ
動作を起動可能なようにしたもので、以下図面に
従つて詳細に説明する。 In order to solve the above-mentioned conventional drawbacks, the present invention starts the refresh operation from a plurality of refresh operation starting devices at the same time, and starts the refresh operation for the storage device until all of the refresh operation starting devices can no longer start the refresh operation. This will be explained in detail below with reference to the drawings.
第１図は本発明の一実施例であつて、２台のリ
フレツシユ動作起動装置を持つ場合を示したもの
である。第１図において、１１，１２はそれぞれ
リフレツシユ動作起動装置であり、２１はリフレ
ツシユ動作起動装置間の制御信号交信線で１１お
よび１２のリフレツシユ動作起動装置間を接続す
る。３１は記憶装置、４１および４２はリフレツ
シユ動作起動信号線である。１１および１２のリ
フレツシユ動作起動装置はそれぞれリフレツシユ
動作起動信号線４１，４２によつて３１の記憶装
置に接続されている。記憶装置３１は、リフレツ
シユ動作起動信号受付制御部５１、リフレツシユ
制御部６１および記憶部７１から構成されてい
る。リフレツシユ動作起動信号線４１および４２
よつて記憶装置３１に入力されたリフレツシユ動
作起動信号はリフレツシユ動作起動信号受付制御
部５１に直接印される。このリフレツシユ動作起
動信号受付制御部５１の出力はリフレツシユ制御
部６１へ、該リフレツシユ制御部６１の出力は記
憶部７１に印される。リフレツシユ動作起動信号
受付制御部５１は８１および８２のリフレツシユ
動作起動信号監視回路と論理積ゲート９１および
９２、論理和ゲート９３により構成される。リフ
レツシユ動作起動信号監視回路８１はリフレツシ
ユ動作起動信号線４１に接続され、更にこのリフ
レツシユ動作起動信号監視回路８１の出力側はリ
フレツシユ動作起動信号線４１とゝもに論理積ゲ
ート９１に接続される。また、リフレツシユ動作
起動信号監視回路８２はリフレツシユ動作起動信
号４２に接続され、更にこの８２の出力側はリフ
レツシユ動作起動信号線４２とゝもに論理積ゲー
ト９２に接続される。論理積ゲート９１および９
２の出力側は論理和ゲート９３に接続される。こ
の論理和ゲート９３の出力がリフレツシユ動作起
動信号受付制御部５１の出力に相当し、リフレツ
シユ制御部６１に印加される。 FIG. 1 shows an embodiment of the present invention in which two refresh operation starting devices are provided. In FIG. 1, reference numerals 11 and 12 are refresh operation starting devices, respectively, and 21 is a control signal communication line between the refresh operation starting devices, which connects the refresh operation starting devices 11 and 12. 31 is a storage device, and 41 and 42 are refresh operation start signal lines. The refresh operation activation devices 11 and 12 are connected to the storage device 31 by refresh operation activation signal lines 41 and 42, respectively. The storage device 31 includes a refresh operation activation signal reception control section 51, a refresh control section 61, and a storage section 71. Refresh operation start signal lines 41 and 42
Therefore, the refresh operation activation signal inputted to the storage device 31 is directly printed on the refresh operation activation signal reception control section 51. The output of the refresh operation activation signal reception control section 51 is written to the refresh control section 61, and the output of the refresh control section 61 is written on the storage section 71. The refresh operation activation signal reception control section 51 is composed of refresh operation activation signal monitoring circuits 81 and 82, AND gates 91 and 92, and an OR gate 93. The refresh operation activation signal monitoring circuit 81 is connected to the refresh operation activation signal line 41, and the output side of the refresh operation activation signal monitoring circuit 81 is connected to the AND gate 91 together with the refresh operation activation signal line 41. Further, the refresh operation start signal monitoring circuit 82 is connected to the refresh operation start signal 42, and the output side of this 82 is connected to the AND gate 92 together with the refresh operation start signal line 42. AND gates 91 and 9
The output side of 2 is connected to an OR gate 93. The output of this OR gate 93 corresponds to the output of the refresh operation activation signal reception control section 51 and is applied to the refresh control section 61.
第１図の実施例の動作は次の通りである。リフ
レツシユ動作起動装置１１および１２は一定周期
ごとに４１および４２のリフレツシユ動作起動信
号線にそれぞれ論理“１”のリフレツシユ動作起
動パルスを送出することにより、記憶装置３１に
対してリフレツシユ動作を開始するよう起動をか
ける。このリフレツシユ動作起動装置１１および
１２は、２１のリフレツシユ動作起動装置間制御
信号交信線により、装置の動作開始にあたり、信
号線４１および４２へのリフレツシユ動作起動パ
ルス送出を同時におこなえるよう制御されるが、
動作開始後は、該リフレツシユ動作起動装置１
１，１２は各々独立に動作する。４１および４２
のリフレツシユ動作起動信号線上に送出されたリ
フレツシユ動作起動パルスは、リフレツシユ動作
起動信号受付制御部５１内のリフレツシユ動作起
動信号監視回路８１および８２によりそれぞれ常
に正常性を検査される。このパルスの正常性の一
般的な検査方法を第２図を用いて説明する。 The operation of the embodiment of FIG. 1 is as follows. The refresh operation starting devices 11 and 12 start the refresh operation for the storage device 31 by sending out refresh operation starting pulses of logic "1" to the refresh operation starting signal lines 41 and 42 at regular intervals. Start it up. The refresh operation starting devices 11 and 12 are controlled by the inter-refresh operation starting device control signal communication line 21 so that they can simultaneously send refresh operation starting pulses to the signal lines 41 and 42 when starting the operation of the devices.
After the operation starts, the refresh operation starting device 1
1 and 12 each operate independently. 41 and 42
The refresh operation activation pulses sent onto the refresh operation activation signal line are constantly checked for normality by the refresh operation activation signal monitoring circuits 81 and 82 in the refresh operation activation signal reception control section 51, respectively. A general method for testing the normality of this pulse will be explained using FIG. 2.
今、リフレツシユ動作起動パルス幅TREFREQWを
記憶装置のリフレツシユ動作サイクル時間
TREFCYCより小さな値となるようにリフレツシユ
動作起動装置１１，１２と記憶装置３１間のイン
ターフエース仕様を決めておく。リフレツシユ動
作起動信号監視回路８１および８２の出力は、通
常、常に論理“１”の状態をとり、信号線４１お
よび４２よりリフレツシユ動作起動信号を受信す
ると、該記憶装置３１のリフレツシユ動作を開始
せしめる。同時に、このリフレツシユ動作開始
後、TREFREQWより大きく、TREFCYCより小さなT1時
間後に信号線４１よび４２上のリフレツシユ動作
起動パルスの状態を検査する。この時、信号線４
１，４２上の論理の状態が“０”であれば、リフ
レツシユ動作起動信号は正常に動作していること
が検出できる。逆に信号線４１，４２上の論理が
“１”であれば、リフレツシユ動作起動信号が異
常であることが検出できる。一方、リフレツシユ
動作起動信号は、正常であればTREFの周期で発生
されている。この周期が短かくなる異常の検出の
ために、T1以後、TREFよりも小さなT2時間まで
の間、連続して検査しておけばよい。 Now, let the refresh operation start pulse width T REFREQW be the refresh operation cycle time of the storage device.
The interface specifications between the refresh operation activation devices 11, 12 and the storage device 31 are determined so that the value is smaller than T REFCYC . The outputs of the refresh operation start signal monitoring circuits 81 and 82 normally always take a logic "1" state, and when a refresh operation start signal is received from the signal lines 41 and 42, the refresh operation of the storage device 31 is started. At the same time, the state of the refresh operation activation pulses on the signal lines 41 and 42 is checked after 1 hour T, which is greater than T REFREQW and smaller than T REFCYC , after the start of this refresh operation. At this time, signal line 4
If the logic state on 1 and 42 is "0", it can be detected that the refresh operation activation signal is operating normally. Conversely, if the logic on the signal lines 41 and 42 is "1", it can be detected that the refresh operation activation signal is abnormal. On the other hand, the refresh operation activation signal is normally generated at a cycle of T REF . In order to detect an abnormality in which this cycle becomes short, it is sufficient to continuously test after T 1 until T 2 hours, which is smaller than T REF .
このようにして、リフレツシユ動作起動信号監
視回路８１および８２はリフレツシユ動作起動信
号の正常性を検査し、正常である間は出力を論理
“１”に保持し、異常が検出された場合、出力を
論理“０”にする。したがつて、論理積ゲート９
１および９２は、正常にリフレツシユ動作起動が
なされている場合はリフレツシユ起動パルスをそ
れぞれ出力する。このリフレツシユ起動パルスが
論理和ゲート９３によつてまとめられ、リフレツ
シユ制御部６１に印加されることにより、記憶部
７１のリフレツシユ動作が起動される。一方、リ
フレツシユ動作起動が異常になると、異常となつ
た１１あるいは１２のリフレツシユ動作起動装置
に対応した８１あるいは８２のリフレツシユ動作
起動信号監視回路の出力が論理“０”となるた
め、９１あるいは９２のゲートは閉じてしまい、
異常の発生したリフレツシユ動作起動装置から与
えられるリフレツシユ動作起動信号の受信は停止
し、正常なリフレツシユ動作起動装置のみからの
起動に従い記憶部７１のリフレツシユ動作が起動
する。 In this way, the refresh operation start signal monitoring circuits 81 and 82 inspect the normality of the refresh operation start signal, and while the refresh operation start signal is normal, the output is held at logic "1", and when an abnormality is detected, the output is Set to logic “0”. Therefore, AND gate 9
1 and 92 each output a refresh activation pulse when the refresh operation is activated normally. The refresh activation pulses are collected by the OR gate 93 and applied to the refresh control section 61, thereby activating the refresh operation of the storage section 71. On the other hand, when the refresh operation activation becomes abnormal, the output of the refresh operation activation signal monitoring circuit 81 or 82 corresponding to the abnormal refresh operation activation device 11 or 12 becomes logic "0". The gate is closed,
The reception of the refresh operation activation signal given from the refresh operation activation device in which the abnormality has occurred is stopped, and the refresh operation of the storage section 71 is activated in accordance with activation only from the normal refresh operation activation device.
なお、リフレツシユ動作起動パルスが送出され
ない障害は、リフレツシユ動作起動信号監視回路
８１および８２では検出できないが、いずれかの
リフレツシユ動作起動装置より正常なリフレツシ
ユ動作起動信号が送出されていればリフレツシユ
動作の起動をすることができるため、問題はな
い。 Note that a failure in which the refresh operation activation pulse is not sent cannot be detected by the refresh operation activation signal monitoring circuits 81 and 82, but if a normal refresh operation activation signal is sent from any of the refresh operation activation devices, the refresh operation will be activated. There is no problem because it can be done.
以上説明したように、本発明によれば、複数の
リフレツシユ動作起動装置より同時にリフレツシ
ユ動作を起動することにより、いずれか１つのリ
フレツシユ動作起動装置が正常であれば記憶装置
に対して正常なリフレツシユ動作の起動が可能
で、単一部の障害で記憶装置の保持する全ての情
報が破壊する事を防止できる。 As explained above, according to the present invention, by activating the refresh operation from a plurality of refresh operation activation devices at the same time, if any one of the refresh operation activation devices is normal, the refresh operation is performed normally for the storage device. , and can prevent all information held by the storage device from being destroyed due to failure of a single part.
第１図は本発明の一実施例の構成図、第２図は
第１図の動作を説明するためのタイミング図であ
る。
１１，１２……リフレツシユ動作起動装置、３
１……記憶装置、４１，４２……リフレツシユ動
作起動信号線、５１……リフレツシユ動作起動信
号受付制御部、６１……リフレツシユ制御部、７
１……記憶部、８１，８２……リフレツシユ動作
起動信号監視回路。
FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of FIG. 1. 11, 12...Refresh operation starting device, 3
DESCRIPTION OF SYMBOLS 1...Storage device, 41, 42...Refresh operation start signal line, 51...Refresh operation start signal reception control unit, 61...Refresh control unit, 7
1...Storage unit, 81, 82...Refresh operation start signal monitoring circuit.
Claims (1)
リフレツシユ動作を行う必要のある記憶装置に対
して、複数のリフレツシユ動作起動装置より同時
にリフレシツシユ動作を指示し、該リフレツシユ
動作の指示を受けた記憶装置は、前記複数のリフ
レツシユ動作起動装置から受け取るそれぞれのリ
フレツシユ起動信号について、該リフレツシユ起
動信号の終了時刻から、次のリフレツシユ動作開
始時刻まで信号レベルを監視し、この間に信号を
検出しなかつたリフレツシユ起動信号により記憶
装置内のリフレツシユ動作を開始させることを特
徴とするリフレツシユ制御方式。1. A storage device that is required to perform a refresh operation at regular intervals in order to retain stored information is instructed to perform a refresh operation at the same time by a plurality of refresh operation activation devices, and a storage device that receives an instruction to perform the refresh operation. monitors the signal level of each refresh activation signal received from the plurality of refresh activation devices from the end time of the refresh activation signal until the next refresh operation start time, and detects a refresh activation signal for which no signal is detected during this period. A refresh control method characterized by starting a refresh operation within a storage device in response to a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56010454A JPS57127991A (en) | 1981-01-27 | 1981-01-27 | Refresh controlling system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56010454A JPS57127991A (en) | 1981-01-27 | 1981-01-27 | Refresh controlling system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57127991A JPS57127991A (en) | 1982-08-09 |
| JPH0157437B2 true JPH0157437B2 (en) | 1989-12-05 |
Family
ID=11750583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56010454A Granted JPS57127991A (en) | 1981-01-27 | 1981-01-27 | Refresh controlling system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57127991A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4453927B2 (en) | 2007-11-19 | 2010-04-21 | 株式会社山田製作所 | Oil pump resonator |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51149730A (en) * | 1975-06-13 | 1976-12-22 | Hitachi Ltd | Refreshing system for ic memory |
| JPS55160391A (en) * | 1979-06-01 | 1980-12-13 | Hitachi Ltd | Abnormal load current prevention system of memory unit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5611278Y2 (en) * | 1980-01-17 | 1981-03-13 |
-
1981
- 1981-01-27 JP JP56010454A patent/JPS57127991A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51149730A (en) * | 1975-06-13 | 1976-12-22 | Hitachi Ltd | Refreshing system for ic memory |
| JPS55160391A (en) * | 1979-06-01 | 1980-12-13 | Hitachi Ltd | Abnormal load current prevention system of memory unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57127991A (en) | 1982-08-09 |
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