JPS6126106B2 - - Google Patents

Info

Publication number
JPS6126106B2
JPS6126106B2 JP57091010A JP9101082A JPS6126106B2 JP S6126106 B2 JPS6126106 B2 JP S6126106B2 JP 57091010 A JP57091010 A JP 57091010A JP 9101082 A JP9101082 A JP 9101082A JP S6126106 B2 JPS6126106 B2 JP S6126106B2
Authority
JP
Japan
Prior art keywords
destination
user
file
processing unit
management information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57091010A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58207131A (ja
Inventor
Kazuo Yajima
Kyoshi Oomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP57091010A priority Critical patent/JPS58207131A/ja
Publication of JPS58207131A publication Critical patent/JPS58207131A/ja
Publication of JPS6126106B2 publication Critical patent/JPS6126106B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Between Computers (AREA)
  • Computer And Data Communications (AREA)
JP57091010A 1982-05-28 1982-05-28 メ−ル宛先管理制御方式 Granted JPS58207131A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57091010A JPS58207131A (ja) 1982-05-28 1982-05-28 メ−ル宛先管理制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57091010A JPS58207131A (ja) 1982-05-28 1982-05-28 メ−ル宛先管理制御方式

Publications (2)

Publication Number Publication Date
JPS58207131A JPS58207131A (ja) 1983-12-02
JPS6126106B2 true JPS6126106B2 (enrdf_load_stackoverflow) 1986-06-19

Family

ID=14014548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57091010A Granted JPS58207131A (ja) 1982-05-28 1982-05-28 メ−ル宛先管理制御方式

Country Status (1)

Country Link
JP (1) JPS58207131A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61163749A (ja) * 1985-01-14 1986-07-24 Nec Corp 情報送信装置
JP2619982B2 (ja) * 1990-11-30 1997-06-11 富士通株式会社 通信制御システム

Also Published As

Publication number Publication date
JPS58207131A (ja) 1983-12-02

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