JPS6126104B2 - - Google Patents

Info

Publication number
JPS6126104B2
JPS6126104B2 JP6105282A JP6105282A JPS6126104B2 JP S6126104 B2 JPS6126104 B2 JP S6126104B2 JP 6105282 A JP6105282 A JP 6105282A JP 6105282 A JP6105282 A JP 6105282A JP S6126104 B2 JPS6126104 B2 JP S6126104B2
Authority
JP
Japan
Prior art keywords
bus
memory
main memory
buses
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6105282A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58178454A (ja
Inventor
Tsutomu Sumimoto
Shuichi Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP6105282A priority Critical patent/JPS58178454A/ja
Publication of JPS58178454A publication Critical patent/JPS58178454A/ja
Publication of JPS6126104B2 publication Critical patent/JPS6126104B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
JP6105282A 1982-04-14 1982-04-14 メモリ制御方式 Granted JPS58178454A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6105282A JPS58178454A (ja) 1982-04-14 1982-04-14 メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6105282A JPS58178454A (ja) 1982-04-14 1982-04-14 メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS58178454A JPS58178454A (ja) 1983-10-19
JPS6126104B2 true JPS6126104B2 (enrdf_load_stackoverflow) 1986-06-19

Family

ID=13160055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6105282A Granted JPS58178454A (ja) 1982-04-14 1982-04-14 メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS58178454A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NO173304C (no) * 1984-12-20 1993-11-24 Honeywell Inc Dobbelt buss-system
US4612542A (en) * 1984-12-20 1986-09-16 Honeywell Inc. Apparatus for arbitrating between a plurality of requestor elements

Also Published As

Publication number Publication date
JPS58178454A (ja) 1983-10-19

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