JPS58178454A - メモリ制御方式 - Google Patents

メモリ制御方式

Info

Publication number
JPS58178454A
JPS58178454A JP6105282A JP6105282A JPS58178454A JP S58178454 A JPS58178454 A JP S58178454A JP 6105282 A JP6105282 A JP 6105282A JP 6105282 A JP6105282 A JP 6105282A JP S58178454 A JPS58178454 A JP S58178454A
Authority
JP
Japan
Prior art keywords
memory
bus
cpu
circuit
access request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6105282A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6126104B2 (enrdf_load_stackoverflow
Inventor
Tsutomu Sumimoto
勉 住本
Shuichi Abe
秀一 安部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP6105282A priority Critical patent/JPS58178454A/ja
Publication of JPS58178454A publication Critical patent/JPS58178454A/ja
Publication of JPS6126104B2 publication Critical patent/JPS6126104B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
JP6105282A 1982-04-14 1982-04-14 メモリ制御方式 Granted JPS58178454A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6105282A JPS58178454A (ja) 1982-04-14 1982-04-14 メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6105282A JPS58178454A (ja) 1982-04-14 1982-04-14 メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS58178454A true JPS58178454A (ja) 1983-10-19
JPS6126104B2 JPS6126104B2 (enrdf_load_stackoverflow) 1986-06-19

Family

ID=13160055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6105282A Granted JPS58178454A (ja) 1982-04-14 1982-04-14 メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS58178454A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61150054A (ja) * 1984-12-20 1986-07-08 ハネウエル・インコーポレーテツド データ処理装置
JPS61151767A (ja) * 1984-12-20 1986-07-10 ハネウエル・インコーポレーテツド 仲裁回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61150054A (ja) * 1984-12-20 1986-07-08 ハネウエル・インコーポレーテツド データ処理装置
JPS61151767A (ja) * 1984-12-20 1986-07-10 ハネウエル・インコーポレーテツド 仲裁回路

Also Published As

Publication number Publication date
JPS6126104B2 (enrdf_load_stackoverflow) 1986-06-19

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