JPS61241952A - 半導体装置 - Google Patents

半導体装置

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Publication number
JPS61241952A
JPS61241952A JP60082460A JP8246085A JPS61241952A JP S61241952 A JPS61241952 A JP S61241952A JP 60082460 A JP60082460 A JP 60082460A JP 8246085 A JP8246085 A JP 8246085A JP S61241952 A JPS61241952 A JP S61241952A
Authority
JP
Japan
Prior art keywords
lead
glass
package
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60082460A
Other languages
English (en)
Inventor
Shunji Koike
俊二 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60082460A priority Critical patent/JPS61241952A/ja
Publication of JPS61241952A publication Critical patent/JPS61241952A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、ガラス封止型半導体装置の気密封止に適用し
て有効な技術に関する。
［′ｉ！景技術］ ガラス封止型半導体装置は、セラミックからなるパッケ
ージ基板のベレット取付部にペレットを取付けた後、該
基板の周囲にリードフレームを低融点ガラスで接着固定
し、次いで前記ペレットのボンデングパッドとリード内
端部とをワイヤボンディングして電気的に接続し、さら
にパッケージ基板の周囲あ前記リードフレーム固定部の
上に重ねた低融点ガラスを介して、セラミックからなる
キャブを接着して内部を封止してなるものである。
その後外部リード部を成形して完成される。
前記の如くリードの一部は低融点ガラスに埋設されてい
る。ところが、前記リードはコバール、４２７０イ等の
金属材料で形成されているため前記ガラスとの接着性は
必ずしも十分でなく、そのためパッケージの気密封止が
保てず半導体装置の信顧性に問題があることが本発明者
により見い出された。
なお、ガラス封止型半導体装置については、１９８０年
１月１５日、工業調査会発行、日本マイシロエレクトロ
ニクス協会編ｒＩｃ化実装技術」Ｐ１３５〜Ｐ１５０に
記載されている。
［発明の目的］ 本発明の目的は、ガラス封止型半導体装置のパッケージ
の気密封止強度を向上できる技術を提供することにある
。
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。
［発明の概要］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。
すなわち、ガラス封止型半導体装置について、少なくと
もガラス埋設部のリード表面に粗面部を形成することに
より、該リード部の表面積の拡大による接着力の増強お
よび粗面部とガラスとの機械的咬み合いの発生により、
パッケージの封止強度を向上させることができ、前記目
的が達成されるものである。
［実施例］ 第１図は、本発明による一実施例である半導体本実施例
の半導体装置は、いわゆるガラス封止型半導体装置であ
り、セラミックからなるパッケージ基板１にベレット２
を金−シリコン共晶３で取付けた後、該基板１の周囲上
面にリードフレーム（図示せず。）のり一部４を低融点
ガラス５で固定し、次いで該リード４の内端部とベレッ
ト２のポンディングパッドとをワイヤ６を介してボンデ
ィングした後、同じくセラミックからなるキャップ７を
前記基板１の周囲上面に低融点ガラス５ａで取付けるこ
とによりパッケージ内部を気密封止し、さらに外部リー
ドを切断、折り曲げしてなるものである。
本実施例の半導体装置においては、リード４のガラスに
よる埋設部より内側の上面の一部にアルミニウム層８が
被着されており、該リード４の表面はその内端部のアル
ミニウム層８を除き、例えば５〜１００μｍ程度の表面
粗さとされている。
ここで、アルミニウム層８の内端部を平坦にしであるの
は、ワイヤボンディングを行い易くするためである。
このように、封止材である低融点ガラスに埋設されるリ
ード４の表面を粗面化することにより、表面積を拡大で
きるため物理的、化学的接着力を向上できると同時に、
リード表面とガラスとの咬み合いによる効果も加わるた
め、大巾に該パッケージの封止強度を向上させることが
できるものである。
なお、本実施例の半導体装置に適用できるリードフレー
ムは、次のようにして容易に形成できる。
すなわち、所定部にアルミニウムをクラッドしたフレー
ム材料からなる薄板を用意し、これを表面が粗面形成さ
れているロールで処理することにより、表裏全体が粗面
化された薄板を形成する。その後、通常のプレス加工を
行って所定の形状に打ち抜き、リード内端部のアルミニ
ウム層８のみをコイニングすることにより、該アルミニ
ウム層８を平坦に形成することができる。
〔効果〕
＋１１．ガラス封止型半導体装置について、少なくとも
ガラス埋設部のリード表面に粗面部を形成することによ
り、該リード部の表面積の拡大による接着の強度および
埋設部のリードとガラスとの機械的咬み合いによるパッ
ケージの封止強度を向上させることができるので、該パ
ッケージの気密性を大巾に向上させることができる。
（２）、前記（１）により、半導体装置の信鯨性を大巾
に向上させることができる。
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。
たとえば、実施例ではパッケージの外側の外部リードの
表面も粗面で形成されたものを示したが、これに限るも
のでなく、ガラスに埋設されるリード部のみに粗面部が
形成されているものであってもよいことはいうまでもな
い。
また、粗面部の形成方法もロールで処理するものに限る
ものでなく、プレス加工等の他の方法によってもよいこ
とはいうまでもない。
〔利用分野〕
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である、いわゆるＤＩＰ型
の半導体装置に適用した場合について説明したが、それ
に限定されるものではなく、たとえば、ガラス封止型半
導体装置であればフラットパッケージ型等の種々の型式
の半導体装置に適用できる技術である。
【図面の簡単な説明】
第１図は、本発明による一実施例である半導体装置を示
す部分断面図である。 １・・・基板、２・・・ベレット、３・・・金−シリコ
ン共晶、４・・・リード、５，５ａ・・・低融点ガラス
、６・・・ワイヤ、７・・・キャップ、８・・・アルミ
ニウム層。

Claims (1)

  1. 【特許請求の範囲】 １、ガラス封止型半導体装置であって、リードの少なく
    とも埋設部に粗面部が形成されてなる半導体装置。 ２、粗面部の表面粗さが５〜１００μｍであることを特
    徴とする特許請求の範囲第１項記載の半導体装置。 ３、埋設部以内のリードの少なくとも一部にアルミニウ
    ム層が被着されていることを特徴とする特許請求の範囲
    第１項記載の半導体装置。 ４、アルミニウム層の表面は、少なくともその一部が平
    坦に形成されていることを特徴とする特許請求の範囲第
    ３項記載の半導体装置。
JP60082460A 1985-04-19 1985-04-19 半導体装置 Pending JPS61241952A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60082460A JPS61241952A (ja) 1985-04-19 1985-04-19 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60082460A JPS61241952A (ja) 1985-04-19 1985-04-19 半導体装置

Publications (1)

Publication Number Publication Date
JPS61241952A true JPS61241952A (ja) 1986-10-28

Family

ID=13775118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60082460A Pending JPS61241952A (ja) 1985-04-19 1985-04-19 半導体装置

Country Status (1)

Country Link
JP (1) JPS61241952A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01239875A (ja) * 1988-03-18 1989-09-25 Sumitomo Electric Ind Ltd 気密端子用リード線の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01239875A (ja) * 1988-03-18 1989-09-25 Sumitomo Electric Ind Ltd 気密端子用リード線の製造方法

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