JPS6123769U - Synchronous separation circuit - Google Patents

Synchronous separation circuit

Info

Publication number
JPS6123769U
JPS6123769U JP10916184U JP10916184U JPS6123769U JP S6123769 U JPS6123769 U JP S6123769U JP 10916184 U JP10916184 U JP 10916184U JP 10916184 U JP10916184 U JP 10916184U JP S6123769 U JPS6123769 U JP S6123769U
Authority
JP
Japan
Prior art keywords
synchronous separation
circuit
time constant
synchronous
separation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10916184U
Other languages
Japanese (ja)
Inventor
宏 吉田
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP10916184U priority Critical patent/JPS6123769U/en
Publication of JPS6123769U publication Critical patent/JPS6123769U/en
Pending legal-status Critical Current

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  • Synchronizing For Television (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本実施例回路の回路図、第2図は従来回路の回
路図、第3図は波形説明図。 T1・・・・・・同期分離駆動トランジスタ、1・・・
・・・時定数回路、T2・・・・・・同期分離トランジ
スタ、6・・・・・・積分回路、T4・・・・・・スイ
ッチングトランジスタ、T5・・・・・・放電トランジ
スタ。
FIG. 1 is a circuit diagram of the circuit of this embodiment, FIG. 2 is a circuit diagram of a conventional circuit, and FIG. 3 is a waveform explanatory diagram. T1... Synchronous separation drive transistor, 1...
... Time constant circuit, T2 ... Synchronous separation transistor, 6 ... Integrating circuit, T4 ... Switching transistor, T5 ... Discharging transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複合映像信号の印加される同期分離トランジスタの入力
電極に抵抗及びコンデンサよりなる時定数回路を接続し
てなり、前記時定数回路の時定数により前記同期分離ト
ランジスタの同期分離レベルが決定される同期分離回路
において、同期分離出力を積分する積分回路と、該積分
回路出力が所定値よりも小さいときのみ前記時定数回路
に接続される放電路とを備え、前記積分回路出力の太き
さに応じて前記同期分離レベルが変化することを特徴と
する同期分離回路。
A synchronous separation device in which a time constant circuit consisting of a resistor and a capacitor is connected to the input electrode of a synchronous separation transistor to which a composite video signal is applied, and the synchronous separation level of the synchronous separation transistor is determined by the time constant of the time constant circuit. The circuit includes an integrator circuit that integrates the synchronization separation output, and a discharge path that is connected to the time constant circuit only when the integrator circuit output is smaller than a predetermined value, and the integrator circuit A synchronous separation circuit characterized in that the synchronous separation level changes.
JP10916184U 1984-07-18 1984-07-18 Synchronous separation circuit Pending JPS6123769U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10916184U JPS6123769U (en) 1984-07-18 1984-07-18 Synchronous separation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10916184U JPS6123769U (en) 1984-07-18 1984-07-18 Synchronous separation circuit

Publications (1)

Publication Number Publication Date
JPS6123769U true JPS6123769U (en) 1986-02-12

Family

ID=30668321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10916184U Pending JPS6123769U (en) 1984-07-18 1984-07-18 Synchronous separation circuit

Country Status (1)

Country Link
JP (1) JPS6123769U (en)

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