JPS59111369U - television receiver - Google Patents

television receiver

Info

Publication number
JPS59111369U
JPS59111369U JP1983004911U JP491183U JPS59111369U JP S59111369 U JPS59111369 U JP S59111369U JP 1983004911 U JP1983004911 U JP 1983004911U JP 491183 U JP491183 U JP 491183U JP S59111369 U JPS59111369 U JP S59111369U
Authority
JP
Japan
Prior art keywords
television receiver
sync signal
integrator circuit
integrates
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983004911U
Other languages
Japanese (ja)
Other versions
JPH0139019Y2 (en
Inventor
尾家　唯史
Original Assignee
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電器産業株式会社 filed Critical 松下電器産業株式会社
Priority to JP1983004911U priority Critical patent/JPS59111369U/en
Publication of JPS59111369U publication Critical patent/JPS59111369U/en
Application granted granted Critical
Publication of JPH0139019Y2 publication Critical patent/JPH0139019Y2/ja
Granted legal-status Critical Current

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Landscapes

  • Television Receiver Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本著案の一実施例におけるテレビジョン受像機
め回路図、第２図はその動作説明のための波形図である
。 １・・・同期分離用トランジスタ、４・・・・・・制御
回路、４ａ、　　４ｂ・・・・・・積分回路を構成する
抵抗、コンデンサ、４Ｃ・・・・・・ツェナーダイオー
ド。FIG. 1 is a circuit diagram of a television receiver according to an embodiment of this invention, and FIG. 2 is a waveform diagram for explaining its operation. 1... Transistor for synchronization separation, 4... Control circuit, 4a, 4b... Resistor and capacitor constituting the integrating circuit, 4C... Zener diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同期分離用トランジスタの出力端に複合同期信号を積分
する積分回路を接続し、この積分回路の他端も、積分さ
れた垂直同期信号レベルよりツェナー電圧の高いツェナ
ーダイオードを介してブランキング回路の入力端に接続
したテレビジョン受像機。An integrator circuit that integrates the composite sync signal is connected to the output terminal of the sync isolation transistor, and the other end of this integrator circuit is also connected to the input of the blanking circuit via a Zener diode whose zener voltage is higher than the integrated vertical sync signal level. A television receiver connected to the end.
JP1983004911U 1983-01-17 1983-01-17 television receiver Granted JPS59111369U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983004911U JPS59111369U (en) 1983-01-17 1983-01-17 television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983004911U JPS59111369U (en) 1983-01-17 1983-01-17 television receiver

Publications (2)

Publication Number Publication Date
JPS59111369U true JPS59111369U (en) 1984-07-27
JPH0139019Y2 JPH0139019Y2 (en) 1989-11-21

Family

ID=30136513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983004911U Granted JPS59111369U (en) 1983-01-17 1983-01-17 television receiver

Country Status (1)

Country Link
JP (1) JPS59111369U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797280A (en) * 1980-12-09 1982-06-16 Matsushita Electric Ind Co Ltd Picture elimination circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797280A (en) * 1980-12-09 1982-06-16 Matsushita Electric Ind Co Ltd Picture elimination circuit

Also Published As

Publication number Publication date
JPH0139019Y2 (en) 1989-11-21

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