JPS61220339A - 半導体材料特性の制御方法 - Google Patents
半導体材料特性の制御方法Info
- Publication number
- JPS61220339A JPS61220339A JP6169385A JP6169385A JPS61220339A JP S61220339 A JPS61220339 A JP S61220339A JP 6169385 A JP6169385 A JP 6169385A JP 6169385 A JP6169385 A JP 6169385A JP S61220339 A JPS61220339 A JP S61220339A
- Authority
- JP
- Japan
- Prior art keywords
- donor
- defect
- substrate
- oxygen
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000000463 material Substances 0.000 title claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 27
- 239000001301 oxygen Substances 0.000 claims abstract description 27
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 26
- 230000007547 defect Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 238000009826 distribution Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 20
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 229960003903 oxygen Drugs 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000000370 acceptor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- -1 oxygen ions Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6169385A JPS61220339A (ja) | 1985-03-26 | 1985-03-26 | 半導体材料特性の制御方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6169385A JPS61220339A (ja) | 1985-03-26 | 1985-03-26 | 半導体材料特性の制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61220339A true JPS61220339A (ja) | 1986-09-30 |
| JPH0511415B2 JPH0511415B2 (enrdf_load_stackoverflow) | 1993-02-15 |
Family
ID=13178584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6169385A Granted JPS61220339A (ja) | 1985-03-26 | 1985-03-26 | 半導体材料特性の制御方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61220339A (enrdf_load_stackoverflow) |
Cited By (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6830964B1 (en) | 2003-06-26 | 2004-12-14 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US6833294B1 (en) | 2003-06-26 | 2004-12-21 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US6993222B2 (en) | 1999-03-03 | 2006-01-31 | Rj Mears, Llc | Optical filter device with aperiodically arranged grating elements |
| US7018900B2 (en) | 2003-06-26 | 2006-03-28 | Rj Mears, Llc | Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions |
| US7045377B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
| US7045813B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Semiconductor device including a superlattice with regions defining a semiconductor junction |
| US7123792B1 (en) | 1999-03-05 | 2006-10-17 | Rj Mears, Llc | Configurable aperiodic grating device |
| US7202494B2 (en) | 2003-06-26 | 2007-04-10 | Rj Mears, Llc | FINFET including a superlattice |
| US7227174B2 (en) | 2003-06-26 | 2007-06-05 | Rj Mears, Llc | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
| US7229902B2 (en) | 2003-06-26 | 2007-06-12 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction |
| US7396742B2 (en) | 2000-09-13 | 2008-07-08 | Hamamatsu Photonics K.K. | Laser processing method for cutting a wafer-like object by using a laser to form modified regions within the object |
| US7446002B2 (en) | 2003-06-26 | 2008-11-04 | Mears Technologies, Inc. | Method for making a semiconductor device comprising a superlattice dielectric interface layer |
| US7491587B2 (en) | 2003-06-26 | 2009-02-17 | Mears Technologies, Inc. | Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer |
| US7514328B2 (en) | 2003-06-26 | 2009-04-07 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween |
| US7517702B2 (en) | 2005-12-22 | 2009-04-14 | Mears Technologies, Inc. | Method for making an electronic device including a poled superlattice having a net electrical dipole moment |
| US7531850B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a memory cell with a negative differential resistance (NDR) device |
| US7531829B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
| US7531828B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions |
| US7535041B2 (en) | 2003-06-26 | 2009-05-19 | Mears Technologies, Inc. | Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
| US7566635B2 (en) | 2002-03-12 | 2009-07-28 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US7586165B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Microelectromechanical systems (MEMS) device including a superlattice |
| US7586116B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
| US7598515B2 (en) | 2003-06-26 | 2009-10-06 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice and overlying stress layer and related methods |
| US7612366B2 (en) | 2003-06-26 | 2009-11-03 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice layer above a stress layer |
| US7659539B2 (en) | 2003-06-26 | 2010-02-09 | Mears Technologies, Inc. | Semiconductor device including a floating gate memory cell with a superlattice channel |
| US7700447B2 (en) | 2006-02-21 | 2010-04-20 | Mears Technologies, Inc. | Method for making a semiconductor device comprising a lattice matching layer |
| US7781827B2 (en) | 2007-01-24 | 2010-08-24 | Mears Technologies, Inc. | Semiconductor device with a vertical MOSFET including a superlattice and related methods |
| US7812339B2 (en) | 2007-04-23 | 2010-10-12 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures |
| US7863066B2 (en) | 2007-02-16 | 2011-01-04 | Mears Technologies, Inc. | Method for making a multiple-wavelength opto-electronic device including a superlattice |
| US7880161B2 (en) | 2007-02-16 | 2011-02-01 | Mears Technologies, Inc. | Multiple-wavelength opto-electronic device including a superlattice |
| US7928425B2 (en) | 2007-01-25 | 2011-04-19 | Mears Technologies, Inc. | Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods |
| US8263479B2 (en) | 2002-12-03 | 2012-09-11 | Hamamatsu Photonics K.K. | Method for cutting semiconductor substrate |
| US8969752B2 (en) | 2003-03-12 | 2015-03-03 | Hamamatsu Photonics K.K. | Laser processing method |
| US9275996B2 (en) | 2013-11-22 | 2016-03-01 | Mears Technologies, Inc. | Vertical semiconductor devices including superlattice punch through stop layer and related methods |
| US9406753B2 (en) | 2013-11-22 | 2016-08-02 | Atomera Incorporated | Semiconductor devices including superlattice depletion layer stack and related methods |
| US9558939B1 (en) | 2016-01-15 | 2017-01-31 | Atomera Incorporated | Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source |
| US9716147B2 (en) | 2014-06-09 | 2017-07-25 | Atomera Incorporated | Semiconductor devices with enhanced deterministic doping and related methods |
| US9721790B2 (en) | 2015-06-02 | 2017-08-01 | Atomera Incorporated | Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control |
| US9722046B2 (en) | 2014-11-25 | 2017-08-01 | Atomera Incorporated | Semiconductor device including a superlattice and replacement metal gate structure and related methods |
| US9899479B2 (en) | 2015-05-15 | 2018-02-20 | Atomera Incorporated | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods |
| US10381242B2 (en) | 2017-05-16 | 2019-08-13 | Atomera Incorporated | Method for making a semiconductor device including a superlattice as a gettering layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5638828A (en) * | 1979-09-07 | 1981-04-14 | Sony Corp | Manufacture of semiconductor device |
| JPS5740939A (en) * | 1980-08-25 | 1982-03-06 | Fujitsu Ltd | P-n junction formation |
-
1985
- 1985-03-26 JP JP6169385A patent/JPS61220339A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5638828A (en) * | 1979-09-07 | 1981-04-14 | Sony Corp | Manufacture of semiconductor device |
| JPS5740939A (en) * | 1980-08-25 | 1982-03-06 | Fujitsu Ltd | P-n junction formation |
Cited By (92)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6993222B2 (en) | 1999-03-03 | 2006-01-31 | Rj Mears, Llc | Optical filter device with aperiodically arranged grating elements |
| US7123792B1 (en) | 1999-03-05 | 2006-10-17 | Rj Mears, Llc | Configurable aperiodic grating device |
| US8933369B2 (en) | 2000-09-13 | 2015-01-13 | Hamamatsu Photonics K.K. | Method of cutting a substrate and method of manufacturing a semiconductor device |
| US7547613B2 (en) | 2000-09-13 | 2009-06-16 | Hamamatsu Photonics K.K. | Laser processing method and laser processing apparatus |
| US7592238B2 (en) | 2000-09-13 | 2009-09-22 | Hamamatsu Photonics K.K. | Laser processing method and laser processing apparatus |
| US9837315B2 (en) | 2000-09-13 | 2017-12-05 | Hamamatsu Photonics K.K. | Laser processing method and laser processing apparatus |
| US7615721B2 (en) * | 2000-09-13 | 2009-11-10 | Hamamatsu Photonics K.K. | Laser processing method and laser processing apparatus |
| US7626137B2 (en) | 2000-09-13 | 2009-12-01 | Hamamatsu Photonics K.K. | Laser cutting by forming a modified region within an object and generating fractures |
| US10796959B2 (en) | 2000-09-13 | 2020-10-06 | Hamamatsu Photonics K.K. | Laser processing method and laser processing apparatus |
| US7396742B2 (en) | 2000-09-13 | 2008-07-08 | Hamamatsu Photonics K.K. | Laser processing method for cutting a wafer-like object by using a laser to form modified regions within the object |
| US8946589B2 (en) | 2000-09-13 | 2015-02-03 | Hamamatsu Photonics K.K. | Method of cutting a substrate, method of cutting a wafer-like object, and method of manufacturing a semiconductor device |
| US8927900B2 (en) | 2000-09-13 | 2015-01-06 | Hamamatsu Photonics K.K. | Method of cutting a substrate, method of processing a wafer-like object, and method of manufacturing a semiconductor device |
| US8946591B2 (en) | 2000-09-13 | 2015-02-03 | Hamamatsu Photonics K.K. | Method of manufacturing a semiconductor device formed using a substrate cutting method |
| US8937264B2 (en) | 2000-09-13 | 2015-01-20 | Hamamatsu Photonics K.K. | Laser processing method and laser processing apparatus |
| US8969761B2 (en) | 2000-09-13 | 2015-03-03 | Hamamatsu Photonics K.K. | Method of cutting a wafer-like object and semiconductor chip |
| US8946592B2 (en) | 2000-09-13 | 2015-02-03 | Hamamatsu Photonics K.K. | Laser processing method and laser processing apparatus |
| US9543207B2 (en) | 2002-03-12 | 2017-01-10 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US8889525B2 (en) | 2002-03-12 | 2014-11-18 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US11424162B2 (en) | 2002-03-12 | 2022-08-23 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US7566635B2 (en) | 2002-03-12 | 2009-07-28 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US9142458B2 (en) | 2002-03-12 | 2015-09-22 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US9287177B2 (en) | 2002-03-12 | 2016-03-15 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US9543256B2 (en) | 2002-03-12 | 2017-01-10 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US10622255B2 (en) | 2002-03-12 | 2020-04-14 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US10068801B2 (en) | 2002-03-12 | 2018-09-04 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US9548246B2 (en) | 2002-03-12 | 2017-01-17 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US9711405B2 (en) | 2002-03-12 | 2017-07-18 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US9553023B2 (en) | 2002-03-12 | 2017-01-24 | Hamamatsu Photonics K.K. | Substrate dividing method |
| US8263479B2 (en) | 2002-12-03 | 2012-09-11 | Hamamatsu Photonics K.K. | Method for cutting semiconductor substrate |
| US8865566B2 (en) | 2002-12-03 | 2014-10-21 | Hamamatsu Photonics K.K. | Method of cutting semiconductor substrate |
| US8969752B2 (en) | 2003-03-12 | 2015-03-03 | Hamamatsu Photonics K.K. | Laser processing method |
| US7288457B2 (en) | 2003-06-26 | 2007-10-30 | Rj Mears, Llc | Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions |
| US7229902B2 (en) | 2003-06-26 | 2007-06-12 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction |
| US6833294B1 (en) | 2003-06-26 | 2004-12-21 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US7531850B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a memory cell with a negative differential resistance (NDR) device |
| US7531829B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
| US7531828B2 (en) | 2003-06-26 | 2009-05-12 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions |
| US7535041B2 (en) | 2003-06-26 | 2009-05-19 | Mears Technologies, Inc. | Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
| US7491587B2 (en) | 2003-06-26 | 2009-02-17 | Mears Technologies, Inc. | Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer |
| US7446334B2 (en) | 2003-06-26 | 2008-11-04 | Mears Technologies, Inc. | Electronic device comprising active optical devices with an energy band engineered superlattice |
| US7586165B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Microelectromechanical systems (MEMS) device including a superlattice |
| US7586116B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
| US7446002B2 (en) | 2003-06-26 | 2008-11-04 | Mears Technologies, Inc. | Method for making a semiconductor device comprising a superlattice dielectric interface layer |
| US7598515B2 (en) | 2003-06-26 | 2009-10-06 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice and overlying stress layer and related methods |
| US7612366B2 (en) | 2003-06-26 | 2009-11-03 | Mears Technologies, Inc. | Semiconductor device including a strained superlattice layer above a stress layer |
| US7436026B2 (en) | 2003-06-26 | 2008-10-14 | Mears Technologies, Inc. | Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions |
| US7435988B2 (en) | 2003-06-26 | 2008-10-14 | Mears Technologies, Inc. | Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel |
| US7659539B2 (en) | 2003-06-26 | 2010-02-09 | Mears Technologies, Inc. | Semiconductor device including a floating gate memory cell with a superlattice channel |
| US6878576B1 (en) | 2003-06-26 | 2005-04-12 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US6891188B2 (en) | 2003-06-26 | 2005-05-10 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
| US6897472B2 (en) | 2003-06-26 | 2005-05-24 | Rj Mears, Llc | Semiconductor device including MOSFET having band-engineered superlattice |
| US6927413B2 (en) | 2003-06-26 | 2005-08-09 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
| US6952018B2 (en) | 2003-06-26 | 2005-10-04 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
| US6958486B2 (en) | 2003-06-26 | 2005-10-25 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
| US7018900B2 (en) | 2003-06-26 | 2006-03-28 | Rj Mears, Llc | Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions |
| US7432524B2 (en) | 2003-06-26 | 2008-10-07 | Mears Technologies, Inc. | Integrated circuit comprising an active optical device having an energy band engineered superlattice |
| US7034329B2 (en) | 2003-06-26 | 2006-04-25 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure |
| US7303948B2 (en) | 2003-06-26 | 2007-12-04 | Mears Technologies, Inc. | Semiconductor device including MOSFET having band-engineered superlattice |
| US6830964B1 (en) | 2003-06-26 | 2004-12-14 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US7279699B2 (en) | 2003-06-26 | 2007-10-09 | Rj Mears, Llc | Integrated circuit comprising a waveguide having an energy band engineered superlattice |
| US7279701B2 (en) | 2003-06-26 | 2007-10-09 | Rj Mears, Llc | Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions |
| US7265002B2 (en) | 2003-06-26 | 2007-09-04 | Rj Mears, Llc | Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel |
| US7514328B2 (en) | 2003-06-26 | 2009-04-07 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween |
| US7227174B2 (en) | 2003-06-26 | 2007-06-05 | Rj Mears, Llc | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
| US7202494B2 (en) | 2003-06-26 | 2007-04-10 | Rj Mears, Llc | FINFET including a superlattice |
| US7109052B2 (en) | 2003-06-26 | 2006-09-19 | Rj Mears, Llc | Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice |
| US7071119B2 (en) | 2003-06-26 | 2006-07-04 | Rj Mears, Llc | Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure |
| US7045813B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Semiconductor device including a superlattice with regions defining a semiconductor junction |
| US7033437B2 (en) | 2003-06-26 | 2006-04-25 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
| US7045377B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
| US7517702B2 (en) | 2005-12-22 | 2009-04-14 | Mears Technologies, Inc. | Method for making an electronic device including a poled superlattice having a net electrical dipole moment |
| US7718996B2 (en) | 2006-02-21 | 2010-05-18 | Mears Technologies, Inc. | Semiconductor device comprising a lattice matching layer |
| US7700447B2 (en) | 2006-02-21 | 2010-04-20 | Mears Technologies, Inc. | Method for making a semiconductor device comprising a lattice matching layer |
| US7781827B2 (en) | 2007-01-24 | 2010-08-24 | Mears Technologies, Inc. | Semiconductor device with a vertical MOSFET including a superlattice and related methods |
| US7928425B2 (en) | 2007-01-25 | 2011-04-19 | Mears Technologies, Inc. | Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods |
| US7880161B2 (en) | 2007-02-16 | 2011-02-01 | Mears Technologies, Inc. | Multiple-wavelength opto-electronic device including a superlattice |
| US7863066B2 (en) | 2007-02-16 | 2011-01-04 | Mears Technologies, Inc. | Method for making a multiple-wavelength opto-electronic device including a superlattice |
| US8389974B2 (en) | 2007-02-16 | 2013-03-05 | Mears Technologies, Inc. | Multiple-wavelength opto-electronic device including a superlattice |
| US7812339B2 (en) | 2007-04-23 | 2010-10-12 | Mears Technologies, Inc. | Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures |
| US9275996B2 (en) | 2013-11-22 | 2016-03-01 | Mears Technologies, Inc. | Vertical semiconductor devices including superlattice punch through stop layer and related methods |
| US9406753B2 (en) | 2013-11-22 | 2016-08-02 | Atomera Incorporated | Semiconductor devices including superlattice depletion layer stack and related methods |
| US9972685B2 (en) | 2013-11-22 | 2018-05-15 | Atomera Incorporated | Vertical semiconductor devices including superlattice punch through stop layer and related methods |
| US9716147B2 (en) | 2014-06-09 | 2017-07-25 | Atomera Incorporated | Semiconductor devices with enhanced deterministic doping and related methods |
| US10170560B2 (en) | 2014-06-09 | 2019-01-01 | Atomera Incorporated | Semiconductor devices with enhanced deterministic doping and related methods |
| US10084045B2 (en) | 2014-11-25 | 2018-09-25 | Atomera Incorporated | Semiconductor device including a superlattice and replacement metal gate structure and related methods |
| US9722046B2 (en) | 2014-11-25 | 2017-08-01 | Atomera Incorporated | Semiconductor device including a superlattice and replacement metal gate structure and related methods |
| US9941359B2 (en) | 2015-05-15 | 2018-04-10 | Atomera Incorporated | Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods |
| US9899479B2 (en) | 2015-05-15 | 2018-02-20 | Atomera Incorporated | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods |
| US9721790B2 (en) | 2015-06-02 | 2017-08-01 | Atomera Incorporated | Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control |
| US9558939B1 (en) | 2016-01-15 | 2017-01-31 | Atomera Incorporated | Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source |
| US10381242B2 (en) | 2017-05-16 | 2019-08-13 | Atomera Incorporated | Method for making a semiconductor device including a superlattice as a gettering layer |
| US10410880B2 (en) | 2017-05-16 | 2019-09-10 | Atomera Incorporated | Semiconductor device including a superlattice as a gettering layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0511415B2 (enrdf_load_stackoverflow) | 1993-02-15 |
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