JPS612193A - Contrast signal generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a gray scale signal generation circuit in a liquid crystal television receiver.

[Prior art and its problems] In recent years, liquid crystal television receivers (AM), which use a liquid crystal display panel in the display section, have been put into practical use as small portable television receivers. Furthermore, recently, liquid crystal color televisions using color liquid crystal panels have been considered. There are various methods for color liquid crystal display, but as shown in Fig. 4, primary color filters 1 of R (red), G (green), and B (blue) are arranged on signal electrodes to form a color liquid crystal panel 2. It is common to use a combination of the above three primary colors to perform color display. Further, in FIG. 4, reference numeral 3 denotes a scanning electrode drive circuit, and zero scanning signal lines are connected to the color liquid crystal panel 2. Furthermore, 4 is an R signal electrode drive circuit, 5 is a G signal electrode drive circuit, and 6 is a B signal electrode drive circuit, each of which has m signal lines connected to the color liquid crystal panel 2. In addition, 7 is a liquid crystal voltage generation circuit, ■o~V5, that is, V[l = G
ND, V1 = (1/a) Vs, V2 = (2/a
)Vs, V3-(1-2/a)Vs, V4-(1-
1/a) Generate L'rv5 and drive each of the above drive circuits 3.4.
5.8 is supplied as the operating voltage. Note that a above is a bias ratio.

Each signal electrode drive circuit 4.5.6 in FIG. 4 above is as follows:
It is constructed as shown in FIG. That is, each signal electrode drive circuit 4.5.6 has m stages of drive circuits 101 to 10m.
It consists of Then, the 4-bit digital data D1 sent from the video processing circuit (not shown) is transferred to D4.
is first input to the register 11 in the first stage drive circuit 101. This register 11 reads the data D1 to D4 in synchronization with the lean ring clock φB, and when input to the latch circuit 12, sends the data to the next stage drive circuit 102. The latch circuit iδ12 latches the chips written in the register 11 in synchronization with the latch pulse Φe,
Inverter 1? , , ...134 to the OR circuits 141-, 144, 1:ta, this OR circuit 14. 04 is input to the output Q1 of the counter 15 installed in the 91st section at 1"L. The counter 15 is reset by the pulse φβ). , C-run 1-up operation is performed by the reverse pulse φC.Then, the above 31 circuits 141
The outputs of 144 to 144 are input to the reset terminal R of the Noritsubu flop 17 via the circuit 16. This flip-flop 17 is activated by a latch pulse φg, and its output is sent to a multi-break relay 18. A frame switching signal φF is applied to the multiplexer 18, and the liquid crystal voltage generating circuit 7
A liquid crystal drive voltage of VO-V5 is applied from VO-V5. and,
The multiplexer 18 generates a signal electrode drive signal, that is, a gradation signal Y, in response to the output signal of the flip-flop 17.
Output l. In addition, the second and subsequent stage drive circuits 102 to
10m is also configured in the same manner as the drive circuit 101 described above, and outputs gradation signals Y2 to Ym.

In the above configuration, the digital data D1 to D4 sent from the video processing circuit is first transmitted to the first stage drive circuit 1.
01 and read into the register 11 in synchronization with the sampling clock φS. The data D1 to D4 read into the register 11 are then sequentially shifted to the register 11 by the drive circuit 102-10m in synchronization with the sampling clock φ9.

Then, when the data D1 to D4 are shifted to the register 11 of the drive circuit 10m, the latch pulse φ
Give 1 to a. As shown in FIG. 6, one latch pulse φρ is output every time n1 pulses of the sampling clock φ5 are output, and each latch pulse φρ is outputted to each drive circuit 10. ...10m, the data held in the register 11 is latched into the latch circuit 12. Further, on the same plane, the counter 15 is reset by the latch pulse φg, and the flip-flop 17 is set as shown in FIG. By setting this flip-flop 17, the output Y1 of the multiplexer 18 rises from the reference level of VB to the level of V5. In this case, in the next frame, when the flip-flop 11 goes to the cell 1, the output Yi of the multi-break ( ) 18 changes from the reference level of V2 to VO.
fall to the level. After being reset by the wrap pulse φg, the counter 15 starts counting by the clock pulse φC. Fourteen clock pulses φC are generated between each latch pulse φβ as shown in FIG. Then, along with the signal outputted from the wrap circuit 12 via the inverters 131 to 134, it is input to the OR circuits 141 to 144, and the output thereof is input to the AND circuit 1G. is input to.

Therefore, when the outputs of the OR circuits 141 to 144 become all ``1'' due to the counting operation of the counter 15, the output of the AND circuit 1G becomes ``1'', and the flip-flop 17 is reset. The count value of the counter 15 at which the outputs of 144 to 144 are all 1° is determined by the latch data of the latch circuit 12, and thereby controls the interval from when the flip-flop 17 is set until it is reset. When the flip-flop 17 is reset, the output of the multiplexer 18 returns to the reference level.Thereafter, the latch pulse φ° C. is reset, and the above operation is repeated. A signal Y1 is outputted from the multi-branch 18 in accordance with the data held by the latch circuit 12, and each signal electrode in the color liquid crystal panel 2 is driven for display.

Figure 7 shows an example of the waveform of the display drive signal, (a)
is the device electrode drive signal X+ constituted by the scan electrode drive circuit 3, (b> is the gray scale signal Y1 output from the multiplexer 18 of the signal electrode drive circuit 10, and (C) is the gray scale signal Y1 output from the multiplexer 18 of the signal electrode drive circuit 10. This is a composite waveform of the key signal Yi.

As described above, in the conventional signal electrode drive circuit 10, a fixed output waveform is obtained depending on the input data.
, B differ from the designed value, the hue will differ. That is, the above filter has R, G, B
Since the filter is formed three times for each color, it is extremely difficult to form the filter uniformly, resulting in variations in the filter film thickness.

If there is a difference in filter film thickness, even if the same voltage is applied to the electrodes, there will be a difference in the effective value applied to the liquid crystal, resulting in deterioration of display quality.

[Object of the Invention] The present invention has been made in view of the above points, and includes RlG, B
It is an object of the present invention to provide a gradation signal generation circuit that can correctly display a desired color and maintain good display quality even when the filter film thickness is different from a set value.

"Key Points of Light" The present invention provides an O
This allows initial adjustment of the N waveform and OFF waveform.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 20 is a signal electrode drive circuit, which is composed of m stages of drive circuits 201 to 20m. These drive circuits 2
0. ~20m is the drive circuit 101~10yyL in FIG.
The output of the flip-flop 17 is connected to the AND circuit 21
The other components are the same as those of the drive circuits 10 to 10m shown in FIG. 5, so the same reference numerals as in FIG. 5 are given, and detailed explanation will be omitted. Further, the counter 15 performs a count-up operation based on the clock pulse φc1, and this clock pulse φc1 is the same clock pulse as the clock pulse φC in FIG. Therefore, the AND circuit 21 is
The gate is controlled by a signal applied from a flip-flop 22 provided outside the signal electrode drive circuit 20. This flip-flop 22 receives a clock pulse φc1
The latch pulse φC is outputted via the OR circuit 23 by the tarlock pulse φCβ. Also, the clock pulse φc output from the OR circuit 23
J2 is input to the terminal R of the 3-hit counter 24. This counter 24 is counted up 4' by the clock pulse φc2, and its output Q1
．． Q2 and Q3 are input to the AND circuit 26 via OR circuits 25a-25c)1. The above []tsuku pulse φc2 is outputted from C109 in each period of the Nikon pulse φca as shown in FIG.
Initial setting data △1, A2, A3 or inverter 26a~
- Input via 2Gc. The above-mentioned initial nr+yra constant data 1, A2, and A3 are correction data for correcting changes in hue due to errors in forming the filter film thickness. Then, to the OR circuit 25a.

The output of 25c is input to terminal R of reset 1 of flip-flop 22 via ant circuit 27.

Next, the operation of the above-mentioned actual eggplant example will be explained. The digital data D1 to D4 sent from the video processing circuit are first
The signal is input to the first-stage drive circuit 201 and read into the register 11 in synchronization with the sampling clock φS. The data D1'' and D4 read into this register 11 are then
The drive circuit 202 is synchronized with the sampling clock φS.
~20m of registers 11 are sequentially shifted. and,
The above data D1 to D4 are stored in the register 11 of the drive circuit 20m.
After that, the latch pulse ψ2 is applied.

This latch pulse φ°C is outputted once every m times the sampling clock φ6 is outputted, as shown in FIG.
Each drive circuit 20. ~20m, the data held in the register 11 is latched into the latch circuit 12. At the same time, the counter 15 is reset 5 by the latch pulse φ° C., and the control flop 17 is set. The output of this flip-flop 17 is
The signal Y1 is sent to the multiplexer 18 via the circuit 21, and the multiplexer 18 outputs the gradation signal Y1 to drive the No. II lightning pole of the display panel for display. On the other hand, the counter 15 is reset 1 to 1 by the latch pulse φ.
After that, the counter I~ operation is started by the clock pulse φc1. Fourteen clock pulses φC1 are generated between each latch pulse φ2 as shown in FIG.

The count outputs 01 to 4 of the counter 15 are as follows:
Together with the signals output from the latch circuit 12 via the inverters 131 to 134, the signals are input to the OR circuits 14x to 144, and the output thereof is input to the AND circuit 16.

Therefore, as the counter 15 performs the counter l- operation, the OR circuit 14. When the outputs of 144 to 144 become all "1'°, the output of the AND circuit 16 becomes 1'°, and the flip-flop 17 is reset. The OR circuit 141-14
The values from 1 to 1 of the counter 15 at which the outputs of 4 are all ``1'' are determined by the latch data of the latch circuit 12, so that from the time knob 70 to knob 17 is sent to cellar 1 until it is reset. time is controlled. For example, when data "8" is latched in the latch circuit 12, the output of the AND circuit 16 becomes "1" when the counter 15 counts eight clock pulses φc1 as shown in FIG. 17 is reset 1
~ will be done. Thereafter, the above-described operation is repeated by applying the latch pulse φ°C. That is,
As shown in FIG.
and the reset period tR is determined. Then, the output of the flip-flop 17 is sent to the multiplexer 18 via the ant circuit 21, and at this time, the effective value is controlled by the initial setting data At, A2, and A3. Now, set the initial setting data At, A2, A3 to M
Based on the data set in Olj, the setting data is inverted to data in roloJ by inverters 26a to 26G, and then sent to AND circuit 2 via OR circuits 25a to 25c.
7 is input.

First, when the latch pulse φ° C. is applied, the flip 70 knob 22 is set by the output of the OR circuit 23, and the counter 24 is reset. By setting the flip-flop 70 knob 22, the gate of the AND circuit 21 is opened, and the output of the flip-flop 17 is sent to the multiplexer 18.
Counting operation is started by C2. Then, when the counter 24 reaches "5" and goes up from power run 1, the outputs Q1 to Q3 become "101" and the initial setting data AI
, A2, A3 which OR output, that is, OR circuit 2
The output points of 5a to 25c become A-1°. Therefore, the output of the AND circuit 27 becomes 1°, and the flip 7
0 knob 22 is reset. Therefore, the gate of the AND circuit 21 is closed, and input to the multiplexer 18 is prohibited. Thereafter, the flip-flop 22 is set by the clock pulse φcQ output from the OR circuit 23, and the gate i- of the AND circuit 21 is interrupted, causing the flip-flop 1
The output of 7 is now sent to multiplexer 18.

As described above, the set period j of the flip-flop 22
, ,I and the reset period tR' are the initial setting data AI
, A2, and A3.

One step below, while flip-flop 17 is set,
Similar operations are repeated to control the effective value of data sent from flip-flop 17 to multiplexer 18. The multiplexer 18 generates a gradation signal Y+ according to data sent from the flip-flop 11 via the AND circuit 21, and drives the signal electrodes of the display panel for display.

Figure 3 shows an example of the waveform of the display drive signal, (a)
is the scan electrode drive signal X output from the scan electrode drive circuit
i, (b) is the multiplexer 1 of the signal electrode drive circuit 20
The gradation signal Yt, (C) output from 8 is a composite waveform of the scanning electrode drive signal x1 and the gradation signal Y1.

As described above, the gradation signal Y1 can be adjusted to multiple levels at each gradation using the initial setting data A1, A2, and A3. Initial setting j-ta A even if different
1. By adjusting A2 and A3, the hue can be set correctly.

[Effects of the Invention] As detailed above, according to the present invention, in the drive circuit of a color liquid crystal panel, it is possible to initially adjust the ON waveform and OFF waveform for each gradation of the gradation waveform obtained from the drive circuit of each color. Therefore, R,,G on the color LCD panel
, even if the film thickness of the B filter is formed different from the set value, it is possible to provide a gradation signal generation circuit that can correctly display a desired color and maintain good display quality.

[Brief explanation of drawings]

Since FIGS. 1 to 3 do not show one embodiment of the present invention,
Fig. 1 is a circuit configuration diagram, Fig. 2 is a timing chart 1 to 1 for explaining the operation, Fig. 3 is a waveform diagram of display drive No. 19, and Fig. 1 is a diagram of a conventional liquid crystal display device. (1 showing the configuration
Fig. 5 is a diagram showing the configuration of the signal electrode 1Φ drive circuit shown in Fig. 4, and Fig. 6 is a diagram for explaining the operation of the signal electrode drive circuit shown in Fig. 5. Timing chart,
FIG. 7 is a waveform diagram of a conventional display drive signal. 11...Register, 12...Latch circuit, 15...
・Counter, 17...Flip 70 knob, 18...
Multiplexer, 20... Ie No. tΦ drive circuit, 2
4...Counter. Figure 1 Figure 4 Figure 5

Claims (1)

[Claims] In a signal electrode drive circuit for driving signal electrodes provided for each primary color on a color liquid crystal panel, there is a gradation signal generation means for generating gradation signals according to display data, and a gradation signal generation means for generating gradation signals according to display data. Initial setting data input means for specifying ON time and OFF time for each gradation of the tone signal;
A gradation signal generation circuit comprising: means for controlling ON time and OFF time of each gradation signal output from the gradation signal generation means based on initial setting data inputted by the means.