JPS61199166A - Device for retrieving wiring path - Google Patents
Device for retrieving wiring pathInfo
- Publication number
- JPS61199166A JPS61199166A JP60038835A JP3883585A JPS61199166A JP S61199166 A JPS61199166 A JP S61199166A JP 60038835 A JP60038835 A JP 60038835A JP 3883585 A JP3883585 A JP 3883585A JP S61199166 A JPS61199166 A JP S61199166A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- obstacle
- section
- pattern
- map
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント配線板および集積回路等の配線設計に
用いられる配線経路探索装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring route searching device used for wiring design of printed wiring boards, integrated circuits, etc.
従来、この種の配線経路探索装置は、線分の禁止に関し
て線分の方向を考慮するという概念はなく、線分を禁止
する障害物が設定された個所では、あらゆる方向の線分
が禁止されていた。従来例に関する文献としては[論理
装置のCADJ (オーム社、樹下行三、 56.0
3.20発行)がある。Conventionally, this type of wiring route search device has no concept of considering the direction of line segments when prohibiting line segments, and lines in any direction are prohibited at a location where an obstacle that prohibits line segments is set. was. Documents related to conventional examples include [Logic Device CADJ (Ohmsha, Yukizo Kishita, 56.0
3.20 issue).
上述した従来の配線経路探索装置は、特定の方向の線分
だけを禁止するような障害物を設定して特定方向の配線
格子数を部分的に調整することができないので、配線パ
ターンの密度が領域によって異なるような基板やビンの
最小間隔が他と異なる部品を搭載する基板への適用が困
難であった。The conventional wiring route search device described above cannot partially adjust the number of wiring grids in a specific direction by setting obstacles that prohibit only line segments in a specific direction, so the density of the wiring pattern is It has been difficult to apply this method to boards on which parts are mounted, such as boards that vary depending on the area, or where the minimum distance between bins differs from other parts.
C問題点を解決するための手段〕
このような問題点を解決するために本発明は、配線経路
を構成する線分のうち特定方向の線分のみを禁止するよ
うな障害物を認識する認識手段を設けるようにしたもの
である。Means for Solving Problem C] In order to solve such problems, the present invention provides recognition for recognizing obstacles that prohibit only line segments in a specific direction from among the line segments that make up the wiring route. This means that there is a means to do so.
本発明においては、認識手段は各方向の線分に関するデ
ータを取り込み特定方向の線分が禁止されているかどう
かを判定する。In the present invention, the recognition means takes in data regarding line segments in each direction and determines whether line segments in a particular direction are prohibited.
本発明に係わる配線経路探索装置の一実施例を第1図に
示す。第1図において、1は本装置全体を制御する配線
制御部、2は障害データbを取り込むための障害設定部
、3はメモリを有するグリッド・マツプ、4は認識手段
としての経路探索部、5は配線制御部1.経路探索部4
間の信号の授受を行なわせるためのインタフェース・テ
ーブルであり、実線で記載した矢印はデータの流れ、破
線で記載した矢印は制御の流れを示す。An embodiment of a wiring route searching device according to the present invention is shown in FIG. In FIG. 1, 1 is a wiring control unit that controls the entire device, 2 is a fault setting unit for importing fault data b, 3 is a grid map having a memory, 4 is a route search unit as a recognition means, and 5 is the wiring control section 1. Route search section 4
This is an interface table for exchanging signals between the two, where arrows drawn with solid lines indicate the flow of data, and arrows drawn with broken lines indicate the flow of control.
配線制御部1は、まず、配線格子の占有状態を記憶する
グリッド・マツプ3を初期化後、障害設定部2を起動し
て障害データbを取り込み、この障害データbをグリッ
ド・マツプ3にセットする。The wiring control unit 1 first initializes the grid map 3 that stores the occupation state of the wiring grid, then activates the fault setting unit 2 to take in fault data b, and sets this fault data b in the grid map 3. do.
障害データbは、水平、垂直または斜め方向の線分の配
線が禁止されているか否かを示すデータ(以下「3方向
データ」という)であり、格子点の位置に対応したグリ
ッド・マツプ3のメモリ上の領域に格納される。本装置
は3方向データによりいずれの方向の線分が配線に使用
できるかを判断する0次に配線制御部1は接続データa
の中から順次1配線区間分のピンペアを取り出してイン
クフェース・テーブル5にセントし、経路探索部4に起
動をかける。Obstacle data b is data indicating whether wiring of line segments in horizontal, vertical, or diagonal directions is prohibited (hereinafter referred to as "three-way data"), and is data that indicates whether wiring of line segments in horizontal, vertical, or diagonal directions is prohibited. Stored in an area in memory. This device uses three-way data to determine which direction of line segment can be used for wiring. Next, the wiring control unit 1 uses connection data a
Pin pairs corresponding to one wiring section are sequentially taken out from among them and placed in the ink face table 5, and the route search section 4 is activated.
経路探索部4は、配線制御部1からインタフェース・テ
ーブル5を介して与えられたピンペアに対し、グリッド
・マツプ3を参照し、特に線分の禁止に関する障害物に
対しては、この障害物が禁止する線分の方向を識別しな
がら配線経路を探索する。ピンペアの経路を発見した時
、経路探索部4は、発見した経路をインタフェース・テ
ーブル5にセットし、配線制御部1に移送する。また、
経路を発見できなかった時には、配線制御部1に対して
その旨を通知する。The route search unit 4 refers to the grid map 3 for the pin pair given from the wiring control unit 1 via the interface table 5, and in particular, for obstacles related to prohibition of line segments, this obstacle is detected. A wiring route is searched while identifying the direction of a prohibited line segment. When a route for a pin pair is discovered, the route search unit 4 sets the discovered route in the interface table 5 and transfers it to the wiring control unit 1. Also,
When the route cannot be found, the wiring control unit 1 is notified of this fact.
配線制御部1では、配線経路がインタフェース・テーブ
ル5を介して送られてきた場合、後に選択がされないよ
うにその経路を新たな障害物としてグリッド・マツプ3
にセットするとともに、外部媒体に出力する。以上のよ
うな操作をすべての配線区間に対して繰り返し、処理を
終了する。In the wiring control unit 1, when a wiring route is sent via the interface table 5, the route is added to the grid map 3 as a new obstacle to prevent it from being selected later.
and output to external media. The above operations are repeated for all wiring sections, and the process ends.
次に配線格子の調整について第2図、第3図を用いて説
明する。第2図は、最小ピン間隔の異なる部品が基板上
に搭載された時、すべてのピン8が格子に乗るように設
定された配線格子の一実施例である。線分A−Bを境界
として左側の領域はピン間に配線パターンを3本、右側
の領域では2零通過させることができる。しかし第3図
に示す線分A−Bを境界とした左側の領域のようにピン
のランド径が大きいためにピン間を通過できる配線パタ
ーンの本数を2本に制限するような条件がついた場合で
も、第2図に示すような水平線分禁止障害6と垂直線分
禁止障害7を設定することにより、領域によって配線パ
ターンの密度が異なる基板の設計も容易に行なうことが
できる。Next, adjustment of the wiring grid will be explained using FIGS. 2 and 3. FIG. 2 shows an example of a wiring grid in which all pins 8 are set on the grid when components with different minimum pin spacings are mounted on the board. With line segment A-B as the boundary, three wiring patterns can be passed between the pins in the area on the left, and two wiring patterns can be passed between the pins in the area on the right. However, as shown in the area on the left with the line segment A-B as the boundary shown in Figure 3, the land diameter of the pins is large, so there is a condition that limits the number of wiring patterns that can pass between the pins to two. Even in this case, by setting the horizontal line segment prohibition disorder 6 and the vertical line segment prohibition disorder 7 as shown in FIG. 2, it is possible to easily design a board in which the wiring pattern density varies depending on the area.
さらに第4図に示すような垂直線分禁止障害7を設定す
ることにより、第5図に示すような水平方向と垂直方向
の配線パターンの密度が異なるような基板の設計にも適
用できる。Further, by setting the vertical line segment prohibition obstacle 7 as shown in FIG. 4, the present invention can be applied to the design of a board in which the density of wiring patterns in the horizontal direction and the vertical direction are different as shown in FIG. 5.
以上説明したように本発明は、配線経路を構成する線分
のうち特定方向の線分のみを禁止するような障害物を認
識する認識手段を設けることにより、配線できる方向を
発見できるようにしたので、配線パターンの密度が異な
る基板の配線設計を容易にできるという効果がある。As explained above, the present invention makes it possible to discover the direction in which wiring can be done by providing recognition means for recognizing obstacles that prohibit only line segments in a specific direction from among the line segments that make up the wiring route. Therefore, there is an effect that it is possible to easily design wiring for boards having different wiring pattern densities.
第1図は本発明に係わる配線経路探索装置の一実施例を
示す系統図、第2図〜第5図は本装置による配線パター
ンの作成方法を説明するための格子パターン図である。
1・・・・配線制御部、2・・・・障害設定部、3・・
・・グリッド・マツプ、4・・・・経路探索部、・5・
・・・インタフェース・テーブル、6・・・・水平線分
禁止障害、7・・・・垂直線分禁止障害、8・・・・ピ
ン。FIG. 1 is a system diagram showing one embodiment of a wiring route searching device according to the present invention, and FIGS. 2 to 5 are lattice pattern diagrams for explaining a method of creating a wiring pattern using this device. 1... Wiring control section, 2... Fault setting section, 3...
・・Grid map, 4・・Route search section, ・5・
...Interface table, 6...Horizontal line segment prohibition failure, 7...Vertical line segment prohibition failure, 8...Pin.
Claims (1)
ンペアの配線経路の探索を行なう配線経路探索装置にお
いて、配線経路を構成する線分のうち特定方向の線分の
みを禁止するような障害物を認識する認識手段を備えた
ことを特徴とする配線経路探索装置。In a wiring route search device that searches for a wiring route for a pin pair that requires connection based on a wiring grid set on a board, obstacles that prohibit only line segments in a specific direction from among the line segments that make up the wiring route A wiring route search device characterized by comprising recognition means for recognizing.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60038835A JPS61199166A (en) | 1985-03-01 | 1985-03-01 | Device for retrieving wiring path |
US06/835,238 US4752887A (en) | 1985-03-01 | 1986-03-03 | Routing method for use in wiring design |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60038835A JPS61199166A (en) | 1985-03-01 | 1985-03-01 | Device for retrieving wiring path |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61199166A true JPS61199166A (en) | 1986-09-03 |
JPH0481226B2 JPH0481226B2 (en) | 1992-12-22 |
Family
ID=12536271
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60038835A Granted JPS61199166A (en) | 1985-03-01 | 1985-03-01 | Device for retrieving wiring path |
Country Status (2)
Country | Link |
---|---|
US (1) | US4752887A (en) |
JP (1) | JPS61199166A (en) |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62159278A (en) * | 1986-01-08 | 1987-07-15 | Hitachi Ltd | Automatic logical designing system |
US5034899A (en) * | 1986-07-07 | 1991-07-23 | Bbc Brown Boveri Ag | Software tool for automatically generating a functional-diagram graphic |
JPS63225869A (en) * | 1986-10-09 | 1988-09-20 | Nec Corp | Wiring path search system |
US5021968A (en) * | 1987-01-13 | 1991-06-04 | Robertson-Ceco Corporation | Graphics-based wire-cable management system |
US5119317A (en) * | 1988-03-16 | 1992-06-02 | Kabushiki Kaisha Toshiba | Routing method and system |
US4831725A (en) * | 1988-06-10 | 1989-05-23 | International Business Machines Corporation | Global wiring by removal of redundant paths |
JPH0786883B2 (en) * | 1988-09-09 | 1995-09-20 | 松下電器産業株式会社 | Method and system for automatically generating mesh diagram or logical circuit diagram |
US5452231A (en) * | 1988-10-05 | 1995-09-19 | Quickturn Design Systems, Inc. | Hierarchically connected reconfigurable logic assembly |
US5109353A (en) | 1988-12-02 | 1992-04-28 | Quickturn Systems, Incorporated | Apparatus for emulation of electronic hardware system |
US5329470A (en) * | 1988-12-02 | 1994-07-12 | Quickturn Systems, Inc. | Reconfigurable hardware emulation system |
JP2680867B2 (en) * | 1988-12-05 | 1997-11-19 | 株式会社日立製作所 | Path layout method |
US5224057A (en) * | 1989-02-28 | 1993-06-29 | Kabushiki Kaisha Toshiba | Arrangement method for logic cells in semiconductor IC device |
JPH02236779A (en) * | 1989-03-10 | 1990-09-19 | Nec Corp | Scan path connecting system |
US5317796A (en) * | 1989-04-18 | 1994-06-07 | Hunter Robert M | Technique for rendering packaging child resistant |
US5353243A (en) * | 1989-05-31 | 1994-10-04 | Synopsys Inc. | Hardware modeling system and method of use |
US5369593A (en) * | 1989-05-31 | 1994-11-29 | Synopsys Inc. | System for and method of connecting a hardware modeling element to a hardware modeling system |
US5309372A (en) * | 1989-07-17 | 1994-05-03 | Kawasaki Steel Corp. | System and method for determining routes between circuit blocks of a programmable logic device by determining a load pin which is closest to the center of gravity of a plurality of load pins |
JPH03138961A (en) * | 1989-10-24 | 1991-06-13 | Fujitsu Ltd | Wiring pattern deciding method |
JP2522420B2 (en) * | 1989-11-28 | 1996-08-07 | 日本電気株式会社 | Automatic wiring design device |
JPH03188650A (en) * | 1989-12-18 | 1991-08-16 | Hitachi Ltd | Routing method, routing system and semiconductor integrated circuit |
US5258920A (en) * | 1989-12-26 | 1993-11-02 | General Electric Company | Locally orientation specific routing system |
US5218551A (en) * | 1990-04-30 | 1993-06-08 | International Business Machines Corporation | Timing driven placement |
JPH0456341A (en) * | 1990-06-26 | 1992-02-24 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit layout method |
JP3033203B2 (en) * | 1991-01-25 | 2000-04-17 | 株式会社日立製作所 | Wiring route searching device and wiring route searching method |
US5315534A (en) * | 1991-06-25 | 1994-05-24 | Unisys Corporation | Computer process for interconnecting logic circuits utilizing softwire statements |
US5341310A (en) * | 1991-12-17 | 1994-08-23 | International Business Machines Corporation | Wiring layout design method and system for integrated circuits |
JP3219500B2 (en) * | 1991-12-27 | 2001-10-15 | 株式会社東芝 | Automatic wiring method |
US5475830A (en) * | 1992-01-31 | 1995-12-12 | Quickturn Design Systems, Inc. | Structure and method for providing a reconfigurable emulation circuit without hold time violations |
US5629859A (en) * | 1992-10-21 | 1997-05-13 | Texas Instruments Incorporated | Method for timing-directed circuit optimizations |
US5544088A (en) * | 1993-06-23 | 1996-08-06 | International Business Machines Corporation | Method of I/O pin assignment in a hierarchial packaging system |
JP3194823B2 (en) * | 1993-09-17 | 2001-08-06 | 富士通株式会社 | CAD library model creation device |
US5680583A (en) * | 1994-02-16 | 1997-10-21 | Arkos Design, Inc. | Method and apparatus for a trace buffer in an emulation system |
US5638288A (en) * | 1994-08-24 | 1997-06-10 | Lsi Logic Corporation | Separable cells having wiring channels for routing signals between surrounding cells |
US5587923A (en) * | 1994-09-07 | 1996-12-24 | Lsi Logic Corporation | Method for estimating routability and congestion in a cell placement for integrated circuit chip |
IL117424A (en) * | 1995-04-27 | 1999-09-22 | Optimark Tech Inc | Crossing network utilizing satisfaction density profile |
US5754826A (en) * | 1995-08-04 | 1998-05-19 | Synopsys, Inc. | CAD and simulation system for targeting IC designs to multiple fabrication processes |
US6353918B1 (en) | 1996-03-15 | 2002-03-05 | The Arizona Board Of Regents On Behalf Of The University Of Arizona | Interconnection routing system |
US5841967A (en) * | 1996-10-17 | 1998-11-24 | Quickturn Design Systems, Inc. | Method and apparatus for design verification using emulation and simulation |
US6009256A (en) * | 1997-05-02 | 1999-12-28 | Axis Systems, Inc. | Simulation/emulation system and method |
US6134516A (en) * | 1997-05-02 | 2000-10-17 | Axis Systems, Inc. | Simulation server system and method |
US6421251B1 (en) | 1997-05-02 | 2002-07-16 | Axis Systems Inc | Array board interconnect system and method |
US6321366B1 (en) | 1997-05-02 | 2001-11-20 | Axis Systems, Inc. | Timing-insensitive glitch-free logic system and method |
US6389379B1 (en) | 1997-05-02 | 2002-05-14 | Axis Systems, Inc. | Converification system and method |
US6026230A (en) * | 1997-05-02 | 2000-02-15 | Axis Systems, Inc. | Memory simulation system and method |
US5960191A (en) | 1997-05-30 | 1999-09-28 | Quickturn Design Systems, Inc. | Emulation system with time-multiplexed interconnect |
US5970240A (en) * | 1997-06-25 | 1999-10-19 | Quickturn Design Systems, Inc. | Method and apparatus for configurable memory emulation |
US6266802B1 (en) * | 1997-10-27 | 2001-07-24 | International Business Machines Corporation | Detailed grid point layout using a massively parallel logic including an emulator/simulator paradigm |
JP2001125943A (en) * | 1999-10-28 | 2001-05-11 | Nec Corp | Method for designing power supply decoupling circuit and design aiding system |
JP3389196B2 (en) * | 2000-04-17 | 2003-03-24 | エヌイーシーマイクロシステム株式会社 | Method of dividing functional block terminal, recording medium recording this method, and automatic wiring processing apparatus by this method |
US6536027B1 (en) * | 2000-12-13 | 2003-03-18 | Lsi Logic Corporation | Cell pin extensions for integrated circuits |
US6694502B2 (en) * | 2001-11-02 | 2004-02-17 | Sun Microsystems, Inc. | Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium |
US20040044979A1 (en) | 2002-08-27 | 2004-03-04 | Aji Sandeep A. | Constraint-based global router for routing high performance designs |
US6986112B2 (en) * | 2003-07-28 | 2006-01-10 | Lsi Logic Corporation | Method of mapping logic failures in an integrated circuit die |
JP4311244B2 (en) * | 2004-03-19 | 2009-08-12 | 株式会社日立製作所 | Wiring route determination method and system |
US7962232B2 (en) * | 2006-10-01 | 2011-06-14 | Dell Products L.P. | Methods and media for processing a circuit board |
US8356267B2 (en) | 2010-10-27 | 2013-01-15 | International Business Machines Corporation | Statistical method for hierarchically routing layout utilizing flat route information |
CN104063558A (en) * | 2014-07-08 | 2014-09-24 | 领佰思自动化科技(上海)有限公司 | Large scale integrated circuit path wiring method based on linear programming |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3944719A (en) * | 1972-12-26 | 1976-03-16 | United Wiring And Manufacturing Co. | Wire routing apparatus |
US4484292A (en) * | 1981-06-12 | 1984-11-20 | International Business Machines Corporation | High speed machine for the physical design of very large scale integrated circuits |
US4593351A (en) * | 1981-06-12 | 1986-06-03 | International Business Machines Corporation | High speed machine for the physical design of very large scale integrated circuits |
JPS59189471A (en) * | 1983-04-13 | 1984-10-27 | Nec Corp | Wiring route searching system |
JPS608982A (en) * | 1983-06-29 | 1985-01-17 | Yokogawa Hokushin Electric Corp | Automatic searching method of path |
US4615011A (en) * | 1983-12-19 | 1986-09-30 | Ibm | Iterative method for establishing connections and resulting product |
US4636965A (en) * | 1984-05-10 | 1987-01-13 | Rca Corporation | Routing method in computer-aided-customization of universal arrays and resulting integrated circuit |
-
1985
- 1985-03-01 JP JP60038835A patent/JPS61199166A/en active Granted
-
1986
- 1986-03-03 US US06/835,238 patent/US4752887A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4752887A (en) | 1988-06-21 |
JPH0481226B2 (en) | 1992-12-22 |
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