US6986112B2 - Method of mapping logic failures in an integrated circuit die - Google Patents
Method of mapping logic failures in an integrated circuit die Download PDFInfo
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- US6986112B2 US6986112B2 US10/628,986 US62898603A US6986112B2 US 6986112 B2 US6986112 B2 US 6986112B2 US 62898603 A US62898603 A US 62898603A US 6986112 B2 US6986112 B2 US 6986112B2
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- grid
- test paths
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31935—Storing data, e.g. failure memory
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- the present invention relates generally to the testing of integrated circuit dies. More specifically, but without limitation thereto, the present invention relates to mapping logic failures on an integrated circuit die to find a location of a physical feature in the integrated circuit die that is common to multiple failed test paths.
- the combination of logic tests for specific logic paths and computer automated design (CAD) navigation tools that can map the physical paths in an integrated circuit die allows the physical path of a failed test or net across the die to be displayed and plotted.
- the plots from a number of tests performed on different dies for identical test paths may be combined to produce a stacked map for displaying the locations of the highest number of failures to identify physical features on the die that are most likely to be the cause of the failed nets.
- a method of mapping logic failures in an integrated circuit die includes steps of: (a) generating a navigation map of test paths for an integrated circuit die; (b) selecting a grid spacing to define a grid map of cell locations from the navigation map for each of the test paths; and (c) calculating a value for each of the cell locations wherein the value is representative of the difference between a total number of the test paths intersecting each of the cell locations and a failed number of the test paths intersecting each of the cell locations.
- a computer program product for mapping logic failures in an integrated circuit die includes:
- FIG. 1 illustrates an example of a stacked map of the prior art used to locate a common cause of failure on an integrated circuit die
- FIG. 2 illustrates a flow chart for a method of mapping logic failures according to an embodiment of the present invention
- FIG. 3 illustrates a grid map according to an embodiment of the present invention
- FIG. 4 illustrates a grid matrix generated from the grid map of FIG. 3 ;
- FIG. 5 illustrates a combined grid map representative of an overlay of multiple grid maps illustrated in FIG. 3 for multiple test paths
- FIG. 6 illustrates a first combined grid matrix generated from the grid matrices illustrated in FIG. 4 for a total number of tests
- FIG. 7 illustrates a second combined grid matrix generated from the grid matrices illustrated in FIG. 4 for a failed number of tests
- FIG. 8 illustrates a third combined grid matrix generated from the first combined grid matrix of FIG. 6 and the second combined grid matrix of FIG. 7 ;
- FIG. 9 illustrates an inverted ratio matrix generated from the third combined grid matrix of FIG. 8 ;
- FIG. 10 illustrates a filtered logic failure matrix generated from the inverted ratio matrix of FIG. 9 ;
- FIG. 11 illustrates a flow chart for a method and a computer program according to embodiments of the present invention.
- FIG. 1 illustrates an example of a stacked map of the prior art used to locate a common cause of failure on an integrated circuit die. Shown in FIG. 1 are locations 102 and 104 of the highest number of failed nets from a selected set of tests performed on a production lot of integrated circuit dies. Locations 102 indicate centers of logic routing areas, and location 104 is a constricted routing area between memory blocks in the floorplan of the integrated circuit die.
- locations 102 may be representative of a physical feature of the die that is a cause of multiple net failures in some of the locations 102
- the net failures occurring in other locations 102 may be simply the result of an unusually high net density in a specific area that is more susceptible to random defects or an unusually high number of tested nets that pass through the same location 102 .
- a disadvantage of the stacked map method illustrated in FIG. 1 is the difficulty in distinguishing those locations 102 that indicate a common cause of net failure from other locations 102 that indicate separate causes of net failure.
- the locations of the highest number of failed nets indicated on the stacked map may be due to other reasons, for example, an unusually high net density in a specific area of the die that is more susceptible to random defects or an unusually high number of tested nets that pass through the same part of the die.
- a method of mapping logic failures in an integrated circuit die includes steps of: (a) generating a navigation map of a test paths for an integrated circuit die; (b) selecting a grid spacing to define a grid map of cell locations from the navigation map for each of the test paths; and (c) calculating a value for each of the cell locations wherein the value is representative of the difference between a total number of the test paths intersecting each of the cell locations and a failed number of the test paths intersecting each of the cell locations.
- FIG. 2 illustrates a flow chart 200 for a method of mapping logic failures according to an embodiment of the present invention.
- Step 202 is the entry point of the flow chart 200 .
- a grid spacing is selected to define a grid map of cell locations for a navigation map of the integrated circuit die.
- FIG. 3 illustrates a grid map 300 according to an embodiment of the present invention. Shown in FIG. 3 are a selected grid spacing 302 , a test path 304 , and cell locations 306 .
- the selected grid spacing 302 defines the size of the cell locations 306 .
- the size of the cell locations 306 is preferably sufficiently small so that random defects are unlikely to occur in the same cell location 306 and so that finding a physical feature of the die within one of the cell locations 306 may be performed in a reasonable amount of time.
- the size of each of the cell locations 306 may be selected so that the probability of more than one random defect occurring in the same cell location 306 is than a selected threshold, for example, 0.01.
- the size of each of the cell locations 306 should also be large enough so that several tested nets are likely to pass through, that is, intersect the same cell location 306 .
- a grid spacing 302 of about 50 to 200 microns is generally sufficient to meet these criteria.
- a test path 304 is overlaid on the grid map 300 .
- the test path 304 may be copied to the grid map 300 from a navigation map or generated from the floorplan of the integrated circuit die according to well-known techniques.
- a grid map is defined in this manner for each test path 304 selected for testing the integrated circuit die.
- a value is assigned to each cell location 306 of the grid map 300 to indicate which cell locations 306 are intersected by the test path 304 .
- the values assigned to the cell locations of the grid map 300 define a grid matrix.
- FIG. 4 illustrates a grid matrix 400 generated from the grid map 300 of FIG. 3 . Shown in FIG. 4 are cell locations 306 and grid matrix values 402 .
- each cell location 306 intersected by the test path 304 in FIG. 3 is assigned a grid matrix value 402 .
- the cell locations 306 that are intersected by the test path 304 may be assigned a value equal to one, while the cell locations 306 that are not intersected by the test path 304 may be assigned a value equal to zero, shown in FIG. 4 as a blank space.
- Each of the grid matrix values 402 represents an element in a row and column of the matrix shown in FIG. 4 .
- the non-zero elements are ( 1 , 2 ), ( 2 , 2 ), ( 3 , 2 ), ( 3 , 3 ), ( 3 , 4 ), ( 3 , 5 ), ( 3 , 6 ), ( 4 , 6 ), ( 5 , 6 ), ( 6 , 6 ), ( 7 , 6 ), ( 7 , 7 ), and ( 7 , 8 ).
- step 210 the grid maps generated for each of the test paths are overlaid to produce a combined grid map.
- FIG. 5 illustrates a combined grid map 500 representative of an overlay of multiple grid maps illustrated in FIG. 3 for multiple test paths. Shown in FIG. 5 are cell locations 306 and test paths 502 , 504 , and 506 .
- the combined grid map 500 is generated by overlaying the grid maps 300 generated for each of the test paths 502 , 504 , and 506 .
- the combined grid map 500 may include the grid maps 300 for hundreds of test paths, and may also include test data of the same test paths collected from multiple die.
- some of the cell locations 306 are intersected by one of the test paths 502 , 504 , and 506 , some are intersected by two of the test paths 502 , 504 , and 506 , some are intersected by three of the test paths 502 , 504 , and 506 , and some are intersected by none of the test paths 502 , 504 , and 506 .
- the test paths 502 and 504 represent failed test paths
- test path 506 represents a passed test path.
- a first combined grid matrix representative of the combined grid map 500 is generated from the grid matrix 300 of FIG. 3 for each test path.
- FIG. 6 illustrates a first combined grid matrix 600 generated from the grid matrices 400 illustrated in FIG. 4 for a total number of tests.
- the value of each of the cell locations 306 in the grid matrix 600 is calculated by summing the grid matrix values 402 of the corresponding elements in each of the grid matrices 400 .
- the grid matrices 400 for each test path 204 may be summed, for example, by a simple matrix addition that combines a list of all the tests performed on each die with the corresponding pre-calculated grid map for each test path of a given integrated circuit.
- the speed of the matrix addition is advantageously higher than that of plotting logic maps that typically require recalculation from data that generally only includes the endpoints of each test path or similar information.
- the cell locations 306 at ( 3 , 2 ), ( 3 , 4 ), ( 4 , 3 ), ( 6 , 5 ), and ( 6 , 7 ) are each intersected by two test paths and have a corresponding summed value of two.
- the cell locations 306 at ( 3 , 3 ) and ( 6 , 6 ) are each intersected by three test paths and have a corresponding summed value of three.
- the first combined grid matrix 600 of the present invention may be quickly calculated from actual test data. If the tested paths are identical on every die tested, that is, the tests are not stopped after fail, then the calculation of the first combined grid matrix 600 may be further simplified by multiplying the total number of die tested by the grid matrix 400 for each test path.
- step 214 the same summing procedure described above is used to generate a second combined grid matrix for only the failed test paths.
- FIG. 7 illustrates a second combined grid matrix 700 generated from the grid matrices 400 illustrated in FIG. 4 for the failed test paths. Shown in FIG. 7 are cell locations 306 and summed grid matrix values 702 .
- the grid matrix values for only the failed test paths 502 and 504 in FIG. 5 are summed to generate the summed grid matrix values 702 .
- the first combined grid matrix 600 is compared to the second combined grid matrix 700 .
- the comparison may be performed, for example, by calculating the difference between a grid matrix value in the first combined grid matrix 600 and the corresponding grid matrix value in the second combined grid matrix 700 .
- FIG. 8 illustrates a third combined grid matrix generated from the first combined grid matrix of FIG. 6 and the second combined grid matrix of FIG. 7 . Shown in FIG. 8 are the comparison matrix values 802 .
- the comparison matrix values 802 are the result of calculating the difference between the summed grid matrix values in the first combined grid matrix 600 and the corresponding elements in the second combined grid matrix 700 and dividing the difference by the total number of test paths.
- the smaller the comparison value 802 the higher the probability that the logic failure in the corresponding cell location 306 is common to multiple failed test paths intersecting the corresponding cell location 306 and not due to other causes of logic failures in the corresponding cell location 306 .
- Other functions may be used to represent the comparison of the first combined grid matrix of FIG. 6 and the second combined grid matrix of FIG. 7 to suit specific applications according to well-known techniques to practice various embodiments of the present invention within the scope of the appended claims.
- the comparison matrix values 802 of the third combined matrix 800 in FIG. 8 are filtered and adjusted, for example, to display areas of the integrated circuit die to concentrate on for detect analysis.
- the comparison matrix values 802 of the third combined matrix 800 in FIG. 8 may be filtered and adjusted by calculating the reciprocal of the comparison matrix values 802 from the third combined matrix 800 .
- FIG. 9 illustrates an inverted ratio matrix 900 generated from the third combined grid matrix of FIG. 8 .
- Shown in FIG. 9 are the inverted ratio matrix values 902 .
- the inverted ratio matrix values 902 are calculated from the corresponding comparison matrix values 802 of the third combined matrix 800 simply by dividing each of the non-blank comparison matrix values 802 into one. For example, the comparison matrix value at ( 3 , 4 ) equal to 0.5 is divided into one to generate the corresponding inverted ratio matrix value 2 , and so on.
- FIG. 10 illustrates a filtered logic failure matrix 1000 generated from the inverted ratio matrix of FIG. 9 . Shown in FIG. 10 are the filtered logic failure matrix values 1002 .
- the filtered logic failure matrix values 1002 are generated by removing elements from the inverted ratio matrix of FIG. 9 that have a value below a selected threshold, for example, two. The remaining values may then be displayed to direct attention to the specific areas of the integrated circuit die that indicate a physical feature of the integrated circuit die that is a common cause of logic failure.
- Step 220 is the exit point of the flow chart 200 .
- FIG. 11 illustrates a flow chart 1100 for a method and a computer program according to embodiments of the present invention.
- Step 1102 is the entry point of the flow chart 1100 .
- step 1104 a navigation map of test paths for an integrated circuit die is generated according to well-known techniques.
- a grid spacing is selected to define a grid map of cell locations from the navigation map for each of the test paths as described above with reference to the grid map 300 of FIG. 3 .
- a value is calculated for each of the cell locations.
- Each value is representative of the difference between a total number of the test paths intersecting each of the cell locations and a failed number of the test paths intersecting each of the cell locations as described above with reference to the comparison matrix 800 of FIG. 8 .
- Step 1110 is the exit point of the flow chart 1100 .
- a computer program product for mapping logic failures in an integrated circuit die includes:
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050132308A1 (en) * | 2003-12-15 | 2005-06-16 | Bruce Whitefield | Method for calculating high-resolution wafer parameter profiles |
US20060059452A1 (en) * | 2004-08-27 | 2006-03-16 | Whitefield Bruce J | Pattern component analysis and manipulation |
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US7657840B2 (en) * | 2006-11-02 | 2010-02-02 | International Business Machines Corporation | System and method for providing a navigable grid to allow for accessible drag-drop in visual modeling tools |
GB201010744D0 (en) * | 2010-06-25 | 2010-08-11 | Turner Andrew | A method for enabling a person to find a location within an area of space |
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US9973403B2 (en) * | 2014-05-09 | 2018-05-15 | Lawrence F. Glaser | Intelligent traces and connections in electronic systems |
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Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4752887A (en) * | 1985-03-01 | 1988-06-21 | Nec Corporation | Routing method for use in wiring design |
US5032991A (en) * | 1988-12-14 | 1991-07-16 | At&T Ball Laboratories | Method for routing conductive paths |
US5392222A (en) | 1991-12-30 | 1995-02-21 | Schlumberger Technologies Inc. | Locating a field of view in which selected IC conductors are unobscured |
US5568563A (en) | 1993-05-17 | 1996-10-22 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus of pattern recognition |
US5572636A (en) | 1992-05-15 | 1996-11-05 | Fujitsu Limited | Three-dimensional graphics drawing apparatus |
US5644500A (en) * | 1994-03-18 | 1997-07-01 | Fujitsu Limited | Routing program generating method and apparatus therefor, placement program generating method and apparatus therefor, and automatic routing method and apparatus therefor |
US5731986A (en) | 1996-05-06 | 1998-03-24 | Winbond Electronics Corporation | Method of downsizing graphic data of a mask pattern stored in a hierarchical graphic database |
US5751581A (en) | 1995-11-13 | 1998-05-12 | Advanced Micro Devices | Material movement server |
US5841664A (en) * | 1996-03-12 | 1998-11-24 | Avant| Corporation | Method for optimizing track assignment in a grid-based channel router |
US5847965A (en) * | 1996-08-02 | 1998-12-08 | Avant| Corporation | Method for automatic iterative area placement of module cells in an integrated circuit layout |
US5870590A (en) * | 1993-07-29 | 1999-02-09 | Kita; Ronald Allen | Method and apparatus for generating an extended finite state machine architecture for a software specification |
US5923564A (en) * | 1996-08-12 | 1999-07-13 | Advanced Micro Devices, Inc. | Performance analysis including half-path joining |
US6542842B2 (en) * | 2000-03-17 | 2003-04-01 | Harmonic Drive Systems | Method of compensating periodic signals in sensor output |
US6842714B1 (en) * | 2003-08-22 | 2005-01-11 | International Business Machines Corporation | Method for determining the leakage power for an integrated circuit |
US20050022085A1 (en) * | 2003-01-14 | 2005-01-27 | Altera Corporation | Functional failure analysis techniques for programmable integrated circuits |
-
2003
- 2003-07-28 US US10/628,986 patent/US6986112B2/en not_active Expired - Fee Related
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4752887A (en) * | 1985-03-01 | 1988-06-21 | Nec Corporation | Routing method for use in wiring design |
US5032991A (en) * | 1988-12-14 | 1991-07-16 | At&T Ball Laboratories | Method for routing conductive paths |
US5392222A (en) | 1991-12-30 | 1995-02-21 | Schlumberger Technologies Inc. | Locating a field of view in which selected IC conductors are unobscured |
US5572636A (en) | 1992-05-15 | 1996-11-05 | Fujitsu Limited | Three-dimensional graphics drawing apparatus |
US5568563A (en) | 1993-05-17 | 1996-10-22 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus of pattern recognition |
US5870590A (en) * | 1993-07-29 | 1999-02-09 | Kita; Ronald Allen | Method and apparatus for generating an extended finite state machine architecture for a software specification |
US5644500A (en) * | 1994-03-18 | 1997-07-01 | Fujitsu Limited | Routing program generating method and apparatus therefor, placement program generating method and apparatus therefor, and automatic routing method and apparatus therefor |
US5751581A (en) | 1995-11-13 | 1998-05-12 | Advanced Micro Devices | Material movement server |
US5841664A (en) * | 1996-03-12 | 1998-11-24 | Avant| Corporation | Method for optimizing track assignment in a grid-based channel router |
US5731986A (en) | 1996-05-06 | 1998-03-24 | Winbond Electronics Corporation | Method of downsizing graphic data of a mask pattern stored in a hierarchical graphic database |
US5847965A (en) * | 1996-08-02 | 1998-12-08 | Avant| Corporation | Method for automatic iterative area placement of module cells in an integrated circuit layout |
US5923564A (en) * | 1996-08-12 | 1999-07-13 | Advanced Micro Devices, Inc. | Performance analysis including half-path joining |
US6542842B2 (en) * | 2000-03-17 | 2003-04-01 | Harmonic Drive Systems | Method of compensating periodic signals in sensor output |
US20050022085A1 (en) * | 2003-01-14 | 2005-01-27 | Altera Corporation | Functional failure analysis techniques for programmable integrated circuits |
US6842714B1 (en) * | 2003-08-22 | 2005-01-11 | International Business Machines Corporation | Method for determining the leakage power for an integrated circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050132308A1 (en) * | 2003-12-15 | 2005-06-16 | Bruce Whitefield | Method for calculating high-resolution wafer parameter profiles |
US7653523B2 (en) | 2003-12-15 | 2010-01-26 | Lsi Corporation | Method for calculating high-resolution wafer parameter profiles |
US20060059452A1 (en) * | 2004-08-27 | 2006-03-16 | Whitefield Bruce J | Pattern component analysis and manipulation |
US7137098B2 (en) * | 2004-08-27 | 2006-11-14 | Lsi Logic Corporation | Pattern component analysis and manipulation |
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US20050028115A1 (en) | 2005-02-03 |
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