JPS59161769A - Automatic correction system of wiring pattern of printed board - Google Patents

Automatic correction system of wiring pattern of printed board

Info

Publication number
JPS59161769A
JPS59161769A JP58036279A JP3627983A JPS59161769A JP S59161769 A JPS59161769 A JP S59161769A JP 58036279 A JP58036279 A JP 58036279A JP 3627983 A JP3627983 A JP 3627983A JP S59161769 A JPS59161769 A JP S59161769A
Authority
JP
Japan
Prior art keywords
pattern
wiring
wiring pattern
lattice
intersection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58036279A
Other languages
Japanese (ja)
Inventor
Eiichi Konno
栄一 今野
Masaaki Hayashi
政昭 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58036279A priority Critical patent/JPS59161769A/en
Publication of JPS59161769A publication Critical patent/JPS59161769A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/72Repair or correction of mask defects

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of stages of correction and to shorten a correction period by correcting a wiring path in a wiring pattern at a necessary position and correcting the line width and wiring interval of this wiring pattern into necessary values. CONSTITUTION:A pattern P1 which runs on a trace parallel to a main lattice 1 under the main lattice finds the 1st intersection (a) with a main lattice B after passing through a land L1, and a pattern P2 which runs under the pattern P1 in parallel finds the 1st intersection (b) with a longitudinal subordinate lattice after passing through the land L1. Thus, both lines are changed in angle downward by 45 deg. from the positions (a) and (b) in their moving directions; the pattern P1 finds the 1st intersection (c) with a lateral subordinate lattice and the pattern P2 finds the 1st intersection (d) with a main lattice 2. Then, the pattern P1 runs on a lateral subordinate lattice from the intersection (c) and finds intersections (e) and (g) by the means opposite to that of finding the intersections (a) and (b) right before approaching the next land L2. Similarly, the pattern P2 finds intersections (f) and (h) by using the means opposite to that of finding the intersections (b) and (d).

Description

【発明の詳細な説明】 (a)@明の技術分野 本発明は自動配線装置によるプリント板配線パターンの
設計変更に係り、特に所要個所の配線径路を修正して配
線パターンの線幅と配線間隔を変更する方式に利用して
好適な配線パターン自動修正方式に関するものである。
Detailed Description of the Invention (a) Technical Field of @Ming The present invention relates to changing the design of a printed circuit board wiring pattern using an automatic wiring device, and in particular, changing the wiring route at required locations to improve the line width and wiring spacing of the wiring pattern. The present invention relates to an automatic wiring pattern correction method suitable for use in a method for changing a wiring pattern.

(+))従来技術と問題点 従来技術を図に沿って説明する。(+)) Conventional technology and problems The prior art will be explained with reference to the drawings.

第1図は従来の自動配線装置のシステム構成図、第2図
は従来方式で形成されたプリント板配線パターンの一例
を示す。図に2いて1ばCPU、2は入力部、3はメモ
リー、小は出力部、5は共通BUS、主格子A−Fと主
格子1〜2とはそれぞれプリント板設計用の縦及び横の
座標線、L1〜L4゜はランド、Pl及びP2は自己線
パターン、rnは0己線パターンの線幅寸法、dlは配
線パターンの間隔寸法を示している。
FIG. 1 is a system configuration diagram of a conventional automatic wiring device, and FIG. 2 shows an example of a printed board wiring pattern formed by the conventional method. In the figure, 2 is the CPU, 2 is the input section, 3 is the memory, small is the output section, 5 is the common BUS, and the main grids A-F and main grids 1 and 2 are vertical and horizontal grids for printed board design, respectively. In the coordinate lines, L1 to L4° indicate lands, Pl and P2 indicate self-line patterns, rn indicates the line width dimension of the zero-self line pattern, and dl indicates the interval dimension of the wiring pattern.

第1図に示す入力部2には図形作成に必要なデータの入
力装置であるキー人力あるいはカード入力等が用いられ
、出力部4には図形表示装置例えばデイスブVイ装置等
からなり立っている。メモリー3には配線パターン、ラ
ンド、配線禁止領域情報等が記憶されており自動設計の
結果は所定のチェックを径由して出力部4に出力される
The input unit 2 shown in FIG. 1 uses a manual key or card input device for inputting data necessary for graphic creation, and the output unit 4 includes a graphic display device such as a display device. . The memory 3 stores wiring patterns, lands, wiring prohibited area information, etc., and the results of the automatic design are outputted to the output section 4 through a predetermined check.

第2図に示す配線パターンは第1図の装置で自動配線さ
れたパターンの一例であって、ランドL1〜L4 (本
例では各ランドは工Cビン用のものを示す)の間を通り
抜ける配線パターンP1とP2が所定のパターン線幅m
と所定の配線間隔d1をもって、ランドL1とL3の間
及びランドL2とL4の間を通過する配線径路が自動配
線されている。この場合ランドL]〜L4の各中心点は
プリント板設計用の主格子の交叉点に位置し、配線パタ
ーンP1〜P2は必ずしも主格子、あるいは主格子の中
間を通るサブ格子の上を通るものではなくその径路をト
v−スと称する。
The wiring pattern shown in Fig. 2 is an example of a pattern automatically wired using the device shown in Fig. 1, and is a wiring pattern that passes between lands L1 to L4 (in this example, each land is for a work C bin). Patterns P1 and P2 have a predetermined pattern line width m
A wiring path passing between lands L1 and L3 and between lands L2 and L4 is automatically routed with a predetermined wiring interval d1. In this case, each center point of lands L] to L4 is located at the intersection of the main lattice for printed board design, and the wiring patterns P1 to P2 do not necessarily pass over the main lattice or the sub-lattice that passes through the middle of the main lattice. Instead, the path is called a toss.

しかして従来の自動配線では同一信号線に対するパター
ンの幅寸法mは固定であり、かつ通常のパターンにはラ
ンドと他のランドとの間のようにせまい部分があり、短
絡の危険を避けるため単純には太くしない方式をとって
いる。従って既設計のプリント板のパターンの幅寸法n
1を太くI−でパターンによる線抵抗を減少せしめたい
場合には、デイスブVイ装置の画面上に配線パターンを
写し出し、ライトベン等のマニュアル処理によりパター
ンを追加し、所要部分のパターン線幅寸法を太くする手
法が一般的に用いられており、配線パターンの修正処理
には多大の修正工数を要する欠点があった。
However, in conventional automatic wiring, the width dimension m of the pattern for the same signal line is fixed, and a normal pattern has narrow parts such as between one land and another land, so in order to avoid the risk of short circuit, We have adopted a method that does not make it thicker. Therefore, the width dimension n of the pattern of the already designed printed board
If you want to reduce the line resistance due to the pattern by making 1 thicker (I-), project the wiring pattern on the screen of the display device, add the pattern by manual processing using a light ben, etc., and adjust the pattern line width dimension of the required part. A method of making the wiring pattern thicker is generally used, which has the drawback of requiring a large number of man-hours to correct the wiring pattern.

(C)  発明の目的 本発明は上記従来の欠点に鑑み、配線パターンの所要個
所の配線径路を修正し、余裕のある場所に対して線幅を
太くして電気容凧の増大を計り、かつ線間隔を広くして
漏話等の防止を計るための能率的な配線パターンの自動
修正方式の提供を目的とする。
(C) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention aims to increase the electric capacity by modifying the wiring path at required points in the wiring pattern and increasing the line width in areas where there is room for it. The purpose of the present invention is to provide an efficient automatic wiring pattern correction method for widening line spacing to prevent crosstalk, etc.

((i)発明の構成 そしてこの目的は本発明に、l:れば、プリント基板に
プリント配線の位置を設定する自動配線装置における配
線パターンの自動修正方式であって、該配線のパターン
の所要個所の配線径路を修正し、該配線パターンの線幅
と配線間隔とを所要値に修正を行なうようにしたことを
特徴とする配線パターン自動修正方式を提供することに
より達成される。
((i) Structure and object of the invention The present invention provides an automatic wiring pattern correction method in an automatic wiring device for setting the position of printed wiring on a printed circuit board, the method comprising: This is achieved by providing an automatic wiring pattern correction method which is characterized in that the wiring path at a particular location is corrected, and the line width and wiring spacing of the wiring pattern are corrected to required values.

(e)  発明の実施例 以下本発明実施例を第3図乃至第4図によって詳述する
。尚第2図との対応部位には同一符号を付してその重複
説明を省略する。
(e) Embodiments of the Invention Embodiments of the invention will now be described in detail with reference to FIGS. 3 and 4. Note that parts corresponding to those in FIG. 2 are given the same reference numerals, and redundant explanation thereof will be omitted.

第3図(信奉発明の方式により第2図の配線パターンを
修正する自動修正の手順を示すものであって(A)は修
正位置の決定手段の説明図、(、B)は線幅増加手段の
説明図、CG)は修正完了のパターン図を示す、第4・
図は第8図の応用例を示す。
FIG. 3 (Showing the automatic correction procedure for correcting the wiring pattern in FIG. 2 using the method of the believer's invention, (A) is an explanatory diagram of the correction position determining means, and (, B) is the line width increasing means. Explanatory drawing, CG) shows the pattern diagram of completed correction.
The figure shows an example of application of FIG.

図においてイ〜チは配線パターンの方向変更点、1’I
J修正線幅T ITI (n、(i2は修正間隔f d
 1<d 2、ザブ格子は各主格子の中間を通る座標線
、主格子3〜4+は横の座標線、L5I′iランドを示
す。
In the figure, 1 to 1 are the wiring pattern direction change points, 1'I
J correction line width T ITI (n, (i2 is correction interval f d
1<d 2, the Zabu lattice is a coordinate line passing through the middle of each main lattice, the main lattices 3 to 4+ are horizontal coordinate lines, and the L5I'i land.

第3図(、A)に示すランドL]とL3との間を通るパ
ターンP1とP2あるいはランドL2とL4との間を通
るパターンPlとP2とにおいて、各ランドの間隔がせ
寸い光めこの間を通るパターンの線幅は、短絡あるいは
リークを避けるために必然的に、INj約を受ける。こ
の様な特定の場所以外であってかつ余裕のある場所(以
下所要箇所と略称も可能である。
In the patterns P1 and P2 passing between lands L] and L3 shown in FIG. The line width of the pattern passing between them is necessarily subject to INj reduction in order to avoid short circuits or leaks. A place other than such a specific place with sufficient space (hereinafter also abbreviated as "required place").

しかして径路を修正するための手段として座標を用いる
。主格子1の下側を主格子1に平行したトレース上を走
るパターンP1はランドL1を通過してから最初に交わ
る主格子Bとの交点イを探し、パターンP1の下側を平
行して走るlくターンP2はランドL1を通過してから
最初に交わる縦サグ格子との交点口を探す。このように
して両線はイと口の位置からそれぞれ進行方向に列し角
度を45°下に変更し、パターンP11d最初に交わる
横サブ格子との交点ハを探し、パターンP2は最初に交
わる主格子2との交点二を探す。次にパターンP1は交
点ハから横サブ格子上を走り次のランドL2に接近する
手前で交点イと口とを探した手段の逆を用いて交点ホと
トとを探す。同様にしてパターンP2もランドL2やL
4.に接近する手前で交点口とことを探した手段の逆を
用いて交点へとチとを探す。このようにして配線パター
ンの径路変更を行なう。
Thus, coordinates are used as a means to modify the route. Pattern P1 runs on a trace parallel to main grating 1 on the lower side of main grating 1. After passing through land L1, find the intersection A with main grating B that first intersects, and run parallel to the lower side of pattern P1. Turn P2 searches for the first intersection with the vertical sag grid after passing through land L1. In this way, both lines are lined up in the direction of travel from the position of A and the mouth, and the angle is changed to 45 degrees downward, and pattern P11d is found to intersect with the first horizontal sub-grid, and pattern P2 is the main line that intersects first. Find intersection point 2 with grid 2. Next, the pattern P1 runs on the horizontal sub-lattice from the intersection C, and before approaching the next land L2, the intersections Ho and G are searched for using the reverse of the method used to search for the intersections A and the mouth. Similarly, pattern P2 also has lands L2 and L.
4. Before approaching the intersection, search for the intersection using the reverse method of searching for the intersection. In this way, the route of the wiring pattern is changed.

(B)は(A)の説明手段にてできた変更径路のうち横
主格子又は横サブ格子上を通る配線パターンに対しての
み太さを加えるようにしたものであって、最初の線幅m
が所要の線幅nに太く変更されると共に配線パターンの
最初の間隔(l 1も所要の間隔d2に広く変更されて
いる。
(B) is a method in which thickness is added only to the wiring pattern that passes over the horizontal main grid or horizontal sub-grid among the changed paths created by the explanation method in (A), and the initial line width is m
is changed to be thicker to the required line width n, and the initial interval (l1) of the wiring pattern is also changed to be wider to the required interval d2.

(C)は(B)の線幅及び間隔の父更処理によって形成
された修正完了のパターン図を示す。
(C) shows a pattern diagram of the completed correction formed by the line width and spacing retouching process in (B).

第4図は第3図の応用例であって第3図の場合はパター
ンに対し下向きに方向を変更しているが、第4図のよう
にランドL5があるときには随時周囲の状況を既設計の
格納データを利用してチェックしながら上向きあるいは
下向きを決定する。どちらにも配線禁止領域のないとき
は例えば下向きを通常とするように決定する。
Fig. 4 is an application example of Fig. 3, and in the case of Fig. 3, the direction is changed downward with respect to the pattern, but when there is a land L5 as shown in Fig. 4, the surrounding situation is changed as needed by the pre-designed design. The upward or downward direction is determined while checking using the stored data. If there is no wiring prohibited area in either area, it is determined that the downward direction is normal, for example.

第5図は本発明のプリント 動修正の手順を説明するための図である。同図(a)は
、本発明のプリント板の配線パターン自動修正のための
フローチャートを示す図であり、同図(’o)は同図(
a)に示すフローチャートを説明するための図である。
FIG. 5 is a diagram for explaining the procedure of print motion correction according to the present invention. FIG. 3(a) is a flowchart for automatically correcting the wiring pattern of a printed board according to the present invention, and FIG.
It is a figure for explaining the flowchart shown in a).

図においてDFはディスク等の[頁接アクセス記憶装置
に格納された自動配線パターンファイ/し、PIいは磁
気データ等に格納された自動配線パターンファイルを示
す。ビン間とは、同図(b)に示すせまい方のランドと
ランドの間全示し、ピン幅とは広い方のビンの間隔のこ
とであって隣接する主格子間を1グリツドと称しグリッ
ドの数でビンの間隔を計数する。
In the figure, DF indicates an automatic wiring pattern file stored in a page access storage device such as a disk, and an automatic wiring pattern file stored in PI or magnetic data. The distance between the bins refers to the entire space between the narrower lands shown in Figure (b), and the pin width refers to the interval between the wider bins, and the distance between adjacent main grids is referred to as one grid. Count the bin spacing by number.

第5図(a)に示すフローチャーl−に示す通り処理を
行なうことにより既設計の自動配線パターンは、ビン間
を通るパターンがあってかつ所要のグリッド数の間隔を
有する場合には既設計の格納データを利用して拡張可能
な場所を探し、主又はサブの縦横の座標線上に配線パタ
ーンを自動修正することが可能である。
By performing the process shown in flowchart l- shown in FIG. 5(a), the already designed automatic wiring pattern can be changed to It is possible to search for expandable locations using the stored data and automatically correct the wiring pattern on the main or sub vertical and horizontal coordinate lines.

(f)  発明の効果 以上、詳細に説明したように、本発明のプリント板の配
線パターン自動修正方式によれば配線パターンの線幅及
び間隔をできるだけ広く設定することが出来るので、大
電流あるいは漏話等の障害に強いという効果があり、人
手を使わずに変更できるため修正工数の節減・修正期間
の短縮が計れる。
(f) Effects of the Invention As explained in detail above, according to the automatic wiring pattern correction method of the printed board of the present invention, the line width and spacing of the wiring pattern can be set as wide as possible, so that large currents or crosstalk can be avoided. It has the effect of being resistant to obstacles such as these, and can be changed without the use of human resources, reducing the number of man-hours required for corrections and shortening the period of correction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の自動配線装置のシステム構成図、第2図
は従来方式で形成されたプリン)・仮配線パターンの一
例、第3図は本発明の方式により第2図の配線パターン
を修正する自動修正の手順を示すものであって、(A)
は修正位置の決定手段の説明図,(B)は線幅増加手段
の説明図,(C)は修正完了のパターン図を示す。第4
図は第8図の応用例を示す。第5図は本発明のプリント
板の配線パターン自動修正の手順を説明するための図で
ある。 図においてP,とP2は配線パターン、L1〜L5はラ
ンド、mは配線パターンの線幅寸法、11は配線パター
ンの修正部の線幅寸法、d】は配線パターンの線間隔寸
法、d2は配線パターンの11否正部分の線間隔寸法、
イ〜チは配線パターンの方向変更点、DFはディスクに
格納された自動配線パターンファイル、PFは磁気テー
プに格納さり. 7j自動配線パターンフアイルヲ示ス
。 =4λ 第1図 第2図 第 3 図′
Figure 1 is a system configuration diagram of a conventional automatic wiring device, Figure 2 is an example of a temporary wiring pattern formed using the conventional method, and Figure 3 is a modification of the wiring pattern in Figure 2 using the method of the present invention. (A)
(B) is an explanatory diagram of the correction position determining means, (B) is an explanatory diagram of the line width increasing means, and (C) is a diagram of the pattern after the modification is completed. Fourth
The figure shows an example of application of FIG. FIG. 5 is a diagram for explaining the procedure for automatically correcting the wiring pattern of a printed board according to the present invention. In the figure, P and P2 are wiring patterns, L1 to L5 are lands, m is the line width dimension of the wiring pattern, 11 is the line width dimension of the corrected part of the wiring pattern, d] is the line spacing dimension of the wiring pattern, and d2 is the wiring The line spacing dimension of the 11 negative positive part of the pattern,
1 to 1 are the wiring pattern direction change points, DF is the automatic wiring pattern file stored on the disk, and PF is stored on the magnetic tape. 7j Shows automatic wiring pattern file. =4λ Figure 1 Figure 2 Figure 3'

Claims (1)

【特許請求の範囲】[Claims] プリント基板にフ”リント配線の位置を設定する自動配
線装置における配線パターンの自動修正方式であって、
該配線パターンの所要個所の配線径路を修正し、該配線
パターンの線幅と配線間隔と
An automatic wiring pattern correction method in an automatic wiring device that sets the position of flint wiring on a printed circuit board,
Correct the wiring route at the required locations of the wiring pattern, and adjust the line width and wiring spacing of the wiring pattern.
JP58036279A 1983-03-04 1983-03-04 Automatic correction system of wiring pattern of printed board Pending JPS59161769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58036279A JPS59161769A (en) 1983-03-04 1983-03-04 Automatic correction system of wiring pattern of printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58036279A JPS59161769A (en) 1983-03-04 1983-03-04 Automatic correction system of wiring pattern of printed board

Publications (1)

Publication Number Publication Date
JPS59161769A true JPS59161769A (en) 1984-09-12

Family

ID=12465338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58036279A Pending JPS59161769A (en) 1983-03-04 1983-03-04 Automatic correction system of wiring pattern of printed board

Country Status (1)

Country Link
JP (1) JPS59161769A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61125192A (en) * 1984-11-22 1986-06-12 沖電気工業株式会社 Device for shaping and treating wiring pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61125192A (en) * 1984-11-22 1986-06-12 沖電気工業株式会社 Device for shaping and treating wiring pattern
JPH0154747B2 (en) * 1984-11-22 1989-11-21 Oki Electric Ind Co Ltd

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