CN106650137B

CN106650137B - Method for accelerating rationalization of standard unit increment layout

Info

Publication number: CN106650137B
Application number: CN201611242903.6A
Authority: CN
Inventors: 周汉斌; 刘毅; 董森华; 陈彬
Original assignee: Huada Empyrean Software Co Ltd
Current assignee: Beijing Empyrean Technology Co Ltd
Priority date: 2016-12-29
Filing date: 2016-12-29
Publication date: 2020-07-10
Anticipated expiration: 2036-12-29
Also published as: CN106650137A

Abstract

A method of accelerating the rationalization of an incremental layout of standard cells, comprising the steps of: determining circuit units needing incremental layout, and searching matched unit rows; and searching matched unit rows near the target position, and accelerating the process of searching a legal position closest to the target position by using a branch-and-bound method. The method for accelerating the rationalization of the incremental layout of the standard unit adopts a branch-and-bound method, sets the threshold parameter, filters out the suboptimal solution scheme in the solution space, shortens the time for searching the legal position of the standard unit in the incremental layout, and improves the efficiency of design optimization.

Description

Method for accelerating rationalization of standard unit increment layout

Technical Field

The invention relates to the technical field of EDA (electronic design automation) design, in particular to a method for searching a unit rationalization position.

Background

The back-end physical design of very large scale integrated circuits increasingly relies on the assistance of EDA (electronic design automation) tools. Design optimization of a circuit requires changing the type, size, inserting new cells, or moving the location of existing cells in the circuit. In order to ensure that the design rule is not violated, the changed cells must be placed at the legal positions of the cell rows in the chip through layout legalization. How to quickly find the legal position of the unit in the incremental layout is related to the speed and quality of design optimization.

Generally, a chip physical layout includes a plurality of unit rows, that is, physical placement positions of standard units, and units in a circuit must be placed on the unit rows and satisfy constraint requirements such as a certain orientation, and the chip physical layout is considered to be legalized. If layout obstacles exist in the layout or some fixed units which cannot be moved, the unit placement positions in the circuit need to avoid the corresponding areas and cannot be overlapped with the corresponding areas. For each cell requiring a position adjustment in design optimization, a reasonable position needs to be found in the vicinity of the cell, which is a very time-consuming operation for a complex system and causes a violation of design rules if not handled properly.

Disclosure of Invention

In order to solve the defects in the prior art, the invention aims to provide a method for accelerating the rationalization of the incremental layout of the standard cell, and the legal position of the standard cell is searched by a branch-and-bound method.

And setting a threshold parameter, and filtering a suboptimal solution scheme in a solution space. The method is applied to incremental layout, so that the legal position of the standard unit can be found quickly, and the efficiency of design optimization is improved.

In order to achieve the above object, the present invention provides a method for accelerating the rationalization of the incremental layout of a standard cell, comprising the steps of:

1) determining circuit units needing incremental layout, and searching matched unit rows;

2) and searching matched unit rows near the target position, and accelerating the process of searching a legal position closest to the target position by using a branch-and-bound method.

Further, before the step 1), the following steps are also included:

reading in physical information of a chip layout, and positioning the position and size of a unit row in the chip;

the physical location information of each cell contained in the circuit is read in to determine the legal location available in the row of cells.

Further, step 2) further comprises: and determining branches and the optimal solution of each branch.

Further, the method comprises the following steps:

21) setting the directions of all the unit rows as horizontal directions;

22) and determining the target position of the newly added unit, and determining the placeable range of the newly added unit by taking the target position as the center.

Further, the placeable range is determined by timing and wiring congestion constraints of the circuit.

Furthermore, all the cell rows which are overlapped with the placeable range of the newly added cell have the overlapped part which is divided into a left part and a right part by the X coordinate value of the target position, and each part forms a branch in the searching process; the branch is positioned on the left side of the X coordinate value of the target position, and the searching direction of the branch is from right to left; the branch is positioned on the right side of the X coordinate value of the target position point, and the searching direction is from left to right; in the search mode, all branches are in the search process, and the distance between the current search position of the branch and the target position is the lower bound of all the unsearched optimal solutions in the branch; for those branches that have not been searched, the lower bound of all feasible solutions is the difference between the Y-axis coordinate value of the unit row where the branch is located and the target position.

Furthermore, when the new adding unit is arranged in a row at a certain feasible solution position, the distance between the feasible solution and the target position is less than the lower bound of the feasible solutions of all the unsearched areas;

if the in-line layout fails, continuously searching the next feasible solution downwards along the branch searching direction at the branch where the feasible solution is located;

if the feasible solution is found, modifying the lower bound of the branch according to the next feasible solution and adding the branch into the active branch set again; if no feasible solution is found, the branch is discarded.

The method for accelerating the rationalization of the incremental layout of the standard unit adopts a branch-and-bound method, sets the threshold parameter, filters out the suboptimal solution scheme in the solution space, shortens the time for searching the legal position of the standard unit in the incremental layout, and improves the efficiency of design optimization.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a flow chart of a method of accelerating the rationalization of the incremental layout of standard cells according to the present invention;

FIG. 2 is a schematic diagram of physical layout constraint limits in a chip layout according to the present invention;

FIG. 3 is a schematic diagram of an active branch and a branch lower bound according to the present invention;

FIG. 4 is a flow diagram of branch-and-bound policy pseudocode according to the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

Fig. 1 is a flowchart of a method for accelerating the rationalization of the incremental layout of the standard cell according to the present invention, which will be described in detail with reference to fig. 1.

Firstly, reading in physical information of a chip layout, and positioning the position and the size of a unit row in a chip in step 101; reading in physical position information of each unit contained in a circuit, and determining available legal positions in a unit row; and selecting a certain circuit unit needing incremental layout in the chip layout, and searching a matched unit row.

The layout of the chip is located in a circuit design file, which includes a netlist file for recording circuit connection relation, a design rule file, a file for recording chip layout physical information, and the like. Firstly, reading in physical information of a chip layout, and positioning the position and size of a unit row in a chip; the physical location information of each cell contained in the circuit is read in to determine the legal location available in the row of cells.

At step 102, physical layout constraint limits are performed in the chip layout. The unit row in the chip layout contains the alternative legal positions of the units, if some layout obstacles or some fixed units are placed on the unit row, the unit row needs to be divided into unit subrows (narrow), and the unit position adjustment brought by the design optimization operation needs to be carried out on each unit Subrow (narrow).

Fig. 2 is a schematic diagram of restriction of physical layout constraints in a chip layout according to the present invention, as shown in fig. 2, a blank area of a cell row is an alternative legal position of a cell, and layout obstacles and fixed cells are placed on the cell row, the cell row needs to be divided into cell subrows, and adjustment of the cell position needs to be performed on each cell subrow. For example, the physical layout adjustment is required for the cell size change or new insertion buffer cell during the timing optimization process, so that the placement positions of the newly added cell and the original cell on the cell row are legal.

In step 103, a branch-and-bound strategy is adopted to dynamically update the distance threshold value, and incremental layout is performed on the circuit unit. The branch and bound method is a method for searching the solution of the problem on a solution space tree of the problem, and the solution space tree is searched by adopting a method with breadth first or minimum consumption first. The invention utilizes the method of rationalizing the incremental layout of the standard unit of the branch-and-bound acceleration integrated circuit, sets the threshold parameter in the process of positioning the legal position of the unit, and passes the suboptimal solution scheme in the solution space, thereby accelerating the process of searching the optimal placement position of the unit.

FIG. 3 is a diagram illustrating active branches and branch lower bounds according to the present invention, as shown in FIG. 3, showing the determination of branches and the optimal solution lower bounds of each branch during the legalization of the accelerator layout applying the branch-and-bound strategy. The direction of all cell rows in the figure is the horizontal direction, the point marked by "T" is the target position of the newly added cell, and the rectangular area marked by the dotted line with "T" as the center is the placeable range of the newly added cell, which is usually determined by the timing of the circuit, the wiring congestion degree constraint, and the like. The final goal of legalizing the layout of the cell is to find the feasible location closest to the target location within the placeable range and complete the layout.

All the cell rows with overlapping range of the cell can be placed, and the overlapping part is divided into left and right two parts by X coordinate value of "T" point, and each part forms a branch in the searching process. The branch is positioned on the left side of the X coordinate value of the T point, and the searching direction is from right to left; the branch is located at the right side of the X coordinate value of the T point, and the searching direction is from left to right. In the search mode, for all branches in the search process, the distance from the current search position of the branch to the point "T" is the lower bound of all the unsearched partial optimal solutions in the branch; for those branches that have not been searched, the lower bound of all feasible solutions is the difference of Y-axis coordinate values of the distance "T" point of the unit row where the branch is located.

FIG. 4 is a pseudo code flow diagram of a branch-and-bound strategy according to the present invention, where the active branch set refers to the set of all branches in the search process that are required to provide the operation of quickly fetching the branch with the smallest lower bound feasible solution.

When the algorithm decides to layout the added circuit cells in-line at a feasible solution location, it must be ensured that the feasible solution is less than the lower bound of the feasible solutions for all the unsearched regions, from the "T" point. Such a change can be successfully returned once the layout is successful within the row at that point; if the in-line layout fails, the next feasible solution is searched downwards along the direction of the branch search in the branch where the feasible solution is located. If so, modifying the lower bound of the branch according to the next feasible solution and adding the branch into the active branch set again; if not found, it is said that the branch does not have a feasible solution location where the layout can eventually succeed, and the branch will be discarded. If all branches are finally discarded, the fact that no point which can be successfully laid out exists in the search range is indicated, the algorithm returns a legalization failure, and the external calling program withdraws the attempt of the circuit unit at the point.

The invention relates to a method for accelerating rationalization of increment layout of a standard unit, which comprises the steps of firstly reading in physical information of a chip layout and positioning the position and the size of a unit row placed in a chip; reading in physical position information of each unit contained in a circuit, and determining available legal positions in a unit row; searching a matched unit row for a certain circuit unit needing incremental layout; and scanning the matched unit rows up and down near the target position, and accelerating the searching process of the legal position by using a branch-and-bound method.

Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of accelerating the rationalization of an incremental layout of standard cells, comprising the steps of:

2) searching matched unit rows near the target position, and accelerating the process of searching a legal position closest to the target position by using a branch-and-bound method;

the step 2) further comprises the steps of determining the target position of the newly added unit, and determining the placeable range of the newly added unit by taking the target position as the center; all the unit rows which are overlapped with the placeable range of the newly added unit, the overlapped part of the unit rows is divided into a left part and a right part by the X coordinate value of the target position, and each part forms a branch in the searching process;

in the search mode, all branches are in the search process, and the distance between the current search position of the branch and the target position is the lower bound of all the unsearched optimal solutions in the branch; for those branches that have not been searched, the lower bound of all feasible solutions is the difference between the Y-axis coordinate value of the unit row where the branch is located and the target position.

2. A method of accelerating incremental layout rationalization of standard cells according to claim 1, characterized by, before said step 1), further comprising the steps of:

3. The method for accelerating incremental layout rationalization of standard cells according to claim 1, further comprising the steps of:

the direction of all the cell rows is set to the horizontal direction.

4. A method for accelerating incremental layout rationalization of standard cells according to claim 1, characterized in that the placeable range is determined by timing, routing congestion constraints of the circuit.

5. The method for accelerating rationalization of a standard cell incremental layout according to claim 1, wherein the branch located to the left of said target location X coordinate value has a search direction from right to left; and the search direction of the branch positioned on the right side of the X coordinate value of the target position point is from left to right.

6. A method of accelerating incremental layout rationalization of standard cells according to claim 1,

when the newly added unit is subjected to inline layout at a certain feasible solution position, the distance between the feasible solution and the target position is smaller than the lower bound of the feasible solutions of all the unsearched areas;