CN106650137A - Method for accelerating standard cell rationalization in incremental placement - Google Patents
Method for accelerating standard cell rationalization in incremental placement Download PDFInfo
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- CN106650137A CN106650137A CN201611242903.6A CN201611242903A CN106650137A CN 106650137 A CN106650137 A CN 106650137A CN 201611242903 A CN201611242903 A CN 201611242903A CN 106650137 A CN106650137 A CN 106650137A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
A method for accelerating the standard cell rationalization in incremental placement includes the steps of determining circuit units which need incremental placement, and searching for matched cell rows; searching matched cell rows near target positions, and accelerating the search process of legal positions nearest to the target positions. According to the method for accelerating the standard cell rationalization in incremental placement, the branch-and-bound method is adopted, threshold parameters are set, the second-best solution scheme in solution space is filtered out, and in incremental placement, the time for searing for the legal positions of standard cells is shortened, and the efficiency of design optimization is improved.
Description
Technical field
The present invention relates in EDA design fields, it is more particularly to a kind of to find the method that unit rationalizes position.
Background technology
The back-end physical design of super large-scale integration is increasingly dependent on EDA（Electric design automation）Instrument it is auxiliary
Help.The design optimization of circuit needs type, the size for changing unit in circuit, inserts new unit, or movement has unit
Position.In order to ensure not violate design rule, the unit after change has to pass through layout and legalizes, and puts cell row in the chips
Legal position.The unit legal position how being quickly found out in increment layout, is related to the speed and quality of design optimization.
Generally, some cell rows, the i.e. putting position of standard block physics are included in chip makes physical domain, in circuit
Unit must put in cell row, and meet it is certain towards etc. constraint requirements, be considered as and legalize.If there is cloth in the middle of domain
Office's obstacle or some irremovable fixed cells, then the unit putting position in circuit need to avoid respective regions, it is impossible to
Overlap.For each unit of demand adjustment position in design optimization, it is required for region in its vicinity to find reasonable position
Put, be a very time-consuming operation for complication system, if dealt with improperly, can also cause design rule to violate.
The content of the invention
In order to solve the deficiency of prior art presence, it is an object of the invention to provide a kind of accelerate standard block increment cloth
The method that office rationalizes, by the method for branch-and-bound, finds the legal position of standard block.
Threshold parameter is set, the suboptimal solution scheme in solution space is filtered out.This method is applied in increment layout, Ke Yijia
Speed finds the legal position of standard block, improves the efficiency of design optimization.
For achieving the above object, the method for acceleration standard block increment rationally distributedization that the present invention is provided, including it is following
Step：
1）It is determined that needing the circuit unit for carrying out increment layout, the cell row of matching is found；
2）The cell row of matching is searched near target location, accelerates to find distance objective position most using the method for branch-and-bound
The process of near legal position.
Further, in the step 1）Before, it is further comprising the steps of：
Read in chip layout physical message, position and size that bit cell row is put in the chips；
Read in the physical location information that circuit includes unit, available legal position in determining unit row.
Further, step 2）Further include：Determine branch and each branch's optimal solution.
Further, it is further comprising the steps：
21）The direction of all cell rows is set to into horizontal direction；
22）It is determined that the target location of the new unit for adding, determined centered on the target location and new add placing for unit
Scope.
Further, sequential, wiring congestion constraint determination of the scope placed by circuit.
Further, all scopes placed with new addition unit have overlap cell row, and its lap is by institute
The X-coordinate value for stating target location is divided into left and right two parts, and each part forms a branch in search procedure；Positioned at institute
The branch on the target location X-coordinate value left side is stated, its direction of search is for from right to left；It is right positioned at the source location X-coordinate value
The branch on side, its direction of search is for from left to right；Under the search pattern, all branches just in search procedure, branch
The distance of current search positional distance target location is exactly the lower bound of all optimal solutions for not searching part in the branch；And it is right
In those also without the searched branch for arriving, the lower bound of their all feasible solutions is branch place cell row distance objective position
Y-axis coordinate value gap.
Further, when layout in every trade is entered in a certain feasible solution position to new addition unit, feasible solution distance objective
Lower bound of the distance of position less than the feasible solution in all regions not searched；
If layout failure in row, the next one is continually looked for downwards along the direction of branch's search in the feasible solution place branch
Feasible solution；
Feasible solution is found, then the lower bound of the branch is changed according to next feasible solution and again the branch is added to into active branch
In the middle of set；If not finding feasible solution, the branch is abandoned.
The method of acceleration standard block increment rationally distributedization of the present invention, using the method for branch-and-bound, arranges threshold value
Parameter, filters out the suboptimal solution scheme in solution space, in increment layout, shorten find standard block legal position when
Between, improve the efficiency of design optimization.
Other features and advantages of the present invention will be illustrated in the following description, also, the partly change from specification
Obtain it is clear that or being understood by implementing the present invention.
Description of the drawings
Accompanying drawing is used for providing a further understanding of the present invention, and constitutes a part for specification, and with the present invention's
Embodiment together, for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the method flow diagram of acceleration standard block increment rationally distributedization according to the present invention；
Fig. 2 is that the physical layout constraint in the chip layout according to the present invention limits schematic diagram；
Fig. 3 is the active branch and branch's lower bound schematic diagram according to the present invention；
Fig. 4 is the branch and boundstrategy false code flow chart according to the present invention.
Specific embodiment
The preferred embodiments of the present invention are illustrated below in conjunction with accompanying drawing, it will be appreciated that preferred reality described herein
Apply example and be merely to illustrate and explain the present invention, be not intended to limit the present invention.
Fig. 1 is the method flow diagram of acceleration standard block increment rationally distributedization according to the present invention, below with reference to figure
1, the method for acceleration standard block increment rationally distributedization of the present invention is described in detail.
First, in step 101, chip layout physical message, position and chi that bit cell row is put in the chips are read in
It is very little；Read in the physical location information that circuit includes unit, available legal position in determining unit row；In chip layout
Middle selection needs to carry out a certain circuit unit of increment layout, finds the cell row of matching.
The domain of chip is located in circuit design file, including, the net meter file of writing circuit annexation, design rule
File, file of memorization COMS clip domain physical message etc..Chip layout physical message is read in first, and bit cell row is in the chips
The position put and size；The physical location information that circuit includes unit is read in, it is available legal in determining unit row
Position.
In step 102, physical layout constraint is carried out in chip layout and is limited.Cell row in chip layout contains list
The alternative legal position of unit, if some layout obstacles have been put in cell row, or some fixed cells, then need unit
Row cutting is unit sub-line (Subrow), and the cell position adjustment that design optimization operation brings is needed in unit sub-line
(Subrow) carry out on.
Fig. 2 is that the physical layout constraint in the chip layout according to the present invention limits schematic diagram, as shown in Fig. 2 cell row
White space be unit alternative legal position, layout obstacle and fixed cell have been put in cell row, then need unit
Row cutting is unit sub-line, and the adjustment of cell position needs to be carried out in unit sub-line.For example, it is right during timing optimization
The change of unit size or new Buffer insertion unit are required for carrying out the adjustment of physical layout so that new to add unit and original
Beginning unit putting position in cell row all legalizes.
In step 103, using branch and boundstrategy, dynamic updates distance threshold, to circuit unit increment layout is carried out.Point
It is a kind of method of the solution of the search problem on the solution space tree of problem to prop up demarcation method, excellent using breadth First or minimum consuming
First method search solution space tree.The present invention accelerates the side of integrated circuit standard unit increment rationally distributedization using branch-and-bound
Method, during positioning unit legal position, arranges threshold parameter, crosses the suboptimal solution scheme in solution space, so as to accelerate to seek
Look for the process of the optimal putting position of unit.
Fig. 3 is the active branch and branch's lower bound schematic diagram according to the present invention, as shown in figure 3, showing in application point
Delimit during tactful accelerator module layout legalizes, the determination of branch and each branch's optimal solution lower bound.All lists in figure
The direction of first row is horizontal direction, and the point identified with " T " is the target location of the new unit for adding, the dotted line centered on " T " point
The rectangular area being identified is the scope placed of the new addition unit, and the scope is generally gathered around by the sequential of circuit, wiring
Squeeze degree constraint etc. to determine.The final goal that legalizes to the layout of the unit is can to find distance objective position in placing range
Nearest feasible location simultaneously completes layout.
It is all with the unit can placing range have overlap cell row, its lap is divided into by the X-coordinate value of " T " point
Left and right two parts, each part forms a branch in search procedure.The branch on the X-coordinate value left side is put positioned at " T ", its
The direction of search is for from right to left；The branch on the right of X-coordinate value is put positioned at " T ", its direction of search is for from left to right.In this search
Under pattern, all branches just in search procedure, the distance of current search positional distance " T " point of branch is exactly in the branch
The lower bound of all optimal solutions for not searching part；And for those are also without the searched branch for arriving, they all feasible
The lower bound of solution is the gap of the Y-axis coordinate value of branch's place cell row distance " T " point.
Fig. 4 be according to the present invention branch and boundstrategy false code flow chart, in figure active branch collection refer to it is all just
Branch's set in search procedure, the set needs to provide the operation for quickly removing the branch for possessing minimum lower bound feasible solution.
When algorithm determines to enter layout in every trade to addition circuit unit in a certain feasible solution position, it is necessary to ensure that this is feasible
Lower bound of the distance of solution distance " T " point less than the feasible solution in all regions not searched.Suchization, once in the point row
Layout successfully can be successfully returning；And if the change of the interior layout failure of row, can be in the feasible solution place branch along the branch
The direction of search continually looks for downwards next feasible solution.If it is found, then being changed under the branch according to next feasible solution
Boundary is simultaneously again added to the branch in the middle of active branch set；If do not found, illustrating that the branch is not present may finally
The successful feasible solution position of layout, the branch will be dropped.If final all of branch is all dropped, hunting zone is illustrated
Inside not existing can be with the successful point of layout, and algorithm is returned and legalized unsuccessfully, and external call program is recalled in the point to the circuit list
The trial of unit.
The method of acceleration standard block increment rationally distributedization of the present invention, reads in first chip layout physical message, fixed
Position and size that bit cell row is put in the chips；The physical location information that circuit includes unit is read in, it is determined that single
Available legal position in first row；For a certain circuit unit for needing to carry out increment layout, the cell row of matching is found；In mesh
Near cursor position, the cell row of upper and lower scan matching accelerates the searching process of legal position using the method for branch-and-bound.
One of ordinary skill in the art will appreciate that：The foregoing is only the preferred embodiments of the present invention, and without
In the present invention is limited, although being described in detail to the present invention with reference to the foregoing embodiments, for those skilled in the art
For, it still can modify to the technical scheme that foregoing embodiments are recorded, or which part technical characteristic is entered
Row equivalent.All any modification, equivalent substitution and improvements within the spirit and principles in the present invention, made etc., all should include
Within protection scope of the present invention.
Claims (7)
1. it is a kind of accelerate standard block increment rationally distributedization method, it is characterised in that comprise the following steps：
1）It is determined that needing the circuit unit for carrying out increment layout, the cell row of matching is found；
2）The cell row of matching is searched near target location, accelerates to find distance objective position most using the method for branch-and-bound
The process of near legal position.
2. it is according to claim 1 accelerate standard block increment rationally distributedization method, it is characterised in that in the step
Rapid 1）Before, it is further comprising the steps of：
Read in chip layout physical message, position and size that bit cell row is put in the chips；
Read in the physical location information that circuit includes unit, available legal position in determining unit row.
3. it is according to claim 1 accelerate standard block increment rationally distributedization method, it is characterised in that step 2）Enter
One step includes：Determine branch and each branch's optimal solution.
4. the method for accelerating standard block increment rationally distributedization according to claim 3, it is characterised in that further bag
Include following steps：
21）The direction of all cell rows is set to into horizontal direction；
22）It is determined that the target location of the new unit for adding, determined centered on the target location and new add placing for unit
Scope.
5. it is according to claim 4 accelerate standard block increment rationally distributedization method, it is characterised in that it is described to put
Sequential, wiring congestion constraint determination of the scope put by circuit.
6. it is according to claim 4 accelerate standard block increment rationally distributedization method, it is characterised in that it is all with it is new
Adding the scope placed of unit has a cell row of overlap, its lap by the X-coordinate value of the target location be divided into a left side,
Right two parts, each part forms a branch in search procedure；Dividing positioned at the target location X-coordinate value left side
, its direction of search is for from right to left；Branch on the right of the source location X-coordinate value, its direction of search is from a left side
To the right side；Under the search pattern, all branches just in search procedure, the current search positional distance target location of branch
Distance is exactly the lower bound of all optimal solutions for not searching part in the branch；And for those also it is searched arrive point
, the lower bound of their all feasible solutions is the gap of the Y-axis coordinate value of branch place cell row distance objective position.
7. it is according to claim 6 accelerate standard block increment rationally distributedization method, it is characterised in that
When layout in every trade is entered in a certain feasible solution position to new addition unit, the distance of feasible solution distance objective position is less than institute
There is the lower bound of the feasible solution in the region not searched；
If layout failure in row, the next one is continually looked for downwards along the direction of branch's search in the feasible solution place branch
Feasible solution；
Feasible solution is found, then the lower bound of the branch is changed according to next feasible solution and again the branch is added to into active branch
In the middle of set；If not finding feasible solution, the branch is abandoned.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611242903.6A CN106650137B (en) | 2016-12-29 | 2016-12-29 | Method for accelerating rationalization of standard unit increment layout |
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| CN201611242903.6A CN106650137B (en) | 2016-12-29 | 2016-12-29 | Method for accelerating rationalization of standard unit increment layout |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107832571A (en) * | 2017-12-21 | 2018-03-23 | 北京华大九天软件有限公司 | The method that unit amount of movement is reduced in integrated circuit standard unit increment layout |
| CN112989751A (en) * | 2021-05-11 | 2021-06-18 | 中国人民解放军国防科技大学 | Circuit channel wiring method and device based on branch-and-bound method and electronic equipment |
| CN116579286A (en) * | 2023-05-29 | 2023-08-11 | 深圳亿方联创科技有限公司 | Incremental layout method based on auction algorithm |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107832571A (en) * | 2017-12-21 | 2018-03-23 | 北京华大九天软件有限公司 | The method that unit amount of movement is reduced in integrated circuit standard unit increment layout |
| CN112989751A (en) * | 2021-05-11 | 2021-06-18 | 中国人民解放军国防科技大学 | Circuit channel wiring method and device based on branch-and-bound method and electronic equipment |
| CN116579286A (en) * | 2023-05-29 | 2023-08-11 | 深圳亿方联创科技有限公司 | Incremental layout method based on auction algorithm |
| CN116579286B (en) * | 2023-05-29 | 2024-04-30 | 深圳亿方联创科技有限公司 | Incremental layout method based on auction algorithm |
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