CN100341387C - Method for automatic generating device mark in printed circuit board design - Google Patents
Method for automatic generating device mark in printed circuit board design Download PDFInfo
- Publication number
- CN100341387C CN100341387C CNB031366287A CN03136628A CN100341387C CN 100341387 C CN100341387 C CN 100341387C CN B031366287 A CNB031366287 A CN B031366287A CN 03136628 A CN03136628 A CN 03136628A CN 100341387 C CN100341387 C CN 100341387C
- Authority
- CN
- China
- Prior art keywords
- device identification
- identification
- circuit board
- priority
- mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000013461 design Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000009434 installation Methods 0.000 claims description 7
- 238000012360 testing method Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012467 final product Substances 0.000 description 3
- 230000005055 memory storage Effects 0.000 description 2
- 235000012364 Peperomia pellucida Nutrition 0.000 description 1
- 240000007711 Peperomia pellucida Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention discloses a method for automatically generating component marks in the design of a printed circuit board, which comprises the following steps that character string information used in component marks is read from an information bank for storing a circuit board drawing, and the attribute of a character string is treated so as to satisfy prescribed mark directions and character styles; then, according to the distance value of a designated component mark and a corresponding component, a mark region series which is composed of a plurality of candidate mark sub regions is formed around the component; a candidate mark sub region which is suitable to place component marks is formed in the mark region series according to the avoidance of priority control, and component marks are generated in the mark sun region.
Description
Technical field
The present invention relates to a kind of method that automatic generator spare identifies in PCB design.
Background technology
After printed circuit board (being called for short PCB) design is finished, the device identification of all devices in the PCB design need be put suitable position.Usually, the number of device is quite numerous in the PCB design, and the correctness of device identification position and direction, directly affects follow-up production and processing, exploitation debugging, so this work also is to have suitable importance.The pose technology of existing P CB plate device identification is finished by the designer is manual fully, without any aid offer help.
There is following shortcoming in prior art:
Owing to need to transfer the device identification number of putting numerous, cause designer's fatigue easily; Be very easy to occur device identification and put mistakes such as dislocation, directly influence production and processing and exploitation debugging; Workload is big, is the bottleneck that improves design efficiency.
Summary of the invention
The object of the present invention is to provide a kind of method that automatic generator spare identifies in PCB design, to avoid mistake and to raise the efficiency.
Technical scheme of the present invention:
A kind of method that automatic generator spare identifies in PCB design, by near this device of the sign device of computer installation in printed circuit board figure, the method comprising the steps of:
Reading device identification information from the information bank of depositing circuit board figure, and the attribute of device identification handled to satisfy the device identification direction and the font of regulation;
According to the distance value of the device identification and the respective devices of appointment, around this device, determine an identified areas series that constitutes by a plurality of candidate identification subregions; And
From described identified areas series, determine a suitable candidate identification subregion of putting device identification according to dodging priority control, and generate device identification at this sign subregion.
According to technique scheme:
Described priority and the device identification input equipment by computer of dodging provides the default value that the device that perhaps uses a computer provides.
Only directly over the device, under, front-left and front-right determine the candidate identification subregion.
Described sign subregion is the rectangular area.
The priority that different device employings is different and/or the different device identification and the distance value of respective devices.
Beneficial effect of the present invention:
The present invention is directed to the present situation of PCB design, proposed a kind of method of putting device identification automatically, the problem below having solved:
(1) service routine is finished putting of device identification automatically, and the designer is freed from heavy manual labor, leaves the more think time of designer for;
(2) stop device identification and put wrong generations such as dislocation, reached device identification font unanimity in all PCB designs, for follow-up production and processing and exploitation debugging are provided convenience;
(3) improved design efficiency greatly, manual setting needs 1 day/people's work, uses this program only to need 1～2 o'clock/people just can finish.
Description of drawings
Fig. 1 is a computer installation structural representation of the present invention;
Fig. 2 is a main flow chart of the present invention;
Fig. 3 for device identification to device apart from schematic diagram;
Fig. 4 is the I/O schematic diagram of functional module of the present invention;
The candidate region diagrammatic series of views of Fig. 5 for forming.
Embodiment
Fig. 1 has shown that is used for implementing a computer of the present invention.Computer has a processor, and it is connected with memory by bus, also connects input/output interface by bus simultaneously.Memory storage circuit printing plate design program.Input/output interface connects keyboard, external memory storage and display, and circuit printing plate figure shows by display, perhaps output equipments such as the printer output by being connected with computer.
Owing to need satisfied requirement simultaneously from aspects such as technology, production, debugging, standards by the device identification among the circuit printing plate figure of computer installation generation, through abstract processing, after being transformed into these requirements in printed circuit board (the being called for short PCB) design, the putting position of requirement device identification can be in the custom position of common manual setting, and the concrete requirement of putting device identification is:
(1) device identification is not far apart from related device, because apart from the fork meaning that causes that easily identification is affiliated too far away;
(2) the not pad, device body, on-line testing of covering device (in-circiuttest, test point ICT), other literal (must satisfy) as far as possible can not cover on the via hole (nonessential satisfy) of device identification;
(3) angle, direction are conformed to the standard and are accustomed to;
(4) consideration that is designed beautifully makes the font of all device identification into unified specification.
The PCB design is a kind of planar design, especially puts the work of device identification.All objects all have (comprising device, via hole, literal etc.) drop shadow spread of a maximum in the PCB design, are referred to as object bounds, and in the PCB design of having finished, except device identification, the position of other object is all fixed.So satisfying under the prerequisite of above-mentioned some requirement, in fact the problem of putting device identification can be converted into such processing requirements:
(1) object bounds of device identification is controlled apart from the distance of the object bounds of related device;
(2) object bounds of device identification does not overlap with the object bounds of other objects;
(3) object bounds angle, the direction of device identification are suitable;
(4) the object bounds height unanimity of device identification, but different because the length of character string is different.
String attribute by device identification, its object bounds must be a rectangle, and may there be shapes such as circle, ellipse, triangle in other objects on the pcb board, and for shortcut calculation is converted into rectangle with all non-rectangle borders, the problem description of so final formation is as follows:
On plane with known dimensions, there is the rectangle of some fixed positions, other rectangle to be positioned is arranged, need in this plane, seek foothold, requirement is satisfied not with the rectangle that has existed and is found the rectangle generation to be positioned border of foothold to overlap recently.Simultaneously, having existed in each rectangle to be positioned and the plane has man-to-man dependency relation between the rectangle, exists the distance between the rectangle of dependency relation can not be far away excessively, and the standard of judgement is to conform to the standard and be accustomed to.
Consult shown in Figure 2, method of the present invention is, read the character string information that is used for device identification earlier, and the attribute of character string handled to satisfy the sign direction and the font of regulation, around device, determine an identified areas series that constitutes by a plurality of candidate identification subregions then, last therefrom definite suitable candidate identification subregion of putting device identification, and in this sign subregion generation device identification.
Be elaborated below in conjunction with the realization of accompanying drawing to said method:
Handle direction and font: the design document of PCB design software Allegro has adopted a kind of structure of object tree to come stored information, and each object all has the attribute of oneself.The device label is exactly in this object tree, can revise the direction and the font of device label easily by the attribute of revising the device label.The Skill language provides visit and has revised the interface of all objects in the object tree, and the programming by the Skill language is the direction and the font of processing apparatus label easily.
When determining the correct position of device identification, dodge priority and device identification to the distance of device as necessary input parameter, can also can provide default value by the input equipment input of computer installation by computer installation.
Dodge priority: in the PCB of reality design, in order to make device identification can be relatively easy to identification, the actual conditions of putting according to the device label, need device identification that these objects are dodged (not covering), comprise: device body, pad, ICT test point, other literal, via hole, here the priority of having dodged has as required been arranged from high to low, sees the following form.
| Priority | Device body | Device bonding pad | The ICT test point | Other literal | Via hole |
| 0 | Y | ||||
| 1 | Y | Y | |||
| 2 | Y | Y | Y | ||
| 3 | Y | Y | Y | Y | |
| 4 | Y | Y | Y | Y | Y |
The explanation device identification needs the priority of the object of dodging out in the table in PCB design.For example, when priority parameters is 4, objects all in the his-and-hers watches being dodged, is 3 o'clock, will ignore the existence of via hole, and the rest may be inferred.The strategy of selection priority can be very flexible in the reality.
Device identification is to the distance of device: refer to the minimum distance of device identification projection rectangle to the device projection rectangle, be illustrated in fig. 3 shown below, wherein the distance of device identification D6 and device is d.
Seek suitable position and solve " rectangle COINCIDENCE PROBLEMS on the plane " exactly.This function is made a module, dodge priority and device identification and arrive two input parameters of the distance of device as this module, the coordinate that is output as the rectangular area that can correctly put device identification is to (coordinate of rectangular area is right: lower left corner coordinate and upper right corner coordinate), as shown in Figure 4.
In a PCB design of having finished, other such as via hole, device, literal except that device identification etc. all has fixing position, and corresponding device identification of each device, always wish that device identification can try one's best apart from its corresponding device more closely, so just produced the input parameter of a device identification apart from the device distance.Size (can from the PCB design document, directly read) according to this parameter and device identification character string itself, can around relevant device, calculate a rectangular area series, N different rectangle arranged in this rectangular area series in theory, whether in these rectangular areas have the suitable rectangle of putting device identification, find the back just device identification to be moved over and get final product if judging then.In order to simplify calculating, the faster procedure speed of service, and the actual conditions that combine PCB design, do not need to carry out so many judgement, only need to judge just the going up of rectangular area, device position, a positive left side, just down, four rectangular areas, the right side suitable getting final product whether just.
Fig. 5 has illustrated the schematic diagram of candidate's device identification rectangle series: wherein d is an input parameter, be the distance of device identification apart from device, the rectangular area of four solid lines in upper and lower, left and right is zones that program is made judgement in the reality, and the rectangular area of dotted line is all rectangular areas that can calculate the position.
Obtaining afterwards through the candidate rectangle of simplifying regional serial (only comprising four rectangles in upper and lower, left and right), then according to dodging the priority parameters input, judge in above-mentioned four rectangular areas whether have the rectangle that is fit to put device identification, device identification is moved over get final product then.(also have a kind of situation to be: through judging that above-mentioned four candidate rectangle zones all are not suitable for putting device identification, the processing of this situation will provide processing method in the related description below.) because PCB design is ever-changing, so realize on the pcb board that it itself is a very complicated problems that the Automatic Program of device identification is put.The present invention has well solved the problem that device identification is put automatically in the PCB design, but running into the very high or pcb board local density of device density when very high, can go out the situation that four candidate rectangles all are not suitable for putting device identification, solution is by program device identification to be moved to the center of its related device and this device of highlighted demonstration, then by the manual setting position.Because this situation has negligible amounts, adopting this solution also is very economical.
Can repeatedly carry out method of the present invention to same printed circuit board figure by computer installation, each by importing the different numerical value of dodging priority and device identification and device distance parameter, arrive different control effects, common PCB design, after carrying out 2～3 times, basically do not need to adjust by hand again, satisfy the requirement of standard and custom fully.
Claims (6)
1, a kind of method that automatic generator spare identifies in Printed Circuit Board Design by automatically device being identified near the device of computer installation in printed circuit board figure, is characterized in that the method comprising the steps of:
From the information bank of depositing circuit board figure, read the character string information that is used for device identification, and the attribute of character string is handled to satisfy the sign direction and the font of regulation;
According to the distance value of the device identification and the respective devices of appointment, around this device, determine an identified areas series that constitutes by a plurality of candidate identification subregions; And
From described identified areas series, determine a suitable candidate identification subregion of putting device identification according to dodging priority control, and generate device identification at this sign subregion.
2, the method for claim 1 is characterized in that, described priority and the distance value input equipment by computer of dodging provides the default value that the device that perhaps uses a computer provides.
3, the method for claim 1 is characterized in that, only directly over the device, under, front-left and front-right determine the candidate identification subregion.
4, as claim 1 or 3 described methods, described sign subregion is the rectangular area.
5, the method for claim 1 is characterized in that, the priority that different device employings is different and/or the different device identification and the distance value of respective devices.
6, as claim 1 or 5 described methods, it is characterized in that, priority order from high to low is: the test point of device body, device bonding pad, on-line testing ICT, other literal, via hole, wherein device identification will be implemented to dodge according to the height of priority.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031366287A CN100341387C (en) | 2003-05-21 | 2003-05-21 | Method for automatic generating device mark in printed circuit board design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031366287A CN100341387C (en) | 2003-05-21 | 2003-05-21 | Method for automatic generating device mark in printed circuit board design |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1549671A CN1549671A (en) | 2004-11-24 |
| CN100341387C true CN100341387C (en) | 2007-10-03 |
Family
ID=34323401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031366287A Expired - Lifetime CN100341387C (en) | 2003-05-21 | 2003-05-21 | Method for automatic generating device mark in printed circuit board design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100341387C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104053306A (en) * | 2014-06-17 | 2014-09-17 | 浪潮集团有限公司 | PCB device bit number design and wrongly marked position inspection method |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281027B (en) * | 2008-05-26 | 2010-06-16 | 北京星网锐捷网络技术有限公司 | Method and apparatus for detecting unqualified silk screen printing mark |
| CN101968822B (en) * | 2009-07-27 | 2012-05-23 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board wiring system and character direction adjusting method |
| CN102385644B (en) * | 2010-08-31 | 2013-12-11 | 英业达股份有限公司 | Drawing method of text tag of circuit board |
| CN103838903A (en) * | 2012-11-27 | 2014-06-04 | 北京华大九天软件有限公司 | Method for creating Label through user-defined font object library |
| CN103902289A (en) * | 2014-03-25 | 2014-07-02 | 浪潮电子信息产业股份有限公司 | Method for quickly adjusting text direction |
| CN104615830A (en) * | 2015-02-10 | 2015-05-13 | 浪潮集团有限公司 | Component attaching method and device based on PCB design |
| CN106294980A (en) * | 2016-08-08 | 2017-01-04 | 浪潮集团有限公司 | A kind of method of auto arrangement silk-screen in PCB |
| CN107590344A (en) * | 2017-09-20 | 2018-01-16 | 广合科技（广州）有限公司 | A kind of automatic editing system and method for carrying out outside line windowing |
| CN109451654A (en) * | 2018-11-01 | 2019-03-08 | 郑州云海信息技术有限公司 | A kind of method, apparatus producing circuit board, circuit board, server and system |
| CN112597737B (en) * | 2020-12-20 | 2022-08-26 | 苏州浪潮智能科技有限公司 | Method, system and readable storage medium for creating PCB test point identification |
| CN114096061A (en) * | 2021-11-03 | 2022-02-25 | 胜宏科技（惠州）股份有限公司 | Method and management system for automatically avoiding edge banding of PCB (printed circuit board) |
| CN114492293B (en) * | 2022-02-10 | 2022-11-25 | 深圳市亿道电子科技有限公司 | Automatic circuit splicing system and method based on altium software |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11353350A (en) * | 1998-06-10 | 1999-12-24 | Pfu Ltd | Substrate drawing preparing device |
| US6317859B1 (en) * | 1999-06-09 | 2001-11-13 | International Business Machines Corporation | Method and system for determining critical area for circuit layouts |
| JP2002084058A (en) * | 2000-09-08 | 2002-03-22 | Horiba Ltd | Printed board producing system |
| US6564364B1 (en) * | 2000-11-15 | 2003-05-13 | Reshape, Inc. | Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file |
-
2003
- 2003-05-21 CN CNB031366287A patent/CN100341387C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11353350A (en) * | 1998-06-10 | 1999-12-24 | Pfu Ltd | Substrate drawing preparing device |
| US6317859B1 (en) * | 1999-06-09 | 2001-11-13 | International Business Machines Corporation | Method and system for determining critical area for circuit layouts |
| JP2002084058A (en) * | 2000-09-08 | 2002-03-22 | Horiba Ltd | Printed board producing system |
| US6564364B1 (en) * | 2000-11-15 | 2003-05-13 | Reshape, Inc. | Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104053306A (en) * | 2014-06-17 | 2014-09-17 | 浪潮集团有限公司 | PCB device bit number design and wrongly marked position inspection method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1549671A (en) | 2004-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100341387C (en) | Method for automatic generating device mark in printed circuit board design | |
| JP2886481B2 (en) | How to place objects | |
| Williams | STICKS-A graphical compiler for high level LSl design | |
| JP2003502769A (en) | How to modify an integrated circuit | |
| US20080046849A1 (en) | Method for changing physical layout data using virtual layer | |
| CN101901494A (en) | Method and system for automatically realizing map lettering | |
| US6539528B2 (en) | Methods, systems, and computer program products for designing an integrated circuit that use an information repository having circuit block layout information | |
| US7590963B2 (en) | Integrating multiple electronic design applications | |
| CN103093181A (en) | License plate image locating method and device | |
| JPS63245940A (en) | Block disposition processing system | |
| JP4652242B2 (en) | Cell arrangement method for semiconductor integrated circuit | |
| US7107200B1 (en) | Method and apparatus for predicting clock skew for incomplete integrated circuit design | |
| CN101739477A (en) | Method for setting marking words of printed circuit board | |
| CN116227407B (en) | Method for forming module boundary of physical layout and related equipment | |
| JPH08212241A (en) | Design method for mask pattern for semiconductor integrated circuit or directly plotting pattern on wafer and their design rule confirming method | |
| CN113168494A (en) | Method and system for Integrated Circuit (IC) layout migration for integrating professional layout design experience | |
| CN101593456A (en) | A kind of quick self-adaptive layout method of The Key to Maps | |
| US20160267204A1 (en) | Management of placement constraint regions in an electronic design automation (eda) system | |
| US20030003375A1 (en) | Block mask making method, block mask and exposure apparatus | |
| US10474038B2 (en) | Method, system, and storage medium for resolving coloring conflict in multi-patterning lithography | |
| CN116050340B (en) | Automatic layout method and device for pins in layout design and related products | |
| Yan et al. | BSG-route: A length-constrained routing scheme for general planar topology | |
| Viswanathan et al. | Fastplace: an analytical placer for mixed-mode designs | |
| CN112489057A (en) | Traffic sign data processing method, electronic device and storage medium | |
| CN112163552A (en) | Labeling method and device for key points of nose, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HUSHI ELECTRICITY STOCK CO., LTD. Free format text: FORMER OWNER: HUAWEI TECHNOLOGY CO., LTD. Effective date: 20090731 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090731 Address after: No. 55, Heilongjiang North Road, Kunshan, Jiangsu Patentee after: Wus Printed Circuit Co.,Ltd. Address before: Bantian HUAWEI headquarters office building, Longgang District, Shenzhen, Guangdong Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |
|
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Wus Printed Circuit Co.,Ltd. Assignor: HUAWEI TECHNOLOGIES Co.,Ltd. Contract fulfillment period: 2009.4.26 to 2015.4.26 Contract record no.: 2009320001055 Denomination of invention: Method for automatic generating device mark in printed circuit board design Granted publication date: 20071003 License type: Exclusive license Record date: 20090706 |
|
| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2009.4.26 TO 2015.4.26; CHANGE OF CONTRACT Name of requester: HUSHI ELECTRICITY STOCK CO., LTD. Effective date: 20090706 |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20071003 |
|
| DD01 | Delivery of document by public notice | ||
| DD01 | Delivery of document by public notice |
Addressee: Zhang Shanshan Document name: Notice of Termination of Patent Rights |