WO2022266906A1

WO2022266906A1 - Method and apparatus for generating layout of integrated circuit

Info

Publication number: WO2022266906A1
Application number: PCT/CN2021/101916
Authority: WO
Inventors: 李定; 胡贻升; 李进朋; 陈培杰
Original assignee: 华为技术有限公司
Priority date: 2021-06-23
Filing date: 2021-06-23
Publication date: 2022-12-29
Also published as: CN117321601A

Abstract

The present application relates to the technical field of electronics, and provides a method and apparatus for generating a layout of an integrated circuit, used for reducing manual participation in a layout design process of an integrated circuit, and realizing automation of layout design of the integrated circuit. The method comprises: obtaining parameter information of a plurality of basic components comprised in a schematic circuit diagram, wherein the basic components may be obtained by means of unified packaging processing; determining, according to the parameter information, a plurality of component layouts corresponding to the plurality of basic components, that is, obtaining specific shapes and sizes of the plurality of basic components in a layout of an integrated circuit; obtaining relative layout information of the plurality of component layouts, and determining physical location information of the plurality of component layouts according to the relative layout information and the plurality of component layouts, for example, determining coordinates of each component layout in the plurality of component layouts; and generating, according to the physical location information, the layout of the integrated circuit corresponding to the schematic circuit diagram.

Description

A layout generation method and device for an integrated circuit

technical field

The present application relates to the field of electronic technology, and in particular to a method and device for generating an integrated circuit layout.

Background technique

The layout design of integrated circuits is an essential link in the manufacture of integrated circuits. It is not only related to whether the functions of integrated circuits are correct, but also greatly affects the performance, cost and power consumption of integrated circuits. The layout design process of traditional integrated circuits usually includes: the designer generates the layout of the corresponding device in the design software of the integrated circuit such as electronic design automation (electronic design automation, EDA) according to the circuit schematic diagram; The connection relationship of the device is manually placed and wired; after multiple physical verification (PV), post-simulation verification and adjustment, the final layout is obtained. However, this design process is time-consuming and inefficient.

In order to improve the efficiency of layout design, a layout design method is provided in the prior art, specifically, through the induction and analysis of the layout of existing integrated circuits, the type of published diagram, the adjustable parameter interface and layout of the corresponding type are determined. Design logic, etc., based on the above information, parameterize the layout or specific wiring of some specific cells in the circuit to form a parameterized cell (parameter cell, PCell) with a parameter interface. When using these PCells, the user only needs to use the PCell Enter the corresponding parameters in the parameter interface to generate a layout with a fixed type and a fixed drawing method.

However, this method can only be applied to layouts with relatively simple design logic, and PCells of different units can only be designed according to a specific process, so the reuse rate is low. In addition, the above-mentioned design process requires a lot of manual participation, and requires relatively high software capabilities of designers.

Contents of the invention

The present application provides a method and device for generating a layout of an integrated circuit, which relate to the field of electronic technology and are used to reduce manual participation in the layout design process of an integrated circuit and realize automation of the layout design of an integrated circuit.

In the first aspect, a method for generating a layout of an integrated circuit is provided. The method includes: obtaining parameter information of a plurality of basic components included in the schematic circuit diagram, the basic components may be obtained through unified packaging, and the basic components It can include basic electronic components such as inductors, resistors, and transistors used to design or form circuits, and can also include components composed of two or more basic electronic components. The parameter information can include process parameter information and Electrical parameter information; determine the multiple device layouts corresponding to the multiple basic components according to the parameter information, that is, obtain the specific shape and size of the multiple basic components in the integrated circuit layout; obtain the relative layout of the multiple device layouts Information, the relative layout information may include the relative position information of any one or more device layouts in the multiple device layouts in the integrated circuit layout; according to the relative layout information and the multiple device layouts, generate a routing-free The layout of the integrated circuit, to determine the physical location information of the multiple device layouts, for example, to determine the coordinates of each device layout in the multiple device layouts; according to the physical location information, generate the integrated circuit corresponding to the circuit schematic diagram Layout, for example, routing is performed on the layout of the integrated circuit without traces to obtain the final layout of the integrated circuit.

In the above technical solution, after the electronic device obtains the process parameter information and electrical parameter information of the multiple basic components included in the circuit schematic diagram, it can determine the multiple components corresponding to the multiple basic components according to the process parameter information and electrical parameter information. A device layout, and then based on the relative layout information of the multiple device layouts, determine the physical location information of the multiple device layouts, and complete the wiring between different device layouts according to the physical location information to generate the corresponding integration of the circuit schematic diagram The layout of the circuit, that is, the automation of the layout design of the integrated circuit is realized. During this process, the user can input the relative layout information of the multiple device layouts according to actual needs, that is, in the process of automatic design of the layout of the integrated circuit, the designer can carry out the overall layout of the layout of the integrated circuit without spending A lot of time is spent on manual layout and routing, etc., so as to solve the problem of long labor time in layout design.

In a possible implementation manner of the first aspect, determining the multiple device layouts corresponding to the multiple basic components according to the parameter information includes: for the first basic component among the multiple basic components, according to the The parameter information of the first basic component, the model device corresponding to the first basic component is instantiated into a device layout, the first basic component is any one of the multiple basic components, the first The model device corresponding to the basic component is obtained by uniformly packaging the first basic component. In the above possible implementation, according to the parameter information of the first basic component, the device layout of the first basic component can be obtained by instantiating the model device corresponding to the first basic component into a device layout, thereby improving Improves the efficiency of generating device layouts for basic components.

In a possible implementation manner of the first aspect, the method further includes: according to the first basic component, acquiring a model component corresponding to the first basic component from a preset model component library, the preset model component The library includes multiple model devices. The multiple model devices can be obtained by uniformly packaging multiple different basic units in advance. For example, the multiple model devices can be the basic components provided by different processes and different chip foundries. Units are packaged in a unified manner, and the multiple different basic units include the first basic component. In the above possible implementation, the multiple model devices are obtained by performing unified packaging on multiple different basic units. The unified packaging can shield the differences between different processes and different chip foundries, and can provide unified The input and output interface, so that the device based on this model can be applied to the product requirements of different processes and different chip foundries.

In a possible implementation manner of the first aspect, determining the multiple device layouts corresponding to the multiple basic components according to the parameter information includes: for the second basic component among the multiple basic components, according to the For the parameter information of the second basic component, the device layout of the second basic component is obtained from the device layout library. For example, the second basic component is an inductor, and the process parameter information of the inductor is TSMC28 or SMC28, and the electrical parameter information is If the length is equal to L and the width is equal to W, then the device layout of the inductance that satisfies the above parameter information can be directly used as the device layout of the second basic component by searching the device layout library from the device layout library. The device layout library includes at least one of the basic units. The device layout of each basic unit under at least one set of parameter information, the device layout included in the device layout library may be obtained by collecting one or more user-generated device layouts, the second basic component is the multiple basic For any basic component in the components, the at least one basic unit includes a second basic component. In the above possible implementation, the second basic component can be directly used as the second basic component by querying the device layout in the previously collected device layout, without generating parameter information, so that the reuse rate of the previously generated device layout can be improved. Therefore, the generation efficiency of the layout of the integrated circuit is improved.

In a possible implementation manner of the first aspect, determining the physical location information of the multiple device layouts according to the relative layout information and the multiple device layouts includes: according to the relative layout information and the multiple device layouts Dimensions, the multiple device layouts are laid out to obtain the physical location information of the multiple device layouts, and the physical location information can be used to generate the layout of the integrated circuit without wiring. The coordinate information of each device layout when the size of the device layout satisfies the above relative layout information is laid out, and the layout of the integrated circuit without wiring can be generated by laying out the multiple device layouts based on the coordinate information. In the above possible implementation, the user can input the relative layout information of the multiple device layouts according to the actual needs, that is, the designer can carry out the overall layout of the layout of the integrated circuit, and the subsequent electronic equipment can automatically generate an integrated circuit that satisfies the relative layout information layout, thereby greatly reducing the amount of manual parameters and improving the efficiency of layout generation.

In a possible implementation manner of the first aspect, laying out the multiple device layouts according to the relative layout information and the sizes of the multiple device layouts includes: according to the relative layout information, the dimensions of the multiple device layouts Size and at least one constraint condition, layout the multiple device layouts, the at least one constraint condition includes one or more of the following conditions: minimum area constraint, minimum distance constraint, current relationship between different device layouts or Distance relationship; wherein, the minimum area constraint may refer to the minimum area required by the layout of the final integrated circuit, that is, the area occupied by the layout of the integrated circuit is at least the area required by the minimum area constraint, and the layout of the integrated circuit The occupied area cannot be smaller than the area required by the minimum area constraint; the minimum distance constraint can refer to the minimum distance between any two adjacent device layouts, that is, the minimum distance between two adjacent device layouts is the The distance required by the minimum distance constraint, the distance between the two adjacent device layouts cannot be smaller than the distance required by the minimum distance constraint; the current relationship between different device layouts can refer to the current flowing through the different device layouts For example, the current flowing through certain two device layouts is equal; the distance relationship can refer to the distance relationship between different device layouts, for example, the distance relationship can be used to indicate the minimum distance between certain two device layouts or max distance etc. In the above possible implementation manners, when laying out the multiple device layouts, other constraint conditions of the layout of the integrated circuit can be further synthesized, so that the layout of the generated integrated circuit can meet the above constraints, thereby reducing the subsequent The time spent by the user on checking and correcting the layout of the integrated circuit further reduces the length of manual participation.

In a possible implementation manner of the first aspect, generating the layout of the integrated circuit corresponding to the circuit schematic diagram according to the physical location information includes: according to the circuit connection relationship in the circuit schematic diagram, the physical location information corresponding Routing is performed in the integrated circuit layout without traces, so as to generate the layout of the integrated circuit corresponding to the circuit schematic diagram. In the above possible implementation mode, the wiring can be automatically carried out in the layout of the integrated circuit without wiring according to the circuit connection relationship in the circuit schematic diagram, so that the designer does not need to spend a lot of time on manual wiring, thereby reducing the layout. Design is labor time consuming.

In a possible implementation manner of the first aspect, according to the circuit connection relationship in the circuit schematic diagram, performing wiring on the layout of the integrated circuit corresponding to the physical position information without wiring includes: obtaining at least one wiring The wiring information, the at least one wiring is a wiring in the layout of the integrated circuit corresponding to the circuit schematic diagram, the wiring information may include wiring path information, wiring width constraint information, etc., and the at least one wiring may affect the The routing in the working index of the integrated circuit, which may include but not limited to one or more of frequency, phase noise, amplitude fluctuation, power consumption, and bandwidth; according to the circuit connection in the circuit schematic diagram relationship and the routing information of the at least one routing, and routing is performed in an integrated circuit layout that does not contain routings corresponding to the physical location information. In the above possible implementation manners, the user can plan one or more routings in the layout of the integrated circuit by inputting routing information according to actual needs, so as to meet the user's special needs for some routings in the layout of the integrated circuit, thereby improving Flexibility in the generation of layouts for integrated circuits.

In a possible implementation manner of the first aspect, the relative layout information includes relative position information between projections of at least two device layouts in the same metal layer among the plurality of device layouts, for example, through the relative layout information Set the positions of two or more device layouts in the same metal layer that have a certain relationship between current and voltage; and/or, the relative layout information also includes the position of the metal layer where at least two device layouts are located in the multiple device layouts Relative level information among them, for example, through the relative layout information, the positions of two or more device layouts that have a certain current-voltage relationship in different metal layers are set. In the above possible implementation manner, the relative layout information is used to set the positions of two or more device layouts that have a certain relationship among the multiple device layouts, which can improve the performance of the layout of the integrated circuit while reducing the subsequent generation The complexity of the layout of an integrated circuit.

In a possible implementation manner of the first aspect, obtaining parameter information of multiple basic components included in the schematic circuit diagram includes: first, the user inputs process parameter information of the multiple basic components according to actual needs, and the electrical parameter information of each of the multiple basic components; the second type, based on user triggers, obtains the process parameter information of the multiple basic components from the circuit schematic diagram, and the multiple The electrical parameter information of each basic component in the basic components; third, the user inputs the process parameter information of the multiple basic components according to actual needs, and obtains the multiple basic components from the circuit schematic diagram based on the user's trigger The electrical parameter information of each basic component in the basic component. In practical applications, electrical parameter information and the like of some basic components can also be obtained through any of the above three methods.

In the second aspect, there is provided a layout generation device for an integrated circuit, the device includes: an acquisition unit, configured to acquire parameter information of a plurality of basic components included in the schematic circuit diagram, and the basic components may be obtained through a unified packaging process , the basic components may include basic electronic components such as inductors, resistors, and transistors for designing or forming circuits, or components composed of two or more basic electronic components, and the parameter information may be Including process parameter information and electrical parameter information; the processing unit is used to determine the multiple device layouts corresponding to the multiple basic components according to the parameter information, that is, to obtain the specific shape and size of the multiple basic components in the integrated circuit layout The obtaining unit is also used to obtain relative layout information of the multiple device layouts, the relative layout information may include relative position information of any one or multiple device layouts in the multiple device layouts in the integrated circuit layout; the The processing unit is further configured to determine the physical location information of the multiple device layouts according to the relative layout information and the multiple device layouts, for example, determine the coordinates of each device layout in the multiple device layouts; the processing unit is also It is used to generate the layout of the integrated circuit corresponding to the schematic circuit diagram according to the physical position information, for example, perform wiring on the layout of the integrated circuit without wiring, so as to obtain the final layout of the integrated circuit.

In a possible implementation manner of the second aspect, the processing unit is further configured to: for the first basic component among the plurality of basic components, according to the parameter information of the first basic component, the first basic component The model device corresponding to the basic components is instantiated into a device layout, and the first basic component is any one of the multiple basic components.

In a possible implementation manner of the second aspect, the processing unit is further configured to: acquire a model device corresponding to the first basic component from a preset model device library according to the first basic component, and the preset The model device library includes multiple model devices, which are obtained by uniformly packaging multiple different basic units. For example, the multiple model devices can be basic components provided by different processes and different chip foundries Units are packaged in a unified manner, and the multiple different basic units include the first basic component.

In a possible implementation manner of the second aspect, the processing unit is further configured to: for a second basic component among the plurality of basic components, according to the parameter information of the second basic component, the slave layout library Obtain the device layout of the second basic component, for example, the second basic component is an inductor, the process parameter information of the inductor is TSMC28, and the electrical parameter information is that the length is equal to L and the width is equal to W, then it can be obtained from the device version The device layout of the inductance that meets the above parameter information is found in the library directly as the device layout of the second basic component, and the device layout library includes the device layout of each basic unit in at least one basic unit under at least one set of parameter information, The device layout included in the device layout library may be obtained by collecting one or more user-generated device layouts, the second basic component is any one of the multiple basic components, and the at least one basic unit Including the second basic component.

In a possible implementation manner of the second aspect, the processing unit is further configured to: layout the multiple device layouts according to the relative layout information and the sizes of the multiple device layouts, so as to obtain the multiple device layouts The physical position information can be used to generate the layout of the integrated circuit without wiring, for example, when the layout of each device layout satisfying the above-mentioned relative layout information is performed according to the size of the above-mentioned multiple device layouts through correlation algorithms. Coordinate information, layout of the multiple device layouts based on the coordinate information can generate a layout of an integrated circuit without traces.

In a possible implementation manner of the second aspect, the processing unit is further configured to: layout the multiple device layouts according to the relative layout information, the size of the multiple device layouts, and at least one constraint condition, the The at least one constraint condition includes one or more of the following conditions: minimum area constraint, minimum distance constraint, current relationship or distance relationship between different device layouts.

In a possible implementation manner of the second aspect, the processing unit is further configured to: perform wiring in an integrated circuit layout corresponding to the physical position information without wiring according to the circuit connection relationship in the circuit schematic diagram, To generate the layout of the integrated circuit corresponding to the circuit schematic diagram.

In a possible implementation manner of the second aspect, the processing unit is further configured to: acquire routing information of at least one routing, where the at least one routing is a routing in the layout of the integrated circuit corresponding to the circuit schematic diagram, The routing information may include routing path information, routing width constraint information, etc., and the at least one routing may be a routing that affects the working index of the integrated circuit, and the operating index may include but not limited to frequency, phase noise, amplitude According to the circuit connection relationship in the circuit schematic diagram and the wiring information of the at least one wiring, the integrated circuit without wiring corresponding to the physical location information Wiring in layout.

In a possible implementation manner of the second aspect, the relative layout information includes relative position information between projections of at least two device layouts in the same metal layer among the plurality of device layouts, for example, through the relative layout information Set the positions of two or more device layouts in the same metal layer that have a certain current-voltage relationship; and/or, the relative layout information also includes the metal layer where at least two device layouts among the multiple device layouts are located The relative level information among them, for example, through the relative layout information, the positions of two or more device layouts that have a certain current-voltage relationship in different metal layers are set.

In a possible implementation of the second aspect, the acquisition unit is further configured to: receive the process parameter information of the plurality of basic components input by the user, and the electrical parameters of each basic component in the plurality of basic components. Parameter information; or, based on user triggers, obtain the process parameter information of the plurality of basic components and the electrical parameter information of each basic component in the plurality of basic components from the schematic circuit diagram; or, receive The process parameter information of the plurality of basic components input by the user, and the electrical parameter information of each basic component in the plurality of basic components are acquired from the schematic circuit diagram based on the trigger of the user. In practical applications, the acquiring unit can also acquire electrical parameter information of some basic components and the like through any one of the above three ways.

In yet another aspect of the present application, an integrated circuit layout generation device is provided, the device includes a processor and a memory, the memory stores instructions, the processor runs the instructions in the memory, so that the device executes the above-mentioned first A layout generation method for an integrated circuit provided in one aspect or in any possible implementation manner of the first aspect.

In yet another aspect of the present application, a computer-readable storage medium is provided. Instructions are stored in the computer-readable storage medium. When the instructions are run on a device, the device executes the above-mentioned first aspect or the first aspect. A layout generation method for an integrated circuit provided in any possible implementation manner.

In yet another aspect of the present application, a computer program product is provided. When the computer program product runs on a device, the device executes the integrated Circuit layout generation method.

It should be understood that, for the beneficial effects of any one of the integrated circuit layout generation device, computer-readable storage medium, and computer program product provided above, reference may be made to the beneficial effects of the method provided in the corresponding aspect above, and details will not be repeated here. .

Description of drawings

Fig. 1 is the flowchart of the layout design of a kind of traditional integrated circuit;

Fig. 2 is a schematic flow chart of refining and generating PCell;

FIG. 3 is a schematic flowchart of a layout generation method for an integrated circuit provided in an embodiment of the present application;

FIG. 4 is a schematic circuit diagram of a digitally controlled oscillator provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of a model device and a device layout provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of relative layout information of a plurality of device layouts provided by an embodiment of the present application;

FIG. 7 is a flow chart of layout design of an integrated circuit provided in an embodiment of the present application;

FIG. 8 is a layout of an integrated circuit of a digitally controlled oscillator provided in an embodiment of the present application;

FIG. 9 is a schematic structural diagram of an integrated circuit layout generation device provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another integrated circuit layout generation device provided by an embodiment of the present application.

detailed description

In this application, "at least one" means one or more, and "multiple" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (unit) of a, b or c can represent: a, b, c, a-b, a-c, b-c or a-b-c, wherein a, b and c can be single or multiple. The character "/" generally indicates that the contextual objects are an "or" relationship. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and execution order.

It should be noted that, in this application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "for example" is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

Before introducing the embodiments of the present application, firstly, the related technical background of the layout design of the integrated circuit involved in the present application will be described.

Among them, the layout design of the integrated circuit is an essential link in the production of the integrated circuit. It is not only related to whether the function of the integrated circuit is correct, but also greatly affects the performance, cost and power consumption of the integrated circuit. As shown in Figure 1, the layout design process of a traditional integrated circuit usually includes: the designer generates the layout of the corresponding device in integrated circuit design software such as electronic design automation (electronic design automation, EDA) according to the circuit schematic diagram; Perform manual layout and wiring according to the connection relationship of different devices in the circuit schematic diagram; perform physical verification (Physical verify, PV) on the initially generated layout, and return to the steps of manual layout and wiring if the PV fails (for example, adjust the layout and connection), if the PV passes the post-simulation verification, for example, the post-simulation verification can use spice simulators, parasitic parameter extraction tools, etc.; if the post-simulation verification passes, the final layout will be obtained; if the post-simulation verification fails, then Return to the steps of manual layout and wiring and re-execute until both PV and post-simulation verification pass. Among them, in the process of manual layout and wiring, PV and post-simulation verification, it can be carried out according to the foundry's process design kit (PDK) and process design constraints.

However, as the process size becomes smaller and smaller, chip foundries require more and more layout design rules, and the design rules that need to be satisfied become more and more complex. Common design rules such as: minimum distance constraints, Metal width constraints, etc. Therefore, layout engineers need to spend a lot of practice, through non-stop PV, post-simulation verification, and adjusting the layout and wiring of the layout, in order to pass the design rule checking (design rule checking, DRC) and layout schematic comparison ( layout versus schematic, LVS) verification. This layout design process is very time-consuming and inefficient; in addition, when the process adjustment or circuit design parameters change greatly, the original layout layout will no longer be applicable, and it is necessary to re-layout and route, etc., so that the entire design process Reusability is low.

At present, some electronic design automation (EDA) software (such as Cadence's PCell Designer tool) can provide a graphical interface for parameterized cell (PCell) design and relatively rich design interfaces, and PCell design can be more convenient Parameterize some specific layout or specific wiring, and finally generate a customized PCell. When users are using these PCells, they only need to input corresponding parameters through the parameter interface of PCells to generate layouts with fixed types and fixed drawing methods. Exemplarily, as shown in FIG. 2 , it is a schematic flow chart of extracting and generating PCell provided by the embodiment of the present application, which may specifically include: summarizing and analyzing the layout of existing integrated circuits by PCell designers, and extracting the published map type; refine and define adjustable parameter interfaces according to the type of layout; refine the design logic of the published diagram; design and generate a modular PCell based on the design logic; Parameterized to form a PCell with a parameterized interface. When designing and generating a modularized PCell, it is necessary to use a PCell design tool, and design on the design interface through the module calling components, logic components, and computing components in the tool.

However, this method can only be applied to layouts with relatively simple design logic, but not to layouts with more complex design logic. This is because it is difficult for designers to analyze and summarize layouts with more complex design logic in the early stage. Therefore, it is impossible to accurately extract the type of publication diagram for subsequent design. In addition, the above-mentioned PCells of different units can only be designed according to a specific process. Once the process is switched, it is necessary to regenerate the PCells of the corresponding process, so the reuse rate is low. In addition, the above-mentioned design process requires a lot of manual participation, and requires relatively high software capabilities of designers. The design process is customized and the degree of reuse is very low. It is impossible to continuously improve design capabilities and efficiency through design accumulation.

Based on this, the embodiment of the present application provides a layout generation method and device for an integrated circuit, which can enable layout designers to focus more on the overall layout and various physical effects without spending a lot of time on manual layout and wiring, DRC or LVS In terms of corrections, it solves the problems of long time-consuming layout design and low design reuse rate.

Figure 3 is a schematic flowchart of a method for generating an integrated circuit layout provided by an embodiment of the present application, the method can be used to generate a layout (layout) of an integrated circuit corresponding to a schematic circuit diagram, and the method can be executed by an electronic device Specifically, it can be executed through EDA software installed on the electronic device, and the method includes the following steps.

S301: Obtain parameter information of a plurality of basic components included in the schematic circuit diagram.

Wherein, the circuit schematic diagram may refer to a circuit diagram used to represent the structure and working principle of the circuit, and the circuit schematic diagram may be generated by using EDA software, and each basic component in the circuit schematic diagram may be represented by a corresponding basic component symbol To indicate that each basic component may have corresponding component information, for example, the component information may include the identification and parameter information of the component. The basic components may include basic electronic components used to design or form circuits, or components composed of two or more basic electronic components. For example, the basic components may include resistors (such as ordinary resistors, photoresistors, thermistors, piezoresistors, humidity-sensitive resistors, variable resistors), inductors, capacitors (such as fixed capacitors, variable capacitors, semi-variable Variable capacitance), diodes (for example, ordinary diodes, light-emitting diodes, Zener diodes, photodiodes), transistors (for example, N-type transistors, P-type transistors), switches and connectors (for example, pin headers, row seats, terminal blocks ), etc., may also include components composed of two or more of the above-mentioned electronic components. The circuit schematic diagram includes a plurality of basic components, and the multiple basic components may include a plurality of different basic components, and there may also be the same basic components, and these basic components may be included in the circuit schematic diagram Structural information to distinguish or identify.

Exemplarily, as shown in FIG. 4 , it is assumed that the circuit schematic diagram is a circuit schematic diagram of a digitally controlled oscillator, and the circuit schematic diagram includes three basic components, specifically an inductor, an adjustable capacitor module and a negative resistance module. Wherein, the inductor is a basic electronic component, and the adjustable capacitor module is composed of two adjustable capacitors (for example, a group-sized adjustable capacitor C1 and a fine-grained adjustable capacitor C2, each adjustable capacitor can include A basic component composed of multiple basic electronic components, such as multiple capacitors and transistors, etc.), the negative resistance module is a basic component composed of two transistors M1 and M2 (each transistor can be a basic electronic component) components. The structural information of the schematic circuit diagram can be used to indicate the above three basic components and the basic electronic components included in each basic component.

In addition, the parameter information may include process parameter information and electrical parameter information. The plurality of basic components share the same process parameter information, and the process parameter information can be determined by the layout designer according to actual needs. For example, the process parameter information of the multiple basic components can be TSMC (Taiwan semiconductor manufacturing company, TSMC) 28nm (TSMC 28 for short), TSMC 16 or SMC 28 (nm), etc. The electrical parameter information includes the electrical parameter information of the multiple basic components, and the electrical parameter information of different basic components in the multiple basic components may be different. For example, the multiple basic components include resistors and transistors, and the multiple basic components include resistors and transistors. The electrical parameter information of the resistor may include the resistance value, and the electrical parameter information of the transistor may include the width and length of the channel.

Exemplarily, taking the circuit schematic diagram of the digitally controlled oscillator shown in FIG. 4 as an example, among the three basic components included in the circuit schematic diagram, the inductor, the adjustable capacitance module and the negative resistance module The process parameter information can be TSMC28, the electrical parameter information of the inductor can include the trace width of the inductor, the electrical parameter information of the adjustable capacitor module can include the number of adjustable capacitors, the width and length of a single adjustable capacitor, the negative The electrical parameter information of the resistor module may include the number of rows and columns of transistors, and the width and length of transistor channels.

Specifically, when the user needs to generate the layout of the integrated circuit corresponding to the circuit schematic diagram, the electronic device can obtain the process parameter information and electrical parameter information of the multiple basic components in the following ways: first, the user can obtain the information according to According to actual needs, input the process parameter information of the multiple basic components and the electrical parameter information of each basic component in the multiple basic components to the electronic equipment; The process parameter information of the multiple basic components and the electrical parameter information of each basic component in the multiple basic components are obtained in the schematic diagram; third, the user can input the electronic equipment according to actual needs. process parameter information of a plurality of basic components, and trigger the electronic device to acquire electrical parameter information of each basic component in the plurality of basic components from the schematic circuit diagram. In practical applications, electrical parameter information and the like of some basic components may also be obtained through any of the above three methods, which is not specifically limited in this embodiment of the present application.

S302: According to the parameter information, multiple model devices corresponding to the multiple basic components are instantiated into multiple device layouts, and the multiple model devices are obtained by performing unified packaging processing on the multiple basic components respectively.

Wherein, the plurality of basic components corresponds to the plurality of model devices one by one, that is, each basic component in the plurality of basic components corresponds to a model device. When the multiple basic components include multiple different basic components, the multiple model components included in the multiple model components are also different. When the same basic component exists in the plurality of basic components, the model devices corresponding to the same basic component are also the same.

In addition, the model device can be a device formed after the basic unit is uniformly packaged, and the basic unit can include basic components provided by the same chip foundry or different chip foundries, so the basic unit can also be called a basic component , hereinafter collectively referred to as basic components. The unified packaging process here can specifically include the unified packaging of the input and output interfaces of the basic components, and the unified naming of the electrical parameters and types of the basic components. The naming and type division of the corresponding basic components of other chip foundries and the division of types. That is, the model devices corresponding to the same basic components provided by different chip foundries provide consistent device parameters and consistent input and output interfaces on the basis of shielding differences between different processes and different chip foundries ( Or called external connection interface), consistent device performance, and electrical parameter access interface, so as to solve the DRC problem at the device level, and provide standardized input and output interfaces to decouple the device from the process. For example, taking the naming of the width of the channel of the transistor as an example, some chip foundries name it width, and some chip foundries name it nfin. In this application, the width of the channel of the transistor can be uniformly named width .

Furthermore, the plurality of model devices having consistent input and output interfaces may mean that the input and output interfaces of each model device in the plurality of model devices are uniformly packaged according to the same standard or design specification, and the obtained after package processing The input and output interfaces of any two model devices in multiple model devices can be directly connected without other processing. For example, the same standard or design specification may require that the boundary of the input and output interfaces of each model device can be directly Used to connect with the input and output interfaces of other model devices, the length of the input and output interfaces of each model device is greater than or equal to the preset length threshold, and/or the width of the input and output interfaces of each model device is greater than or equal to the preset width threshold Wait. The foregoing standards and design specifications may be specifically determined according to DRC design rules, characteristics of different devices, and characteristics of different processes, which are not specifically limited in this embodiment of the present application. In addition, for different processes of the same basic component, the corresponding model devices may be consistent. For example, the port names, numbers and connection methods of the same basic component in different processes are the same.

Exemplarily, taking a transistor as an example, for the same p-type (p-type) core (core) tube, the unified naming or name can be pch_mac, and the corresponding parameter information list can include the length l and width of the channel w and the number of unit repetitions m, the corresponding input and output interfaces can include source S, drain D, gate G and body B, and the connection method can be that S and D are connected to the second metal layer and routed horizontally, G Connect to the first metal layer and unify the lateral traces.

Specifically, when the electronic device obtains the parameter information, that is, obtains the process parameter information and the electrical parameter information of each basic component in the plurality of basic components, for each model device in the plurality of model devices , the electronic device can instantiate the model device into a device layout according to the process parameter information and the electrical parameter information of the basic components corresponding to the model device, that is, obtain the specific shape and size of the device layout, etc., so that the multiple A model device can correspond to multiple device layouts.

Exemplarily, take the working schematic diagram of the digitally controlled oscillator shown in FIG. As shown in (a) and (b) in FIG. 5 respectively, the model device of the adjustable capacitor module can be shown in (c) in FIG. 5 , and the corresponding device layout is not shown for the adjustable capacitor module. Wherein, the device layout of the inductor can be a polygon; the device layout of the negative resistance module includes two transistors, S1, G1 and D1 can be the source, gate and drain of the first transistor M1 respectively, and S2, G2 and D2 can be the source, gate and drain of the second transistor M2 respectively, and the first transistor M1 and the second transistor can be realized through the through-hole wiring set on S1, G1, D1, S2, G2 and D2 Corresponding connection of M2.

Further, the plurality of model devices may be obtained from a model device library, the model device library may be preset, and the model device library may include a plurality of different model devices, and the plurality of different model devices Each model device in corresponds to a basic component, that is, each model device is a model device of the corresponding basic component. For example, as shown in Table 1 below, the model device library may include identifications of multiple basic components and parts, which are respectively represented as ID1 to IDn, and a plurality of different model devices, which are respectively represented as Model-1 to Model-n, ID1 to IDn corresponds to Model-1 to Model-n one by one, and n is an integer greater than 1.

Table 1

基本元器件的标识Identification of basic components	模型器件model device
ID1ID1	Model-1Model-1
ID2ID2	Model-2Model-2
……...	……...
IDnID	Model-nModel-n

Specifically, before instantiating the multiple model devices into multiple device layouts according to the parameter information, the method may further include: for each basic component in the multiple basic components, according to the basic component from The corresponding model devices are obtained from the model device library, so that the multiple basic components correspond to the multiple model devices. For example, for each basic component, according to the identification of the basic component, the model component corresponding to the identification is obtained from the model component library, that is, the model component corresponding to the basic component is obtained.

Optionally, when obtaining the parameter information of the multiple basic components, the electronic device may first query the device layout sample library according to the parameter information of the multiple basic components, and the device layout sample library stores a large number of Device layout, the device layout in the device layout sample library can be obtained by collecting device layouts generated by different users. Specifically, for each basic component in the plurality of basic components, the device layout sample library can be queried according to the parameter information of the basic component, if there is a component in the layout sample library that satisfies the parameter information of the basic component device layout, the device layout can be determined as the device layout of the basic component. If there is no device layout satisfying the parameter information of the basic component in the layout sample library, the device layout of the basic component can be generated according to the description of S302 above; further, the electronic device can also store the generated layout device In this device layout sample library, it is convenient for subsequent use or other users.

S303: Obtain relative layout information of the multiple device layouts, and determine physical location information of the multiple device layouts according to the relative layout information and the multiple device layouts.

Wherein, the relative layout information may refer to the relative layout information of the plurality of device layouts in the layout of the integrated circuit corresponding to the circuit schematic diagram. The relative layout information may include relative position information between any two device layouts in the plurality of device layouts, or the relative position of any one device layout, etc., and the relative position information may include between the metal layers where the two device layouts are located. The relative relationship between the two device layouts, the relative position between the projections of the two device layouts in the same metal layer, and the relative position of any one device layout in the layout of the integrated circuit, etc. For example, taking the two device layouts as A and B as an example, the relative layout information can be used to indicate that the metal layer where A is located is located above the metal layer where B is located, and the projection of A on the metal layer where B is located is located at B on the left side. Exemplarily, taking the circuit schematic diagram of the digital oscillator shown in FIG. 4 as an example, the relative layout information of the device layout corresponding to the inductor, the adjustable capacitance module and the negative resistance module can be shown in FIG. The device layout of the resistance module can be located between the device layout of the inductor and the device layout of the adjustable capacitor module, that is, the projections of the three basic components on the same metal layer are the device layout of the inductor, the The device layout of the negative resistance module and the device layout of the adjustable capacitor module.

In addition, the physical position information of the plurality of device layouts refers to the physical position information of the plurality of device layouts in the layout of the integrated circuit corresponding to the circuit schematic diagram. The physical location information may be used to indicate the physical location of each device layout in the plurality of device layouts. The physical location of a device layout may include the metal layer where each device layout in the plurality of device layouts is located, and where the device layout is located. Coordinate positions in the metal layer, etc.

Specifically, the electronic device may acquire the relative layout information of the plurality of device layouts in the following ways: first, the user may input the relative layout information of the plurality of device layouts into the electronic device according to actual needs Information; the second type, the user triggers the electronic device to obtain the relative layout information of the multiple device layouts from the circuit schematic diagram; the third type, the user can input the multiple device layout information to the electronic device according to actual needs the relative layout information of a part of the device layout, and trigger the electronic device to obtain the relative layout information of another part of the device layout in the plurality of device layouts from the circuit schematic diagram. Optionally, when the user inputs the relative layout information of the plurality of device layouts to the electronic device, the user may use the container component provided by the electronic device for setting the relative layout for input, for example, in the graphics of the electronic device In the user interface, the plurality of device layouts can be displayed as a plurality of square thumbnails, and the container component can be located in the main interface, and the container component can include horizontal arrangement, vertical arrangement, array arrangement and A variety of container components surround, the user only needs to select the corresponding container component, and drag the device layout that needs to set the relative layout relationship to the corresponding position in the container component. It should be noted that the step of obtaining the relative layout information and the above steps of S301 and S302 may be partially sequenced, and this step only needs to be done before determining the physical location information of the multiple device layouts. Take this as an example.

After obtaining the relative layout information, the electronic device can layout the multiple device layouts according to the relative layout information to obtain the layout of the integrated circuit without wiring, that is, to obtain the physical location information of the multiple device layouts . Wherein, when the electronic device lays out the multiple device layouts, in addition to the relative layout information, it can also combine other constraints (for example, the minimum area constraint and the minimum distance constraint in the process constraints, and the distance between different device layouts). current relationship and distance relationship, etc.), the physical position information is determined by automatic synthesis to layout the multiple device layouts. Optionally, the electronic device can automatically synthesize the relative layout information, and one or more of constraints such as the minimum area constraint and the minimum distance constraint, and continuously adjust different device layouts (for example, in the bottom metal layer) during the synthesis process. The physical location information of the multiple device layouts is obtained through the annealing algorithm; the multiple device layouts are laid out according to the physical location information to obtain the layout of the integrated circuit without wiring.

It should be noted that the minimum area constraint may refer to the minimum area required by the layout of the final integrated circuit, that is, the area occupied by the layout of the integrated circuit is at least the area required by the minimum area constraint, and the layout of the integrated circuit The occupied area cannot be smaller than that required by this minimum area constraint. The minimum distance constraint may refer to the minimum distance between any two adjacent device layouts, that is, the minimum distance between two adjacent device layouts is the distance required by the minimum distance constraint, and the two adjacent The distance between device layouts cannot be smaller than that required by this minimum distance constraint. The current relationship between different device layouts may refer to the magnitude relationship of the currents flowing through the different device layouts, for example, the currents flowing through certain two device layouts are equal. The above-mentioned distance relationship may refer to a distance relationship between different device layouts, for example, the distance relationship may be used to indicate a minimum distance or a maximum distance between certain two device layouts.

Optionally, when acquiring the relative layout information and the plurality of device layouts, the electronic device may first query the circuit layout sample library according to the relative layout information and the plurality of device layouts, and the circuit layout sample library stores a large number of The layout of the integrated circuit, the layout of the integrated circuit in the circuit layout sample library can be obtained by collecting the layout of a part of the integrated circuit or the layout of the complete integrated circuit that has been generated by different users. Specifically, for the device layouts associated with the relative layout information in the plurality of device layouts, the circuit layout sample library can be queried according to the corresponding associated device layouts and the relative layout information between them, if the circuit layout sample library exists in the circuit layout sample library that satisfies If there is a required layout, the layout can be determined as the layout corresponding to the associated device layout. If there is no layout that meets the requirements in the circuit layout sample library, the layout of the corresponding integrated circuit without wiring can be generated according to the description of S303 above; further, the electronic device can also generate the layout of the integrated circuit without wiring. The layout of an integrated circuit or a part of the layout of an integrated circuit without traces is stored in the circuit layout sample library for subsequent use or use by other users.

S304: Generate the layout of the integrated circuit corresponding to the circuit schematic diagram according to the physical location information.

When the electronic device obtains the layout of the integrated circuit without traces laid out according to the physical location information, the electronic device can, according to the circuit connection relationship in the schematic circuit diagram, create a layout of the integrated circuit without traces. Generate traces to obtain the layout of the integrated circuit corresponding to the circuit schematic diagram. Wherein, the circuit connection relationship can be obtained by the electronic device from the schematic circuit diagram, and the circuit connection relationship can be used to indicate the connection relationship of the multiple device layouts, for example, the circuit connection relationship can include multiple wiring lines .

Further, according to the circuit connection relationship, before generating the wiring in the layout of the integrated circuit without wiring, the method may further include: acquiring wiring information of at least one wiring, and the wiring information may include wiring path information, As well as wiring width constraint information, etc., the at least one routing can be a working index that affects the integrated circuit (for example, the working index can include but not limited to frequency, phase noise, amplitude fluctuation, power consumption, bandwidth, etc. One or more) key routing. Wherein, the at least one routing can be determined by the user, and the routing information of the at least one routing can also be input by the user; or, the electronic device can determine the at least one routing, for example, the electronic device can The at least one routing is determined in connection with the circuit. After acquiring the routing information of the at least one routing, the electronic device can generate the at least one routing in the layout of the integrated circuit without routing according to the routing information, and at the same time generate the at least one routing according to the circuit connection relationship. For other routings other than one routing, for example, use an algorithm to analyze the routing paths and layer jumps of the other routings and perform routing, so as to obtain the layout of the integrated circuit corresponding to the circuit schematic diagram.

Wherein, when generating the at least one key trace and the other traces, the electronic device may comprehensively consider the different requirements of the chip foundry for the traces (for example, such as a maximum current requirement of a trace of 20mA, etc.), and Layout design rules and other restrictions on routing, etc., to ensure that the routing in the generated layout can meet specific requirements. In addition, during the process of generating the at least one key routing and the other routing, if there are one or more routings passing through (via) different metal layers, the electronic device can also punch holes between different metal layers To realize the deployment of the one or more routings.

For ease of understanding, the method provided in the embodiment of the present application will be described below with reference to the digitally controlled oscillator shown in FIG. 4 as an example. The digitally controlled oscillator includes an inductor, an adjustable capacitor module, and a negative resistance module connected in parallel in sequence. Specifically, EDA software is installed on the electronic equipment, and the EDA software can include a model device library, a sample design library (which can include the above-mentioned device layout library and circuit layout library), a floor plan designer and routing Engine, as shown in FIG. 7, when generating the layout of the integrated circuit corresponding to the digitally controlled oscillator, the method may include: the layout planning designer obtains the parameter information of each module in the inductor, the adjustable capacitor module and the negative resistance module For example, the process parameter information can be TSMC28, the electrical parameter information of the inductor is width and length, the electrical parameter information of the adjustable capacitor module is the number of adjustable capacitors, and the width and length of a single adjustable capacitor, and the electrical parameter information of the negative resistance module. The parameter information is the number of rows and columns of the transistor, and the width and length of the channel of the transistor; the layout planning designer obtains the model device corresponding to each module in the inductor, adjustable capacitance module and negative resistance module, and according to the above parameter information Instantiate it into three device layouts, that is, the inductor device layout, the adjustable capacitance module device layout and the negative resistance module device layout (optional, you can query the sample design library, when the three devices exist in the sample design library One or more of the layouts can be obtained from the sample design library); the floor plan designer obtains the relative layout information of the three device layouts, and determines the layout of the multiple device layouts according to the relative layout information and process constraint information Physical location information, such as determining the metal layer where each device layout is located, and the coordinate position of the device layout in the metal layer, etc., can also generate an integrated circuit layout without traces based on the physical location information; the routing engine according to The physical location information and routing constraints generate the layout of the integrated circuit corresponding to the digitally controlled oscillator, where the path and width of the key routing in the layout can be given by the user, for example, as the main routing of the critical routing Paths (represented as thick lines in Figure 4) can be manually constrained by the user, and non-critical lines other than the critical line can be planned by the path engine field. If the line needs to be punched, it can be punched through the built-in hole punching engine accomplish). Wherein, the finally generated layout of the integrated circuit corresponding to the digital oscillator can be shown in FIG. The adjustable capacitance module and negative resistance module in the paper are described by taking the specific structure in the circuit schematic diagram as an example.

In the embodiment of the present application, after obtaining the parameter information of the multiple basic components included in the circuit schematic diagram, the electronic device can instantiate the model devices corresponding to the multiple basic components into multiple device layouts according to the parameter information , and based on the received relative layout information of the multiple device layouts, determine the physical location information of the multiple device layouts, and then generate the layout of the integrated circuit corresponding to the circuit schematic diagram according to the physical location information. Since the model devices corresponding to the multiple basic components are obtained by uniformly packaging the multiple basic components, the differences between different processes and different chip foundries are shielded, and a unified input and output interface can be provided. Users can input the relative layout information of multiple device layouts and the wiring information of key routings that affect the working indicators of integrated circuits according to actual needs, so that the layout designers can be more focused while realizing the automatic layout design of integrated circuits It is based on the overall layout without spending a lot of time on manual layout and routing, DRC or LVS correction, thus solving the problem of long labor time in layout design. In addition, during the layout design process of the integrated circuit, the layout of the device or the layout of the integrated circuit that has been generated before can also be reused, so that the reuse rate of the design can be further improved.

The foregoing mainly introduces the solutions provided by the embodiments of the present application from the perspective of electronic equipment. It can be understood that, in order to realize the above functions, the electronic equipment includes corresponding hardware structures and/or software modules for performing various functions. Those skilled in the art should easily realize that the present application can be implemented in the form of hardware or a combination of hardware and computer software in combination with the units and algorithm steps of each example described in the embodiments disclosed herein. Whether a certain function is executed by hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

The embodiment of the present application can divide the functional modules of the layout generation device of the integrated circuit according to the above method example, for example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module . The above functional modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be other division methods in actual implementation.

In the case of dividing each functional module corresponding to each function, FIG. 9 shows a possible structural schematic diagram of the layout generation device of the integrated circuit involved in the above embodiment. The device can be an electronic device or be applied to an electronic device. chip in. The device includes: an acquisition unit 401 and a processing unit 402 . Wherein, the obtaining unit 401 is used to support the device to execute the steps of obtaining relative layout information in S301 and S303 in the above method embodiment, and obtaining the wiring information of at least one key routing described herein; the processing unit 402 is used to support this The device executes S302 and S303 in the above method embodiment to determine the physical location information of multiple device layouts, S304, and other technical processes described herein.

On the basis of hardware implementation, the above-mentioned processing unit 402 may be a processor, the acquisition unit 401 may be a receiver, and the receiver and the transmitter may be integrated into a transceiver, which may also be called a communication interface.

FIG. 10 is a schematic structural diagram of an integrated circuit layout generation device according to an embodiment of the present application. The device may be an electronic device or a chip applied to an electronic device. The device includes: a communication interface 413 and a processor 412 . Wherein, the processor 412 is used to control and manage the actions of the device, for example, the processor 412 can be used to support the device to execute S301-S304 in the above method embodiment, and/or other processes for the technologies described herein ; The communication interface 413 can be used to support the device to communicate. Optionally, the device may further include a memory 411 for storing program codes and data of the device.

Wherein, the processor 412 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a processing chip, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof . It can realize or execute various logical blocks, modules and circuits described in conjunction with the disclosure of the embodiments of the present application. The processor 412 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like. The communication interface 413 may be a transceiver, a transceiver circuit, or a transceiver interface or the like. The memory 411 may be a volatile memory or a non-volatile memory or the like.

For example, the communication interface 413, the processor 412, and the memory 411 are interconnected via a bus 414, and the bus 414 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus Wait. The bus 414 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in FIG. 10 , but it does not mean that there is only one bus or one type of bus.

It should be noted that all the content in the foregoing method embodiments can be referenced correspondingly in the device embodiments, and details will not be repeated here in the embodiments of the present application.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation or may be integrated into another device, or some features may be omitted, or not implemented.

The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be one physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places . Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

Finally, it should be noted that: the above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto, and any changes or replacements within the technical scope disclosed in the application shall be covered by this application. within the scope of the application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A layout generation method for an integrated circuit, characterized in that the method comprises:

Obtain the parameter information of multiple basic components included in the circuit schematic diagram;

determining a plurality of device layouts corresponding to the plurality of basic components according to the parameter information;

Acquiring relative layout information of the plurality of device layouts, and determining physical location information of the plurality of device layouts according to the relative layout information and the plurality of device layouts;

According to the physical location information, the layout of the integrated circuit corresponding to the circuit schematic diagram is generated.
The method according to claim 1, wherein said determining multiple device layouts corresponding to said multiple basic components according to said parameter information comprises:

For the first basic component among the plurality of basic components, instantiate the model device corresponding to the first basic component into a device layout according to the parameter information of the first basic component, and the first basic component A basic component is any one of the multiple basic components.
The method according to claim 2, further comprising:

According to the first basic component, the model device corresponding to the first basic component is obtained from the preset model device library, the preset model device library includes a plurality of model devices, and the plurality of model devices are respectively It is obtained by performing a unified packaging process on multiple different basic units, where the multiple different basic units include the first basic component.
The method according to any one of claims 1-3, wherein the determining the multiple device layouts corresponding to the multiple basic components according to the parameter information includes:

For the second basic component among the plurality of basic components, according to the parameter information of the second basic component, the device layout of the second basic component is obtained from the device layout library, and the device layout library including a device layout of each basic unit in at least one basic unit under at least one set of parameter information, the second basic component is any one of the plurality of basic components, and the at least one basic A unit includes said second basic element.
The method according to any one of claims 1-4, wherein the determining the physical location information of the multiple device layouts according to the relative layout information and the multiple device layouts includes:

According to the relative layout information and the size of the multiple device layouts, the multiple device layouts are laid out to obtain the physical location information of the multiple device layouts, and the physical location information can be used to generate layout of an integrated circuit.
The method according to claim 5, wherein the laying out the multiple device layouts according to the relative layout information and the sizes of the multiple device layouts comprises:

According to the relative layout information, the size of the plurality of device layouts and at least one constraint condition, the layout of the plurality of device layouts is performed, and the at least one constraint condition includes one or more of the following conditions: minimum Area constraints, minimum distance constraints, current relationships or distance relationships between different device layouts.
The method according to any one of claims 1-6, wherein the generating the layout of the integrated circuit corresponding to the circuit schematic diagram according to the physical location information includes:

According to the circuit connection relationship in the circuit schematic diagram, wiring is performed in the layout of the integrated circuit corresponding to the physical position information without wiring, so as to generate the layout of the integrated circuit corresponding to the circuit schematic diagram.
The method according to claim 7, wherein, according to the circuit connection relationship in the circuit schematic diagram, wiring is carried out on the layout of the integrated circuit corresponding to the physical position information without wiring, including:

Acquiring routing information of at least one routing, where the at least one routing is a routing in the layout of the integrated circuit corresponding to the circuit schematic diagram;

According to the circuit connection relationship in the circuit schematic diagram and the routing information of the at least one routing, routing is performed in the integrated circuit layout corresponding to the physical position information without routing.
The method according to any one of claims 1-8, wherein the relative layout information includes relative position information between projections of at least two device layouts in the same metal layer among the plurality of device layouts.
The method according to any one of claims 1-9, wherein the relative layout information further includes relative level information between metal layers where at least two device layouts among the plurality of device layouts are located.
The method according to any one of claims 1-10, wherein the parameter information includes process parameter information and electrical parameter information.
A layout generation device for an integrated circuit, characterized in that the device comprises:

an acquisition unit, configured to acquire parameter information of a plurality of basic components included in the schematic circuit diagram;

a processing unit, configured to determine a plurality of device layouts corresponding to the plurality of basic components according to the parameter information;

The acquiring unit is further configured to acquire relative layout information of the plurality of device layouts;

The processing unit is further configured to determine physical location information of the multiple device layouts according to the relative layout information and the multiple device layouts;

The processing unit is further configured to generate the layout of the integrated circuit corresponding to the circuit schematic diagram according to the physical location information.
The device according to claim 12, wherein the processing unit is further used for:

For the first basic component among the plurality of basic components, instantiate the model device corresponding to the first basic component into a device layout according to the parameter information of the first basic component, and the first basic component A basic component is any one of the multiple basic components.
The device according to claim 13, wherein the processing unit is further used for:

According to the first basic component, the model device corresponding to the first basic component is obtained from the preset model device library, the preset model device library includes a plurality of model devices, and the plurality of model devices are respectively It is obtained by performing a unified packaging process on multiple different basic units, where the multiple different basic units include the first basic component.
The device according to any one of claims 12-14, wherein the processing unit is further configured to:

For the second basic component among the plurality of basic components, according to the parameter information of the second basic component, the device layout of the second basic component is obtained from the device layout library, and the device layout library including a device layout of each basic unit in at least one basic unit under at least one set of parameter information, the second basic component is any one of the plurality of basic components, and the at least one basic A unit includes said second basic element.
The device according to any one of claims 12-15, wherein the processing unit is further configured to:

According to the relative layout information and the size of the multiple device layouts, the multiple device layouts are laid out to obtain the physical location information of the multiple device layouts, and the physical location information can be used to generate layout of an integrated circuit.
The device according to claim 16, wherein the processing unit is further used for:

According to the relative layout information, the size of the plurality of device layouts and at least one constraint condition, the layout of the plurality of device layouts is performed, and the at least one constraint condition includes one or more of the following conditions: minimum Area constraints, minimum distance constraints, current relationships or distance relationships between different device layouts.
The device according to any one of claims 12-17, wherein the processing unit is further configured to:

According to the circuit connection relationship in the circuit schematic diagram, wiring is performed in the layout of the integrated circuit corresponding to the physical position information without wiring, so as to generate the layout of the integrated circuit corresponding to the circuit schematic diagram.
The device according to claim 18, characterized in that,

The processing unit is further configured to acquire routing information of at least one routing, and the at least one routing is a routing in the layout of the integrated circuit corresponding to the circuit schematic diagram;

The processing unit is further configured to, according to the circuit connection relationship in the circuit schematic diagram and the routing information of the at least one routing, perform routing in the integrated circuit layout corresponding to the physical position information without routing.
The device according to any one of claims 12-19, wherein the relative layout information includes relative position information between projections of at least two device layouts in the same metal layer among the plurality of device layouts.
The device according to any one of claims 12-20, wherein the relative layout information further includes relative level information between metal layers where at least two device layouts among the plurality of device layouts are located.
The device according to any one of claims 12-21, wherein the parameter information includes process parameter information and electrical parameter information.
A layout generation device for an integrated circuit, characterized in that the device includes a processor and a memory, instructions are stored in the memory, and the processor executes the instructions in the memory, so that the device executes the A layout generation method for an integrated circuit as described in any one of Claims 1-11.
A computer-readable storage medium, characterized in that instructions are stored in the computer-readable storage medium, and when the instructions are run on a device, the device is made to perform the operation described in any one of claims 1-11. A layout generation method for integrated circuits.
A computer program product, characterized in that, when the computer program product is run on a device, the device is made to execute the layout generation method for an integrated circuit according to any one of claims 1-11.