CN112989751B

CN112989751B - Circuit channel wiring method and device based on branch-and-bound method and electronic equipment

Info

Publication number: CN112989751B
Application number: CN202110508171.5A
Authority: CN
Inventors: 魏迎梅; 韩贝贝; 窦锦身; 杨雨璇; 万珊珊; 冯素茹
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2021-05-11
Filing date: 2021-05-11
Publication date: 2021-08-06
Anticipated expiration: 2041-05-11
Also published as: CN112989751A

Abstract

The utility model provides a circuit channel wiring method, a device and an electronic device based on a branch-and-bound method, wherein, the method comprises: constructing a two-dimensional grid in a wiring space; marking coordinates of each pin in the circuit diagram in the two-dimensional grid; taking pins connected in the circuit diagram as pin pairs, wherein the circuit diagram comprises a plurality of pin pairs; determining wiring paths corresponding to a plurality of pin pairs in the circuit diagram according to a branch-and-bound method; and drawing a circuit wiring diagram according to the wiring paths of the pin pairs. The method can utilize the branch-and-bound method to select the wiring path for each connected pin pair in the circuit diagram, and the selected wiring path can ensure the optimal wiring path under the condition of not causing open circuit or short circuit, thereby reducing the influence of parasitic resistance introduced by the connecting wires on the performance of the whole circuit.

Description

Circuit channel wiring method and device based on branch-and-bound method and electronic equipment

Technical Field

The invention relates to the technical field of circuit wiring, in particular to a circuit channel wiring method and device based on a branch-and-bound method and electronic equipment.

Background

An integrated circuit is a core part of the information industry, and the integrated circuit is a circuit having a specific function that integrates electronic components by using a semiconductor technology, and has been widely used in various aspects of production and life. With the development of the technology, the number of components inside an integrated circuit has reached the billion level, and circuit Design and implementation can be completed only by means of special computer software, which is generally called an Electronic Design Automation (EDA) tool.

When conducting the wiring of circuit wire, need minimize the length of wiring under the condition of not causing the open circuit or short circuit, reduce the influence of wire resistance, traditional circuit channel wiring is directly according to the way of minimizing the wiring length and is wired, but this way easily appears the short circuit or the condition of open circuit.

Disclosure of Invention

In view of the above, the present invention is directed to a circuit path routing method, device and electronic device based on branch-and-bound method, so as to overcome the above problems or at least partially solve the above problems.

In view of the above object, a first aspect of the present invention provides a circuit path routing method based on branch-and-bound method, including:

constructing a two-dimensional grid in a wiring space;

marking coordinates of each pin in the circuit diagram in the two-dimensional grid;

taking pins connected in the circuit diagram as pin pairs, wherein the circuit diagram comprises a plurality of pin pairs;

determining wiring paths corresponding to a plurality of pin pairs in the circuit diagram according to a branch-and-bound method;

and drawing a circuit wiring diagram according to the wiring paths of the pin pairs.

In view of the above object, a second aspect of the present invention provides a circuit path routing apparatus based on branch-and-bound method, comprising:

the network construction module is used for constructing a two-dimensional grid in a wiring space;

the marking module is used for marking the coordinates of each pin in the circuit diagram in the two-dimensional grid;

a pin pair determining module, configured to use pins connected in the circuit diagram as pin pairs, where the circuit diagram includes a plurality of pin pairs;

the path determining module is used for determining the wiring paths corresponding to the pin pairs in the circuit diagram according to a branch-and-bound method;

and the layout module is used for drawing a circuit layout according to the wiring paths of the pin pairs.

In view of the above object, a third aspect of the present invention provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method according to the first aspect when executing the program.

From the above, it can be seen that the circuit channel wiring method, the device and the electronic device based on the branch-and-bound method provided by the invention can select the wiring path for each connected pin pair in the circuit diagram by using the branch-and-bound method, and the selected wiring path can ensure the optimal wiring path without causing open circuit or short circuit, thereby reducing the influence of parasitic resistance introduced by the connecting wires on the performance of the whole circuit.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the related art, the drawings required to be used in the description of the embodiments or the related art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a flow chart of a circuit channel wiring method based on a branch-and-bound method according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a step 104 of a circuit path routing method based on a branch-and-bound method according to an embodiment of the present invention;

FIG. 3 is another specific flowchart of step 104 of a circuit path routing method based on branch-and-bound method according to an embodiment of the present invention;

FIG. 4 is a detailed flowchart of step 104 of a circuit path routing method based on branch-and-bound method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a wiring space according to an embodiment of the invention;

FIG. 6 is a schematic diagram of the shortest path of pin pair [3,1] in FIG. 5;

FIG. 7 is a schematic diagram of a wiring solution for each pin pair of FIG. 5;

FIG. 8 is a schematic diagram of another empty routing space in accordance with an embodiment of the present invention;

FIG. 9 is a schematic diagram of the routing path for pin pair [1,1] of FIG. 8;

FIG. 10 is a diagram of a reachable path search tree for pin (1,4) of pin pair [2,2] in FIG. 8;

FIG. 11 is a diagram of a reachable path search tree for pin (4,3) of pin pair [2,2] in FIG. 8;

FIG. 12 is a schematic diagram of the routing path for pin pair [2,2] of FIG. 8;

FIG. 13 is a diagram of a search tree for the reachable path of pin (1,5) in FIG. 8;

FIG. 14 is a schematic diagram of the routing path for pin pair [3,3] of FIG. 8;

FIG. 15 is a schematic diagram of the routing paths for each pin pair of Table 1;

FIG. 16 is a schematic diagram of a qualified via spacing arrangement;

FIG. 17 is a schematic diagram of a blank pin to be routed;

FIG. 18 is a schematic diagram of the pin pair [1,1] routing path of FIG. 17;

FIG. 19 is a diagram of a search tree for the reachable paths of pin (1,4) in FIG. 17;

FIG. 20 is a schematic diagram of the wire path of pin pair [2,2] of FIG. 17;

FIG. 21 is a diagram of a search tree for reachable paths for the upper pin (1,4) of pin number 2 in FIG. 17;

FIG. 22 is a diagram of a search tree for reachable paths for the lower pin (6,3) of pin number 2 in FIG. 17;

FIG. 23 is a diagram of a search tree for the reachable path of pin (1,4) in FIG. 17;

FIG. 24 is a schematic view of the wire path of pin number 3 in FIG. 17;

FIG. 25 is a schematic diagram of a routing path for a deadlock problem;

FIG. 26 is a schematic diagram of a wiring path with a predetermined distance set between vias in Table 1;

FIG. 27 is a block diagram of a circuit path routing apparatus based on branch-and-bound method according to an embodiment of the present invention;

fig. 28 is a schematic hardware structure diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

It should be noted that technical terms or scientific terms used in the embodiments of the present invention should have the ordinary meanings as understood by those having ordinary skill in the art to which the present invention belongs, unless otherwise defined. The use of "first," "second," and similar language in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and similar language are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The integrated circuit design consists of multiple stages, one important stage being called "physical design", the devices being placed in appropriate positions and then connected by wire connectors. Among them, the latter is called "wiring", which is an important problem that EDA needs to solve. In simple terms, the process is called "routing", assuming that the routing area consists of squares, the metal lines are allowed to be placed along straight lines or right angles (squares), connecting the designated squares (pins) without causing open or short circuits. For metal wiring having only one layer, the lines are not allowed to cross in order not to cause a short circuit. However, in practice, most integrated circuits employ multiple metal layers, different metal layers are at different heights, and adjacent layers need to be communicated by using through holes, so that different metal layers do not cause short circuit by sharing through holes. When conducting wiring, it is necessary to minimize the length of wiring and reduce the influence of resistance without causing disconnection or short circuit.

The present invention focuses on solving one particular case of the "wiring" problem: "channel routing". The present invention first performs the design and solution of "via routing" for these three different problems, from the simplest single layer "via routing", to "via routing" that contains two metal layers, and "via routing" for two metal layers when the distance between vias is constrained. The "channel" refers to a horizontal wiring region in which metal wires are required to connect corresponding pins.

As shown in fig. 1, the circuit path wiring method based on the branch-and-bound method of this embodiment includes:

step 101, constructing a two-dimensional grid in a wiring space.

In this step, the wiring space may be a one-layer wiring space or a multi-layer wiring space. The two-dimensional network is formed by grids with the same size, the width of the grids can be correspondingly adjusted according to actual needs, and the two-dimensional network formed in the way is formed by n multiplied by m grids, wherein n is the number of the transverse grids of the two-dimensional network, and m is the number of the longitudinal grids of the two-dimensional network.

Step 102, marking the coordinates of each pin in the circuit diagram in a two-dimensional grid.

In this step, before wiring according to the circuit diagram, it is necessary to mark in the two-dimensional network the positions of the pins of the individual electrical components in the circuit diagram. And after marking, locking the grids at the coordinates of each pin, and prohibiting the connecting line from passing through. And if multi-layer channel wiring is carried out, the through holes are forbidden to be arranged according to the grids of the pin coordinates.

And 103, taking the pins connected in the circuit diagram as pin pairs, wherein the circuit diagram comprises a plurality of pin pairs.

In this step, the coordinate values of the pairs of connected pins are stored in a list, so that the corresponding pairs of pins can be called out from the list in sequence or randomly for wiring.

And step 104, determining the wiring paths corresponding to the pin pairs in the circuit diagram according to a branch-and-bound method.

In the step, a branch-and-bound method is used for searching a corresponding wiring path for the pin pairs, the searched path may be one path or multiple paths, and if the searched path is multiple paths, any one wiring path is used as the alignment for the next pin pair, and then a branch-and-bound algorithm is used for searching the wiring path. Such a circuit diagram may be able to find multiple sets of routing paths.

Step 105, drawing a circuit wiring diagram according to the wiring paths of the pin pairs.

In this step, if there is at least one group of wiring paths corresponding to the circuit diagram, at least one circuit wiring diagram can be drawn correspondingly, and then the at least one circuit wiring diagram is presented to the user, so that the user can select a most satisfactory circuit wiring diagram from the at least one circuit wiring diagram for actual wiring.

Through the scheme, the wiring path can be selected by utilizing the branch-and-bound method for each connected pin pair in the circuit diagram, the selected wiring path can be ensured to be optimal under the condition of not causing open circuit or short circuit, and then the influence of parasitic resistance introduced by the connecting wire on the performance of the whole circuit is reduced.

In a specific embodiment, step 104 specifically includes:

step 1041, selecting a target pin pair from the plurality of pin pairs, and determining a routing path of the target pin pair by using a branch-and-bound method.

In the step, a pin pair is randomly or sequentially selected from a storage list of the pin pairs to serve as a first target pin pair, a routing path A of the first target pin pair is determined by a branch-and-bound method, and then a spatial tree is constructed by taking the routing path A as a father node. And the routing path a may be multiple, such as a1, a2, and A3, three spatial trees are constructed with a1, a2, and A3 as parent nodes, respectively.

And 1042, performing forbidden cross connection locking on the wiring paths of the target pin pairs to obtain a next target pin pair, determining the wiring paths of the next target pin pair by using a branch-and-bound method, and continuously iterating the process until all the pin pairs in the circuit diagram determine corresponding wiring paths.

In this step, the obtained wiring path of the root node is subjected to forbidden cross-connection locking (that is, the wiring path a is taken as a "fence"), the wiring path B of the next target pin pair is continuously searched by adopting the branch-and-bound method, and the wiring path B is placed on the child node of the parent node a. Wherein, if there are multiple routing paths found (B1, B2), they are the children of the parent node A.

And then taking the wiring path B as a father node, continuously searching the wiring path C of the next target pin pair by adopting a branch-and-bound method, and circulating the steps until all the pin pairs in the circuit diagram determine the corresponding wiring paths.

And then, tracing and searching the last father node X upwards for the child node from the father node Y of the last child node Z, judging whether the corresponding father node X has a plurality of child nodes, and if not, continuing to search upwards. If the W is found to have a plurality of child nodes X1 and X2 (wherein X1 is the child node corresponding to the tracing path, and X1 already has the corresponding child node). And taking the rest child nodes X2 as parent nodes, carrying out forbidden cross connection locking on the X2 wiring path, and searching the wiring path Y1 of the next pin pair by using a branch-and-bound method until the wiring path of the last pin pair is determined. The above process is repeated until all the branches of the whole spatial tree can contain all the pin pairs from the root node to the end node.

Through the scheme, one or more space trees are correspondingly constructed, each space tree corresponds to a plurality of groups of wiring paths containing all pin pairs in the circuit diagram, and therefore each group of wiring paths can be sorted, and wiring drawing is carried out and presented to a user for the user to select. Or only one space tree is constructed, the space tree only has one branch trend, and only one group of wiring paths containing all pin pairs in the circuit diagram are proved, so that a user does not need to select the wiring paths, and the circuit wiring can be directly carried out according to the circuit wiring diagram obtained by the group of wiring paths.

In a specific embodiment, before step 1042, the method further comprises:

step 1042', setting the setting conditions as:

；

wherein the content of the first and second substances,

、

respectively representing the upper pin coordinate and the lower pin coordinate of a pin pair,

、

respectively represent

Horizontal and vertical coordinates within the two-dimensional network

，

、

To represent

Horizontal and vertical coordinates within the two-dimensional network

，

Representing the wiring path distance of the pin pairs,

indicating the number of pin pairs that the circuit diagram contains,

is a positive integer and is a non-zero integer,s _n1jands _n2jthe coordinates of two adjacent upper pins are represented,e _n1jande _n2jrepresenting the coordinates of two adjacent lower pins.

In this step, when the channel wiring is performed, there cannot be an intersection between two wirings, that is, the sum of products of subtraction of column coordinates of a first pin pair and a second pin pair is greater than 0, that is, if the column coordinate of the upper pin of the first wiring is smaller than the column coordinate of the upper pin of the second wiring, the column coordinate of the lower pin of the first wiring must also be smaller than the column coordinate of the lower pin of the second wiring, otherwise, an intersection is generated, which may cause a short circuit.

As shown in fig. 5, the column coordinate of the upper pin number 3 is smaller than the column coordinate of the upper pin number 5 (in this example, the column coordinate is equal to the number of the pin), and the column coordinate of the lower pin number 1 is smaller than the column coordinate of the lower pin number 4, so if it is desired to connect the upper pin 3 and the lower pin 4, the upper pin 5 and the lower pin 1,

if the difference is less than 0, the crossing will occur, so the achievement of the coordinate difference of the upper pin column and the lower pin column of every two lines is required to be more than 0 as a constraint, and the minimum sum of all the wiring lengths is used as a constraint objective function in the set condition.

In addition, s.t. is an abbreviation of subject to, representing a constraint.

In the process of selecting the wiring path, the constraint is required according to the set condition, so that the condition that two wirings are crossed and short-circuited in the process of wiring can be avoided.

In a specific embodiment, as shown in fig. 3, step 104 further specifically includes:

and 104a, taking the coordinate of one pin in the pin pair as a datum point and the coordinate of the other pin as a termination point. The pin pair refers to any pin pair in the circuit diagram, which needs to be subjected to wiring path selection.

And step 104b, determining a square position closest to the end point from at least one movable square position of the reference point as a displacement point, discarding the rest square positions, taking the displacement point as a new reference point, continuously iterating the process until the displacement point reaches the end point, and determining at least one displacement route corresponding to the pin pair.

And 104c, taking the determined at least one displacement route as a wiring route of the pin pair.

In the above scheme, a spatial tree may be established starting from the reference point, and the corresponding movable square point is used as a live node. Each live node has only one chance to become an extended node, and once a live node becomes an extended node, all its children nodes are generated at one time, and among these children nodes, those children nodes that result in an infeasible solution or result in a non-optimal solution are discarded, and the rest of the children nodes are added to the live node table. Thereafter, the next node is taken from the live node table to become the current expansion node, and the above node expansion process is repeated. This process continues until the desired solution or livelock table is found to be empty. Different ways of selecting the next expansion node from the live node table result in different branch and bound methods, which specifically include: queue-type (FIFO) branch-and-bound and/or Priority-queue (PQ) branch-and-bound. The queue type branch-and-bound method specifically carries out the searching process of the sequential wiring path according to the corresponding arrangement sequence of the pin pairs. The priority queue type branch-and-bound method specifically carries out the searching process of the wiring path according to the sequence of the corresponding priority of the pin pairs.

Through the scheme, when all the pins of the circuit diagram are searched for the wiring paths correspondingly, all the optimal wiring solutions corresponding to the circuit diagram can be searched for completely, the missing situation is avoided, multiple groups of the searched wiring paths are possible, and a user can select the wiring paths according to actual needs.

In an embodiment, the routing path of a target pin pair is taken as a parent node, the routing path of the next target pin pair is taken as a child node, and the target pin pair refers to any one of a plurality of pin pairs included in the circuit diagram.

Then, in step 1042, the routing path of the next target pin pair is determined by using a branch-and-bound method, which specifically includes:

and determining that the wiring path of the child node obtained by using a branch-and-bound method is zero, searching the corresponding previous father node by using the father node as the child node by using a backtracking method, deleting the father node until the previous father node is determined to have a plurality of child nodes, selecting one child node from the rest child nodes as the father node, and determining the wiring path of the corresponding child node by using the branch-and-bound method.

In this step, if there are a plurality of child nodes in one parent node, the expansion is continued with any child node as the parent node, and the remaining child nodes are stored in the node repository as nodes.

Based on the above conditions, if the wiring path of the pin pair corresponding to the child node cannot be found, the parent node corresponding to the child node needs to be deleted, and a backtracking method is used to perform upward backtracking search to determine whether the corresponding child node exists in the active node repository for the previous parent node. If so, calling the corresponding child node from the live node storage library, deleting the called child node from the live node storage library, taking the called child node as a parent node, and determining the wiring path of the corresponding child node by using a branch-and-bound method. If not, deleting the father node, continuously tracing the last father node upwards until whether the last father node has a corresponding child node in the active node storage library is determined, and searching the wiring path according to the method. If the routing path of the pin pair corresponding to the child node cannot be found in the searching process, the process is continuously repeated.

In particular embodiments, in such an iterative process, there may be a situation where the corresponding routing path may not be found after traversing all of the active nodes in the active node repository. That is, the pin pair does not find a corresponding routing path, and the pin pair is determined to be an unreachable pin pair. In this case, it is necessary to form through holes, to perform wiring by using two or more layers of wiring spaces, and to set a through hole set as an empty set in advance.

As shown in fig. 4, step 104 further includes:

and 104d, judging whether the through hole set is a non-empty set, if so, entering the step 104e, and otherwise, entering the step 104 g.

And 104e, judging whether through hole coordinates which can be reached by two pins of the inaccessible pin pair are found from the through hole set, if so, entering step 104f, and otherwise, entering step 104 g.

And step 104f, taking the found through hole coordinates which can be reached by the two pins of the unreachable pin pair as the through hole coordinates of the unreachable pin pair.

And step 104g, determining corresponding through hole coordinates for the inaccessible pin pairs by using a backtracking method, and adding the through hole coordinates to the through hole set.

And 104h, determining that paths of two pins of the unreachable pin pair respectively reaching the through hole coordinates are wiring paths of a first layer of wiring space, and determining that a connection path of the two through hole coordinates is a wiring path of a second layer of wiring space, wherein the second layer of wiring space refers to at least one wiring space except the first layer of wiring space.

And 104i, searching the wiring path of the next pin pair by using a branch-and-bound algorithm until all the pin pairs in the circuit diagram determine the corresponding wiring paths.

In the above steps, some integrated circuits cannot adopt one layer of wiring space to complete wiring, and can adopt a plurality of layers of wiring spaces, the wiring spaces of different layers are at different heights, and adjacent layers are communicated by using through holes, so that different wiring spaces can share the through holes without causing short circuit.

Taking two wiring space layers as an example, channel wiring is carried out in a wiring space, and the shortest reachable path between the pin pairs and the determination of the positions of the through holes are determined by combining a branch-and-bound algorithm and a backtracking method, so that the total wiring length is minimum.

The method specifically comprises the following steps:

first, a pin pair P1 is arbitrarily selected, and a corresponding routing path L1 is obtained in the first-level routing space by using a branch-and-bound method.

Then, routing paths of other pin pairs are sequentially searched by using a branch-and-bound method, the pin pair P2 is found to be unreachable, the pin pair 2 is determined to be an unreachable pin pair, the position of a through hole needs to be searched, and the through hole and a second-layer routing space are used for conducting connection routing. And repeating the steps continuously until all pin pairs in the circuit diagram find corresponding wiring paths, or no active node exists in the corresponding active node storage library.

And finally, drawing a circuit wiring diagram according to the wiring paths of the pin pairs.

Through the scheme, the wiring design can be carried out by utilizing the multilayer wiring space, so that the condition that the circuit wiring cannot be carried out due to the fact that corresponding wiring paths cannot be found in some circuit diagrams is avoided. And this embodiment combines branch and delimit the method and trace back the method and select the passageway position of confirming more rationally, carries out the wiring design and accords with actual need more based on the passageway that corresponds, when guaranteeing the normal wiring of circuit diagram, guarantees that the connecting wire of circuit diagram can reach the shortest, reduces the influence of the additional resistance that the connecting wire produced.

In a specific embodiment, step 104d specifically includes:

respectively constructing corresponding search trees according to reachable paths of two pins of the unreachable pin pairs, wherein reachable coordinates of the two pins of the unreachable pin pairs are used as leaf nodes of the search trees; calculating the node distance between leaf nodes of the two search trees, wherein the obtained node distance is at least one; and taking the two leaf nodes corresponding to the node distance with the minimum distance value as through hole coordinates, and adding the through hole coordinates into the through hole set.

In the above step, if the set of through holes is a non-empty set, the shortest path from the two pins of the unreachable pin pair to any two through holes in the set of through holes is calculated, and then the through hole position corresponding to the unreachable pin pair is found from the set of through holes, if not, the corresponding through hole position is found in the above step 104d, and the found through hole position is added to the set of through holes.

Through the mode, the found through hole distance is the most appropriate, and meanwhile, the number of punched holes can be reduced as much as possible.

In the specific embodiment, for some specific wiring requirements, the distance between two adjacent through holes cannot be too close, so that the distance between two through holes is required to be preset to be greater than or equal to the preset distance

。

Then, in step 104d, "taking the two leaf nodes corresponding to the node distance with the minimum distance value as the coordinates of the through hole, and adding the coordinates of the through hole to the through hole set" further includes:

taking the node distance which is greater than or equal to the preset distance as a node distance to be selected, wherein the node distance to be selected is at least one; selecting the distance of the node to be selected with the minimum distance value from the at least one distance of the node to be selected as the final node distance; and taking the two leaf nodes corresponding to the final node distance as through hole coordinates, and adding the through hole coordinates into the through hole set.

Through above-mentioned scheme, can utilize and predetermine the distance and prescribe a limit to the distance between the through-hole, guarantee that two adjacent through-holes can not be too near apart from, avoid two through-hole distances to cause the influence to wiring space and connecting wire too near.

Based on the description of the above embodiments, another embodiment of the present invention provides a circuit path routing method based on branch-and-bound method, which reduces the influence of parasitic resistance introduced by metal lines on the circuit by minimizing the length of the routing. The simplest single layer "channel routing", to the "channel routing" comprising two metal layers, and the "channel routing" of two metal layers when the distance between vias is constrained, are designed in a step-by-step progression from simple to complex.

Branch and bound is one of the most common algorithms for solving integer programming problems. The method can solve not only pure integer programming but also mixed integer programming. The branch-and-bound method is a search and iteration method, and different branch variables and subproblems are selected for branching. The backtracking method (exploration and backtracking method) is a method of searching for the best, also called heuristic method, and searches forward according to the best condition to achieve the goal. However, when a certain step is explored, if the original selection is not good or the target is not reached, the step is returned to be reselected, the technology of returning to be returned to be a backtracking method, and a point of a certain state meeting the backtracking condition is called a backtracking point.

The branch-and-bound method often searches the solution space tree of the problem in a breadth-first or least-costly (most-profitable) first manner. Unlike backtracking, in searching the solution space tree of the problem, each live node has only one chance to become an extension node, and once a live node becomes an extension node, all its children nodes are generated at one time, and among these children nodes, those children nodes that result in an infeasible solution or in a non-optimal solution are discarded, and the rest of the children nodes are added to the live node table. Thereafter, the next node is taken from the live node table to become the current expansion node, and the above node expansion process is repeated. This process continues until the desired solution or livelock table is found to be empty. The different ways of selecting the next expansion node from the list of live nodes results in different branch-and-bound methods, the most common being both the queued (FIFO) branch-and-bound method and the Prioritized Queued (PQ) branch-and-bound method. The present embodiment solves the above-mentioned three "channel routing" problems based on branch-and-bound and backtracking methods.

The implementation process of the application scenario specifically solving the above problems is as follows:

one-layer or single-layer channel wiring

Suppose a routing space is composed of

The number of the upper edge and the lower edge in the space respectively corresponds to the pin number of the square grids, and the pins with the same number need to be connected. To address this problem, it is then desirable to minimize the total length of the wiring without the wiring causing a short, which can be abstracted as minimizing the shortest path problem between two points on the grid. The embodiment designs a model according to the relation between columns where the pin coordinates are located and the constraint that the grids which are already wired are locked (preventing the lines from cross short circuit), and adoptsAnd solving by using a branch-and-bound algorithm, realizing no intersection between two wirings and minimizing the length of the total wiring.

The invention takes 3 pairs of pin data in fig. 5 as an example to perform the solution explanation of single-layer channel wiring, and the coordinates of the upper pin and the lower pin of the 3 pairs of pins are respectively [3,1]、[5,4]、[6,7]The wiring space is

. The invention first considers the pin coordinate pair [3,1]]Pin pair [3,1]]In that

The invention adopts random mode to select one shortest path arbitrarily and connect it; second, for pin pair [5,4]]In the pin pair [3,1]]Based on the constraint that the wire has been laid out, i.e. the pin pair [3,1]]The connection line can be regarded as a 'fence' in the network, and on the basis of the constraint, a branch-and-bound algorithm is adopted to find the pin pair [5,4]]The shortest reachable path between them, and connect them together as a pin pair [5,4]]The wiring of (1); finally, at pin pair [3,1]]And pin pair [5,4]]On the basis of connecting the 'enclosing wall', the branch-and-bound algorithm is continuously adopted to find the pin pair [6,7 ]]The shortest reachable path in between. The entire wiring problem is solved.

When the channel wiring is performed, no intersection exists between the two wirings, namely, the product of the subtraction of the column coordinates of the first pin pair and the second pin pair is larger than 0, namely, if the column coordinate of the upper pin of the first wiring is smaller than the column coordinate of the upper pin of the second wiring, the column coordinate of the lower pin of the first wiring must also be smaller than the column coordinate of the lower pin of the second wiring, otherwise, the intersection is generated, and the short circuit is caused. As shown in FIG. 5, the column coordinate of the upper pin number 3 is smaller than the column coordinate of the upper pin number 5 (in this example, the column coordinate is equal to the pin number), and the column coordinate of the lower pin number 1 is smaller than the column coordinate of the lower pin number 4, so if one wants to let the upper pin number 3 be smaller than the lower pin number 4The pin 3 is connected with the lower pin 4, the upper pin 5 is connected with the lower pin 1,

less than 0, crossover occurs, so it is desirable to have the product of the difference between the upper and lower pin column coordinates for each two lines greater than 0 as a constraint, while minimizing the sum of all wire lengths as an objective function.

Definition of

、

Respectively representing the upper pin coordinate and the lower pin coordinate of a pin pair (i.e. the start point and end point coordinates of a wire),

indicating the number of total required wires, i.e. pin pairs,

is a positive integer. Wherein the content of the first and second substances,

、

respectively represent the starting points

Is/are as follows

Coordinates and

the coordinates, i.e., the number of rows and columns where the upper pins are located, and similarly,

、

indicating endpoint

Is/are as follows

Coordinates and

the coordinates, i.e., the number of rows and columns in which the lower pins are located.

At the same time use

The distance is represented by the number of grid points through which one upper and lower pin pair is routed. According to the above analysis, the setting conditions for the design are as follows:

for the single layer "channel routing" problem shown in fig. 5, the steps are as follows:

step 1: first, consider the pin coordinate pair [3,1]]Pin pair [3,1]]In that

The shortest path in the grid may be more than one, and this embodiment randomly selects one of the shortest paths and connects them. Shown in FIG. 6 is a pin pair [3,1]]Among them 3 shortest paths。

Step 2: secondly, aiming at the connection problem of the pin pair [5,4], on the basis of the constraint that the pin pair [3,1] is already wired, namely the connection line of the pin pair [3,1] can be regarded as a 'fence' in the grid, and the wired square is set to be locked, other lines are not allowed to pass through, otherwise, a short circuit is formed, on the basis of the constraint, the shortest path between the pin pair [5,4] is found by adopting a branch and bound algorithm, and is connected to be used as the wiring of the pin pair [5,4 ].

Step 3: finally, at pin pair [3,1]]And pin pair [5,4]]On the basis of connecting a 'fence', a branch-and-bound algorithm is continuously adopted to find a pin pair [3,1]]The shortest path between them, then the entire routing problem is solved. As shown in FIG. 7, is the same as that in FIG. 5

One of the solutions in the wiring space.

Two-layer and two-layer channel wiring

In practice, some integrated circuits cannot be wired with one metal layer (i.e., one wiring space), and multiple metal layers (i.e., multiple wiring spaces) are used, where different metal layers are at different heights, and adjacent layers are connected by vias, so that different metal layers can share the vias without causing short circuits. In the embodiment, two metal layers (i.e., two layers of wiring spaces) are taken as an example to perform "channel wiring" in the wiring space, and the shortest reachable path between the pin pairs and the determination of the positions of the through holes are determined by combining a branch-and-bound algorithm and a backtracking method, so that the total wiring length is minimum. As shown in fig. 8, 1,2, and 3 respectively indicate the upper and lower pin numbers, and pins with the same pin number as the upper and lower pin numbers in fig. 8 need to be connected, and the resistance of one through hole is set to be equal to that of a wire in 5 squares.

Setting the two-layer metal wiring at one

The wiring target is the coordinates of the upper and lower pin pairs [1, 3]]，[5,10]，[6,2]，[8,4]，[12,9]Connecting; with [1, 3]]、[5,10]For example, the 1 st pin from the left side in the upper pins is connected with the 3 rd pin from the left side in the lower pins; meanwhile, the 5 th pin in the upper pins is connected with the 10 th pin in the lower pins, as shown in table 1:

TABLE 1 target layout space size and the connection relationship of the upper and lower pins

First, this embodiment randomly initializes any one pin pair to get the wiring thereof as

And setting the via set as an empty set

. Secondly, at this point

And under the constraint of a fence, finding the shortest reachable path between other pin pairs by adopting a branch-and-bound algorithm. If in the metal layer, the pin pairs are found to be unreachable, then the via set is searched

If the set is an empty set, then the second layer of metal sheet needs to be accessible by constructing vias. If the through hole is collected

If not, the current pin pair to through hole set is firstly solved

The shortest reachable path of any through hole in the plurality of through holes is routed along the shortest path. If the pin pairs are grouped by searching through holes

If there is no accessible via, a new via needs to be drilled. For the searching of the through hole position, a backtracking method is adopted to determine the grid point of the through hole placement. The specific process is as follows:

step 1: first, initialize any pair of pins

The layout mode shown in fig. 9 is obtained, and the set of through holes is set as an empty set

。

Step 2: and sequentially searching the shortest reachable paths of other pins by using a branch limit algorithm.

The search finds that pin 2 is unreachable, and therefore requires a second layer of metal to make it reachable. Finding this time by searching through sets of vias

And thus there are no available vias, two more vias need to be made in the board to allow connection between pins 2.

The selection of the through hole position adopts the following mode:

(1) the search tree shown in fig. 10 and 11 is generated by searching for the top and bottom pins of pin 2 preferentially using the breadth search, and then representing the reachable paths by coordinates (1,4) and (4, 3).

(2) The positions of the through holes can be selected by a backtracking method through the search tree of the pins. Firstly, leaf nodes are selected, the leaf nodes (3,1), (3,2) and (3,3) of the lower pins (1,4) can be obtained to be used as candidate sets of through holes, and the leaf nodes (1,3) of the upper pins (1,4) are used as candidate sets of through holes

If the position with the shortest grid distance is selected as the position of the through hole, the shortest path between the positions of the through holes (3,3) and (1,3) is selected to be 2, that is

Sequentially backtracking the father nodes upwards until all the nodes are traversed, selecting the node with the minimum through hole distance, and putting the position into the through hole set

. Wiring between pin numbers 2

As shown in fig. 12:

finally, the wiring path between the pins 3 is found again, and the unreachable pins 3 can be found through the breadth search algorithm. Then its wiring needs to be implemented through a 2-layer metal plate and vias are needed. First, the upper pins (1,5) and the lower pins (4,2) of the pin 3 are searched to the through hole set by indexing the through hole set

Shortest path of any via in (c). The distances to the top and bottom pin to via set searched by the branch and bound algorithm are shown in table 2:

TABLE 2 distance of pins (1,5) and pins (4,2) to the vias

Therefore, in the embodiment, the through holes (3,2) are selected as the through holes of the lower pins (4,2), and a new through hole needs to be drilled if the upper pins (1,5) have no accessible through holes. The selection of the new via is performed by the above method, and the search tree of the pins (1,5) is traversed by the breadth search first method as shown in fig. 13.

Firstly, leaf nodes (4,7), (3,6), (2,6) and (1,7) are selected as alternative sets of through holes, and the shortest paths from the positions to the through holes (3,2) are calculated, so that the shortest paths can be obtained

，

，

，

. The shortest reachable distance is

. At this time, backtracking is performed to the father node of the leaf node, and candidate sets (4,6), (3,5), (2,5), (1,6) of the through hole positions of the candidate sets are obtained. Calculating the shortest path from these positions to the vias (3,3) to obtain

，

，

，

And (3,5) is selected as the through hole through which the upper pin (1,5) can directly reach when the shortest path distance between the through hole (3,3) and the candidate set (3,5) is the minimum. Adding via locations (3,5) to the set of vias

That is, the wiring of the lead 3 is as shown in fig. 14:

for the above layout, there are cases in which the selection of the via is such that, if both the upper pin and the lower pin can find the corresponding reachable via in the via candidate set, the following assumptions are made. If the wiring distance of the upper metal plate through the through hole satisfies the following formula, we will punch 2 through holes again for wiring:

wherein

Respectively indicate the positions of 2 through holes,

representing the resistance of the via. If wiring in the upper metal layer requires more paths than the resistance required for making a new via, then a new via is chosen.

In summary, the connections of all the pins in table 2 are completed, and the obtained channel wiring result is shown in fig. 15:

third, two-layer channel wiring under distance constraint between through holes

As integrated circuit dimensions shrink, the "via routing" of the two metal layers is resumed according to the routing requirements in table 2, assuming that the new via fabrication process requires that the pitch of any two vias must be 2 grid points or greater.

The euclidean distance is first introduced as the spatial distance between two through holes, as shown in the following equation.

Wherein

Respectively representing the abscissa and ordinate between the 2 through holes. Euclidean distance between two through holes

The operator can meet the requirements of the operator,

for a given distance threshold, this embodiment assumes that the spacing between vias must be greater than 2 grid points to represent where two vias are locatedThe distance between the centers of the grids is greater than or equal to 3, and the arrangement schematic diagram of the qualified through hole intervals is shown in fig. 16.

If the above conditions are to be satisfied, the size of the metal plate also needs to be large enough, and if the size of the metal plate is too small, a suitable through hole cannot be found. This embodiment assumes that the width of the metal plate is at least

The number of rows and columns. Because if the distance threshold is

Then 2 through holes in the same row occupy

Rows are shown in FIG. 16, distance thresholds

It occupies 4 rows or 4 columns, and 1 row each with the addition of upper and lower pins, so that the selection of the via needs to be performed if this condition is satisfied. From these constraints, the constraints are constructed as follows:

wherein, in the step (A),c _iandc _jindicating the position coordinates of the selected two through holes,

to representc _iAndc _jthe distance between them.

Wherein, in the step (A),widthindicating wiring emptyThe width of the gap.

The example shown in fig. 17 is wired, and when selecting the through holes, the principle of the present embodiment is to select the through holes as rightward as possible so as not to affect the pin selection on the left side.

Wiring of pin 1:

first, any pair of pins is initialized

The layout shown in fig. 18 is obtained, and the set of through holes is set as an empty set

。

Wiring of pin 2:

and then, sequentially searching the shortest reachable paths of other pin pairs by using a branch limit algorithm. The search finds that pin 2 is unreachable, and therefore requires a second layer of metal to make it reachable. The via collection is searched to find that it is now an empty collection, and therefore there are no available vias, and two new vias need to be made on the circuit board to allow connection between pins 2.

In general, if the path and Euclidean distance are equal to the minimum threshold, then this via is absolutely the optimal via, and this condition is satisfied if the vias are in the same row or column. Therefore, the present embodiment uses the following method to find the optimal via, first, the upper pin (1,4) is subjected to depth-first search to serve as a candidate via, then, four positions where the euclidean distance in the horizontal or vertical direction of the candidate via is the threshold are found to find whether there is a path that the lower pin (6,3) can reach, the coordinates (1,4) are found according to the order of depth-first search shown in fig. 19, and when (1,3) is found to serve as the candidate set of the upper pin (1,4), the positions related to (1,3) are (1,6), (4, 3). Taking (1,6) and (4,3) as the via candidate set of the lower pin (6,3), and then using a branch-and-bound algorithm to find the paths of the lower pin (6,3) and the candidate set to obtain

，

If not, the search is continued until a location is found, and if found, (4,3) can be used as a via for the lower pin (6, 3). Inserting (1,3) and (6,3) as through holes into the through hole collection, i.e.

. If the upper pin cannot be searched, the lower pin is searched in the same way.

Wiring between pins 2

As shown in fig. 20 below:

for the layout of the pin 2, if a special condition exists, namely the upper, lower, left and right positions of all the upper pins (1,4) are traversed, and the reachable through hole positions of the lower pins (6,3) are not found, the following mode is adopted:

the search tree of the upper pins (1,4) and the lower pins (6,3) of the pin 2 is obtained by the breadth search first method, as shown in fig. 21 and 22.

First, the selection is performed from the leaf nodes, and the leaf nodes (2,2), (2,3), (6,6) and (1,6) of the upper pins (1,4) can be obtained as candidate sets of the through holes, and the leaf nodes (5,4), (4,1), (4,2) and (4,4) of the lower pins (6,3) can be obtained as candidate sets of the through holes. Paths between upper pin via candidate set and lower pin via candidate set respectively

And Euclidean distance

. The results shown in table 3 were obtained:

TABLE 3 Path distance and Euclidean distance between leaf nodes

At the position satisfying the Euclidean distance

If the wiring path is shortest under the condition of being equal to or greater than the threshold, the shortest path between (2,3) and (5,4) is 4, and the distance between the vias is greater than the given threshold, then (2,3) and (5,4) can be used as the via location. And then continuously backtracking to the father node until all the conditions are traversed, and finding the position where the path between the through holes is minimum and all the through holes of the through hole candidate set are larger than the distance threshold value under the condition of meeting the Euclidean distance.

Wiring of the pin 3:

then we look for the 3 rd pin routing and through the branch and bound algorithm can find that pin 3 is unreachable. Then its wiring needs to be implemented through a 2-layer metal plate and vias are needed. First, the upper pins (1,5) and the lower pins (6,2) of the pin 3 are searched to the through hole set by indexing the through hole set

Shortest path of any via in (c). The distances to the top and bottom pin to via set searched by the branch and bound algorithm are shown in table 4:

TABLE 4 distance from Upper and lower pins to the set of vias

Therefore, the through holes (3,2) are selected as the through holes of the lower pins (4,2), and a new through hole needs to be drilled when the upper pins (1,5) have no accessible through holes. The new through hole method firstly determines the Euclidean distance in 4 directions of the through holes (4,3) up, down, left and right

Is used as a through hole for the upper pin (1,5), so that it can be obtained that the Euclidean distance of (4,6) to the through hole (4,3) is

Path is 4, andthe Euclidean distance between the current through hole and other through holes in the through hole set is larger than that of other through holes in the through hole set

. It is therefore possible to use (4,6) as a through-hole for the upper leads (1, 5). Adding via locations (4,6) to a set of vias

。

If the through holes (4,3) have no proper through hole positions on the upper, lower, left and right sides, the following mode is adopted: the reachable positions of the lower pins (1,5) are traversed once by a depth search priority mode, a search tree shown in fig. 23 is used for calculating the positions from the traversed positions to the through holes (4,3), and the positions with the shortest paths are used as the optimal through hole positions under the condition that the Euclidean distances are met.

The results obtained by the search are shown in table 5:

TABLE 5 search results

When the position of (4,6) is excluded, there are two (3,6) and (5, 6). Then, searching the through hole set, and searching whether the two positions and other through holes meet the requirement of Euclidean distance

And if the through holes are satisfied, taking any one of the through holes as the upper pins (1,5) of the through holes. The wiring of pin 3 is shown in fig. 24:

deadlock problem

If a pin causes a deadlock problem as shown in FIG. 25, i.e., the pin represented by the four-star in the figure cannot find a reachable via anyway, because the position of the top-left via is exclusive from the candidate position of the pin, the set of vias is aggregated

The via that is excluded from the pin is deleted and the re-search is performed because the via was deletedThe paths between the affected pin pairs until the vias found are no longer mutually exclusive.

Wiring results

For the routing requirements of table 1, the routing results are as follows:

for example, when the wiring requirements are as shown in table 6, the wiring results obtained by the same method in this case are shown in fig. 26:

TABLE 6 target layout space and pin pairs to be connected

It should be noted that the method of the embodiment of the present invention may be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene and completed by the mutual cooperation of a plurality of devices. In the case of such a distributed scenario, one of the multiple devices may only perform one or more steps of the method according to the embodiment of the present invention, and the multiple devices interact with each other to complete the method.

It should be noted that the above describes some embodiments of the invention. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Based on the same inventive concept as the circuit path wiring method based on the branch-and-bound method in the above embodiments, this embodiment proposes a circuit path wiring device based on the branch-and-bound method, as shown in fig. 27, the device includes:

a network construction module 21, configured to construct a two-dimensional grid in a wiring space;

a marking module 22, configured to mark coordinates of each pin in the circuit diagram in a two-dimensional grid;

a pin pair determining module 23, configured to use pins connected in a circuit diagram as pin pairs, where the circuit diagram includes a plurality of pin pairs;

the path determining module 24 is configured to determine, according to a branch-and-bound method, a wiring path corresponding to the plurality of pin pairs in the circuit diagram;

and a layout module 25 for drawing a circuit layout according to the wiring paths of the respective pin pairs.

In a specific embodiment, the path determining module 24 specifically includes:

the selecting unit is used for selecting a target pin pair from the plurality of pin pairs and determining a wiring path of the target pin pair by using a branch-and-bound method;

and the path determining unit is used for acquiring the next target pin pair, determining the wiring path of which the next target pin pair meets the set condition by using a branch-and-bound method, and continuously iterating the process until all the pin pairs in the circuit diagram determine the corresponding wiring paths.

In a specific embodiment, the apparatus further comprises:

the condition setting module sets setting conditions as follows:

；

wherein the content of the first and second substances,

、

、

respectively represent

Horizontal and vertical coordinates within a two-dimensional network

，

、

To represent

Horizontal and vertical coordinates within a two-dimensional network

，

Representing the wiring path distance of the pin pairs,

indicating the number of pin pairs that the circuit diagram contains,

In a specific embodiment, the path determining module 24 further includes:

the pin coordinate determination unit is used for taking the coordinate of one pin in the pin pair as a reference point and the coordinate of the other pin as a terminal point;

the displacement determining unit is used for determining a square point closest to the end point from at least one square point where the reference point can move as a displacement point, abandoning other square points, continuously iterating the process until the displacement point reaches the end point by taking the displacement point as a new reference point, and determining at least one displacement route corresponding to the target pin pair; and taking the determined at least one displacement route as a wiring path of the pin pair.

In a specific embodiment, a wiring path of a target pin pair is taken as a parent node, a wiring path of a next target pin pair is taken as a child node, and the target pin pair refers to any one of a plurality of pin pairs contained in a circuit diagram;

the path determination unit is specifically configured to:

In a specific embodiment, the pin pairs do not find corresponding wiring paths, the pin pairs are determined to be unreachable pin pairs, wiring is carried out by using a multilayer wiring space, and a through hole set is preset to be an empty set;

the path determining module 24 specifically further includes:

the judging unit is used for determining that the through hole set is a non-empty set, and searching through hole coordinates which can be reached by two pins of the unreachable pin pair from the through hole set to be used as the through hole coordinates of the unreachable pin pair; alternatively, the first and second electrodes may be,

the judging unit is also used for determining that the through hole set is an empty set or determining that the through hole coordinates of the unreachable pin pairs are not found in the through hole set, determining corresponding through hole coordinates for the unreachable pin pairs by using a backtracking method, and adding the through hole coordinates into the through hole set;

the path determining unit is further used for determining that paths of two pins of the unreachable pin pair respectively reaching the through hole coordinates are wiring paths of a first layer of wiring space, and connection paths of the two through hole coordinates are wiring paths of a second layer of wiring space, wherein the second layer of wiring space refers to at least one wiring space except the first layer of wiring space; and searching the wiring path of the next pin pair by using a branch-and-bound algorithm until all the pin pairs in the circuit diagram determine the corresponding wiring paths.

In a specific embodiment, the determining unit specifically includes:

the construction unit is used for respectively constructing corresponding search trees according to reachable paths of two pins of the unreachable pin pairs, wherein reachable coordinates of the two pins of the unreachable pin pairs are used as leaf nodes of the search trees;

the calculating unit is used for calculating the node distance between leaf nodes of the two search trees, wherein the obtained node distance is at least one;

and the adding unit is used for taking the two leaf nodes corresponding to the node distance with the minimum distance value as through hole coordinates and adding the through hole coordinates to the through hole set.

In a specific embodiment, the adding unit is further configured to:

For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the various modules may be implemented in the same one or more software and/or hardware implementations of the invention.

The apparatus of the foregoing embodiment is used to implement a corresponding circuit path wiring method based on a branch-and-bound method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described herein again.

Based on the same inventive concept, corresponding to any embodiment of the method, the invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the program to implement the circuit path wiring method based on the branch-and-bound method according to any embodiment.

Fig. 28 is a schematic diagram illustrating a more specific hardware structure of an electronic device according to this embodiment, where the electronic device may include: a processor 1010, a memory 1020, an input/output interface 1030, a communication interface 1040, and a bus 1050. Wherein the processor 1010, memory 1020, input/output interface 1030, and communication interface 1040 are communicatively coupled to each other within the device via bus 1050.

The processor 1010 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, and is configured to execute related programs to implement the technical solutions provided in the embodiments of the present disclosure.

The Memory 1020 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, or the like. The memory 1020 may store an operating system and other application programs, and when the technical solution provided by the embodiments of the present specification is implemented by software or firmware, the relevant program codes are stored in the memory 1020 and called to be executed by the processor 1010.

The input/output interface 1030 is used for connecting an input/output module to input and output information. The i/o module may be configured as a component in a device (not shown) or may be external to the device to provide a corresponding function. The input devices may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices may include a display, a speaker, a vibrator, an indicator light, etc.

The communication interface 1040 is used for connecting a communication module (not shown in the drawings) to implement communication interaction between the present apparatus and other apparatuses. The communication module can realize communication in a wired mode (such as USB, network cable and the like) and also can realize communication in a wireless mode (such as mobile network, WIFI, Bluetooth and the like).

Bus 1050 includes a path that transfers information between various components of the device, such as processor 1010, memory 1020, input/output interface 1030, and communication interface 1040.

It should be noted that although the above-mentioned device only shows the processor 1010, the memory 1020, the input/output interface 1030, the communication interface 1040 and the bus 1050, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will appreciate that the above-described apparatus may also include only those components necessary to implement the embodiments of the present description, and not necessarily all of the components shown in the figures.

The electronic device of the foregoing embodiment is used to implement a circuit path wiring method based on a branch-and-bound method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which are not described herein again.

Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present invention also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the branch-and-bound method-based circuit path routing method according to any of the above embodiments.

Computer-readable media of the present embodiments, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

The storage medium of the above embodiment stores computer instructions for causing the computer to execute the circuit channel wiring method based on the branch-and-bound method according to any of the above embodiments, and has the beneficial effects of corresponding method embodiments, which are not described herein again.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to those examples; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity.

In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the invention. Furthermore, devices may be shown in block diagram form in order to avoid obscuring embodiments of the present invention, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present invention are to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that embodiments of the invention can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the invention.

Claims

1. A circuit channel wiring method based on a branch-and-bound method is characterized by comprising the following steps:

constructing a two-dimensional grid in a wiring space;

determining the wiring paths corresponding to the plurality of pin pairs in the circuit diagram according to a branch-and-bound method, specifically comprising: taking the coordinate of one pin in the pin pair as a datum point and the coordinate of the other pin as a termination point; determining a square position closest to the termination point from at least one movable square position of the reference point as a displacement point, discarding the rest square positions, continuously iterating the process until the displacement point reaches the termination point by taking the displacement point as a new reference point, and determining at least one displacement route corresponding to the target pin pair; taking the determined at least one displacement route as a wiring path of the pin pair;

drawing a circuit wiring diagram according to the wiring paths of the pin pairs;

the pin pairs do not find corresponding wiring paths, the pin pairs are determined to be inaccessible, wiring is carried out by utilizing a multilayer wiring space, and a through hole set is preset to be an empty set; determining, by the branch-and-bound method, wiring paths corresponding to the plurality of pin pairs in the circuit diagram, which specifically includes:

determining that the through hole set is a non-empty set, and searching through hole coordinates which can be reached by two pins of the unreachable pin pair from the through hole set to be used as the through hole coordinates of the unreachable pin pair; alternatively, the first and second electrodes may be,

determining that the through hole set is an empty set or determining that a through hole coordinate of the unreachable pin pair is not found in the through hole set, determining a corresponding through hole coordinate for the unreachable pin pair by using a backtracking method, and adding the through hole coordinate to the through hole set;

determining that paths of two pins of the unreachable pin pair respectively reaching the through hole coordinates are wiring paths of a first layer of wiring space, and connection paths of the two through hole coordinates are wiring paths of a second layer of wiring space, wherein the second layer of wiring space refers to at least one wiring space except the first layer of wiring space;

and searching the wiring path of the next pin pair by using a branch-and-bound algorithm until all the pin pairs in the circuit diagram determine the corresponding wiring paths.

2. The method according to claim 1, wherein the determining the routing paths corresponding to the plurality of pin pairs in the circuit diagram according to a branch-and-bound method specifically includes:

selecting a target pin pair from a plurality of pin pairs, and determining a wiring path of the target pin pair by using a branch-and-bound method;

and obtaining a next target pin pair, determining the wiring path of the next target pin pair meeting the set condition by using a branch-and-bound method, and continuously iterating the process until all the pin pairs in the circuit diagram determine the corresponding wiring paths.

3. The method according to claim 2, wherein before the obtaining of the next target pin pair, determining the routing path of the next target pin pair satisfying the set condition by using a branch-and-bound method, and continuously iterating the process until all pin pairs in the circuit diagram determine the corresponding routing paths, the method further comprises:

setting the setting conditions as follows:

；

wherein the content of the first and second substances,

、

、

respectively represent

Horizontal and vertical coordinates within the two-dimensional network

，

、

To represent

Horizontal and vertical coordinates within the two-dimensional network

，

Representing the wiring path distance of the pin pairs,

indicating the number of pin pairs that the circuit diagram contains,

4. The method according to claim 2 or 3, wherein the routing path of the target pin pair is a parent node, the routing path of the next target pin pair is a child node, and the target pin pair refers to any one of a plurality of pin pairs included in the circuit diagram;

determining the wiring path of the next target pin pair by using a branch-and-bound method, specifically including:

and determining that the wiring paths of the child nodes obtained by using a branch-and-bound method are zero, searching the corresponding previous father node by taking the father node as the child node by using a backtracking method, deleting the father node until the previous father node is determined to have a plurality of child nodes, selecting one child node from the rest child nodes as the father node, and determining the wiring paths of the corresponding child nodes by using the branch-and-bound method.

5. The method according to claim 1, wherein the determining corresponding via coordinates for the unreachable pin-pairs by a backtracking method, and adding the via coordinates to the via set, specifically comprises:

respectively constructing corresponding search trees according to reachable paths of two pins of the unreachable pin pair, wherein reachable coordinates of the two pins of the unreachable pin pair are used as leaf nodes of the search trees;

calculating the node distance between leaf nodes of the two search trees, wherein the obtained node distance is at least one;

and taking the two leaf nodes corresponding to the node distance with the minimum distance value as through hole coordinates, and adding the through hole coordinates into the through hole set.

6. The method according to claim 5, wherein the two leaf nodes corresponding to the node distance with the smallest distance value are taken as via coordinates, and the via coordinates are added to the via set, and specifically the method further comprises:

taking a node distance which is greater than or equal to a preset distance as a node distance to be selected, wherein the node distance to be selected is at least one;

selecting the distance of the node to be selected with the minimum distance value from at least one distance of the node to be selected as the final node distance;

and taking the two leaf nodes corresponding to the final node distance as through hole coordinates, and adding the through hole coordinates to the through hole set.

7. A circuit channel wiring device based on branch-and-bound method is characterized by comprising:

the path determining module is configured to determine, according to a branch-and-bound method, a wiring path corresponding to a plurality of pin pairs in the circuit diagram, and specifically includes: the pin coordinate determination unit is used for taking the coordinate of one pin in the pin pair as a reference point and the coordinate of the other pin as a terminal point; the displacement determining unit is used for determining a square point closest to the end point from at least one square point where the reference point can move as a displacement point, abandoning other square points, continuously iterating the process until the displacement point reaches the end point by taking the displacement point as a new reference point, and determining at least one displacement route corresponding to the target pin pair; taking the determined at least one displacement route as a wiring path of the pin pair;

the layout module is used for drawing a circuit layout according to the wiring paths of the pin pairs;

the method comprises the following steps that a corresponding wiring path is not found in a pin pair, the pin pair is determined to be an unreachable pin pair, wiring is carried out by utilizing a multilayer wiring space, and a through hole set is preset to be an empty set; the path determining module further includes:

8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 6 when executing the program.