JPS61183923A - Formation of epitaxial layer - Google Patents

Formation of epitaxial layer

Info

Publication number
JPS61183923A
JPS61183923A JP2389885A JP2389885A JPS61183923A JP S61183923 A JPS61183923 A JP S61183923A JP 2389885 A JP2389885 A JP 2389885A JP 2389885 A JP2389885 A JP 2389885A JP S61183923 A JPS61183923 A JP S61183923A
Authority
JP
Japan
Prior art keywords
epitaxial layer
thickness
silicon substrate
oxide film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2389885A
Other languages
Japanese (ja)
Inventor
Yuji Yamanishi
山西　雄司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2389885A priority Critical patent/JPS61183923A/en
Publication of JPS61183923A publication Critical patent/JPS61183923A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To form a thinner epitaxial layer on a substrate having one conductive type, by depositing the epitaxial layer on the substrate and then repeating a heat oxidation process of oxidizing the layer to a predetermined thickness and an etching process of removing the oxidized silicon film for several times. CONSTITUTION:A p-type silicon epitaxial layer 2 is deposited on an n-type silicon substrate 1 to a thickness of 2.5Xm. The substrate is then kept at 1,000 deg.C and heat treated for 1hr within a heating surface supplied with oxygen which has been passed through 95 deg.C water,whereby an oxide film 3 of 3,750Angstrom is formed on the surface of the silicon substrate. The oxide film 3 is completely removed with an etching solution in which HF and NH4F are mixed in the volume ratio of 2:10, whereby the thickness of the epitaxial layer 21 on the silicon substrate is reduced. Repeating these processes of oxidization and of removing an oxide film 3 with the same etching solution, the thickness of the epitaxial layer on the silicon substrate can be further reduced.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、通常のエピタキシャル成長処理では再現性あ
るいは均一性の面などからみて形成することが困難であ
った極めて薄いエピタキシャル層の形成を可能にする方
法に関する。[Detailed Description of the Invention] Industrial Field of Application The present invention is a method that enables the formation of extremely thin epitaxial layers, which are difficult to form in terms of reproducibility or uniformity using ordinary epitaxial growth processes. Regarding.

従来の技術 半導体装置、たとえば、高周波トランジスタの高周波特
性を高めようとした場合、不純物濃度が制御された薄い
ベース層を形成し、この中へエミッタ領域を作り込むこ
とが必要になる。このベース層の形成のために気相成長
によるエピタキシャル成長法が採用されている。In order to improve the high frequency characteristics of a conventional semiconductor device, such as a high frequency transistor, it is necessary to form a thin base layer with a controlled impurity concentration and form an emitter region into this base layer. Epitaxial growth using vapor phase growth is used to form this base layer.

また、気相成長によるエピタキシャル成長法でシリコン
エピタキシャル層を形成する場合、四塩化けい素の水素
還元法あるいはモノシランの熱分解法が採用されている
が、これらの方法では極めて薄いエピタキシャル層を形
成することが困難である。In addition, when forming a silicon epitaxial layer using epitaxial growth using vapor phase growth, hydrogen reduction of silicon tetrachloride or thermal decomposition of monosilane is used, but these methods do not allow for the formation of extremely thin epitaxial layers. is difficult.

すなわち、通常の半導体装置の製造工程におけるエピタ
キシャル層の形成にあたり最適とされる成長速度は、毎
分（１５〜５μｍ程度であるため、たとえば１〜２μｍ
程度のエピタキシャル層を形成しようとするときの成長
処理時間は、秒もしくは分であられされる短い時間とな
る。このような短い成長処理時間の下では、半導体ウェ
ハ相互間は勿論のこと、単一の半導体ウエノ・内におい
てもエピタキシャル層の厚みにばらつきが生じる。In other words, the optimum growth rate for forming an epitaxial layer in a normal semiconductor device manufacturing process is approximately 15 to 5 μm per minute, for example, 1 to 2 μm.
The growth process time when attempting to form an epitaxial layer of about 100 mL is short, measured in seconds or minutes. Under such a short growth processing time, variations in the thickness of the epitaxial layer occur not only between semiconductor wafers but also within a single semiconductor wafer.

また、エピタキシャル成長法の利点は、エピタキシャル
成長層内の不純物濃度を均一化できることにあるが、上
記のような薄い厚みになるとエピタキシャル層中の不純
物濃度の制御の再現性が低下してしまう。さらに、現在
の測定技術では、１〜２μｍ程度まで薄くしたエピタキ
シャル層の膜厚を正確に測定することも困難であり、十
分な膜厚の管理ができない。Further, an advantage of the epitaxial growth method is that the impurity concentration in the epitaxial growth layer can be made uniform, but when the thickness becomes as thin as described above, the reproducibility of controlling the impurity concentration in the epitaxial layer decreases. Furthermore, with current measurement techniques, it is difficult to accurately measure the thickness of an epitaxial layer that is thinned to about 1 to 2 μm, and the thickness cannot be adequately controlled.

発明が解決しようとする問題点 従来のエピタキシャル成長方法では、極めて薄いエピタ
キシャル層を、その厚さ、不純物濃度が均一化された状
態で形成することができないため、薄いエピタキシャル
層を必要とする半導体装置の製造が困難であり、また、
半導体装置を製造したとしても特性のばらつきが大きく
１歩留りの低下が避けられなかった。Problems to be Solved by the Invention Conventional epitaxial growth methods cannot form extremely thin epitaxial layers with uniform thickness and impurity concentration. It is difficult to manufacture, and
Even if semiconductor devices were manufactured, variations in characteristics were large and a drop in yield was unavoidable.

問題点を解決するだめの手段 本発明のエピタキシャル層の形成方法は、−導電形ノシ
リコン基板上にエピタキシャル層を成長させたのち、こ
のシリコン基板に、エピタキシャル層の全域を所定の厚
みだけ酸化させる熱酸化工程と形成された酸化シリコン
膜を除去するエツチング工程とからなる処理を複数回施
し、エピタキシャル層の厚みを成長直後の厚みよりも減
少させる方法である。Means to Solve the Problems The method for forming an epitaxial layer of the present invention includes: - After growing an epitaxial layer on a conductivity type silicon substrate, the entire area of the epitaxial layer is oxidized to a predetermined thickness on this silicon substrate. This is a method in which a process consisting of a thermal oxidation process and an etching process to remove the formed silicon oxide film is performed multiple times to reduce the thickness of the epitaxial layer from the thickness immediately after growth.

作　　用 このエピタキシャル成長方法によれば、通常の方法では
得ることが困難であった薄いエピタキシャル層を形成す
ることが可能になる。Function: According to this epitaxial growth method, it is possible to form a thin epitaxial layer, which is difficult to obtain using conventional methods.

実施例 以下に図面を参照して本発明のエピタキシャル層の成長
方法について詳細に説明する。EXAMPLES The method for growing an epitaxial layer of the present invention will be described in detail below with reference to the drawings.

第１図〜第５図は、本発明のエピタキシャル成長方法に
よりエピタキシャル層を形成する過程を示す図であり、
先ず、第１図で示すようにｎ形のシリコン基板１の上に
ｐ形のシリコンエピタキシャル層２を２．５μｍの厚さ
に成長させる。エピタキシャル層の厚みの正確な測定は
この程度までが限界であり、これよりも薄くなると測定
が困難となシ、測定に時間がかかる。次いで、１０００
’Ｃに保たれ、しかも、９５°Ｃの水の中に通過させた
酸素が供給される加熱炉内でシリコン基板を１時間にわ
たシ加熱処理する。この処理によって、シリコン基板の
表面には３７５０人の酸化膜３が形成される（第２図）
。こののち、フッ酸（ＨＦ）とフッ化アンモニウム（Ｎ
Ｈ４Ｆ）を容量比で２：１０の割合で混合させて形成し
たエツチング液を用いて酸化膜３をすべて除去すること
により第３図で示すようだ厚みが減少したエピタキシャ
ル層２１をもつシリコン基板が得られる。この過程を経
て、第１回目の処理が終了する。1 to 5 are diagrams showing the process of forming an epitaxial layer by the epitaxial growth method of the present invention,
First, as shown in FIG. 1, a p-type silicon epitaxial layer 2 is grown to a thickness of 2.5 μm on an n-type silicon substrate 1. Accurate measurement of the thickness of the epitaxial layer is limited to this extent; if it becomes thinner than this, measurement becomes difficult and takes time. Then 1000
The silicon substrate is heat-treated for one hour in a heating furnace maintained at 95°C and supplied with oxygen passed through 95°C water. Through this process, an oxide film 3 of 3,750 layers is formed on the surface of the silicon substrate (Figure 2).
. After this, hydrofluoric acid (HF) and ammonium fluoride (N
By removing all the oxide film 3 using an etching solution prepared by mixing H4F) at a volume ratio of 2:10, a silicon substrate with an epitaxial layer 21 whose thickness has been reduced as shown in FIG. 3 is obtained. can get. After this process, the first process is completed.

第４図および第５図は第２回目の処理の過程を示す図で
あり、上記の条件と同一の条件で加熱処理を施して酸化
膜３を形成しく第３図）、次いで。FIGS. 4 and 5 are diagrams showing the process of the second treatment, in which heat treatment is performed under the same conditions as above to form the oxide film 3 (FIG. 3), and then.

この酸化膜３を上記と同一のエツチング液を用いて除去
することにより、さらに厚みが減少したエピタキシャル
層２２をもつシリコン基板が得られる０ 以上、第２回目の処理までを説明したが、第８同日寸で
のＩＪｆＬＩ！！ｌ！をｍ＋−た結果、１．５μｍの厚
みだけエピタキシャル層が除去され、１．０μｍのエピ
タキシャル層が表面に形成された。By removing this oxide film 3 using the same etching solution as above, a silicon substrate having an epitaxial layer 22 with a further reduced thickness can be obtained. IJfLI on the same day! ! l! As a result, the epitaxial layer was removed by a thickness of 1.5 μm, and an epitaxial layer of 1.0 μm was formed on the surface.

以上の過程を経て形成したエピタキシャル層をベース層
として利用した８　００　ＭＨｚ帯用のｎｐｎトランジ
スタを製作したところ、良好な高周波特性を得ることが
できた。When an npn transistor for the 800 MHz band was manufactured using the epitaxial layer formed through the above process as a base layer, good high frequency characteristics could be obtained.

なお、以上の説明では、８回の処理をくり返して所望の
厚みをうる場合を例示したが、この回数は特に限られる
ものではない。ただし、酸化のための加熱処理工程で、
エピタキシャル層中の不純物が酸化膜あるいはシリコン
基板の中ヘオートドープすることを極力避けるよう配慮
することが大切である。周知のように、熱酸化膜の成長
は、一定時間が経過したのちは放物線刻に従う。このた
め、厚い熱酸化膜を成長させようとした場合には極めて
長い熱処理が必要とされ、このような長時間にわたる熱
処理を施すと上記のオートドープ現象が顕著となる。こ
の不都合を避けるため熱酸化処理を複数回に分けること
により、比較的短い時間で実質的に厚い熱酸化膜を成長
させたのと同等の結果を得ることができる。In addition, in the above description, the case where the desired thickness is obtained by repeating the process eight times was illustrated, but this number of times is not particularly limited. However, in the heat treatment process for oxidation,
It is important to take care to avoid autodoping of impurities in the epitaxial layer into the oxide film or silicon substrate as much as possible. As is well known, the growth of a thermal oxide film follows a parabolic curve after a certain period of time has elapsed. For this reason, when attempting to grow a thick thermal oxide film, an extremely long heat treatment is required, and when such a long heat treatment is performed, the above-mentioned autodoping phenomenon becomes noticeable. In order to avoid this inconvenience, by dividing the thermal oxidation treatment into multiple steps, it is possible to obtain a result equivalent to growing a substantially thick thermal oxide film in a relatively short period of time.

発明の詳細 な説明した本発明のエピタキシャル成長方法によれば、
不純物濃度が均一で、しかも、厚みが極めて薄いエピタ
キシャル層をシリコン基板上に再現性よく成長させるこ
とが可能となり、半導体装置の性能を大幅に高める効果
が奏される。特に、本発明を高周波用半導体装置の製造
に適用するならば、高周波特性の改善と製造歩留りの向
上をはかる効果が奏される。According to the epitaxial growth method of the present invention described in detail,
It becomes possible to grow an epitaxial layer with a uniform impurity concentration and an extremely thin thickness on a silicon substrate with good reproducibility, which has the effect of significantly improving the performance of a semiconductor device. In particular, if the present invention is applied to the manufacture of high-frequency semiconductor devices, the effects of improving high-frequency characteristics and manufacturing yield can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図〜第５図は、本発明のエピタキシャル層の形成方
法を説明するだめの製造過程を示す図である。 １・・・・・・ｎ形シリコン基板、２，２１．２２・・
・・・・□ｐ形エピタキシャル層、３・・・・・・酸化
膜。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図 ？ 第２図1 to 5 are diagrams showing the manufacturing process for explaining the method of forming an epitaxial layer of the present invention. 1... N-type silicon substrate, 2, 21.22...
...□p-type epitaxial layer, 3... oxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure? Figure 2

Claims (1)

【特許請求の範囲】[Claims] 　シリコン基板上にエピタキシャル層を成長させたのち
、同シリコン基板に、エピタキシャル層の全域を所定の
厚みだけ酸化させる熱酸化工程と形成された酸化シリコ
ン膜を除去するエッチング工程とからなる処理を複数回
施し、前記エピタキシャル層の厚みを成長直後の厚みよ
りも減少させる工程を有することを特徴とするエピタキ
シャル層の形成方法。After growing an epitaxial layer on a silicon substrate, the same silicon substrate is subjected to multiple treatments consisting of a thermal oxidation process in which the entire area of the epitaxial layer is oxidized to a predetermined thickness, and an etching process to remove the formed silicon oxide film. A method for forming an epitaxial layer, comprising the step of reducing the thickness of the epitaxial layer from the thickness immediately after growth.
JP2389885A 1985-02-08 1985-02-08 Formation of epitaxial layer Pending JPS61183923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2389885A JPS61183923A (en) 1985-02-08 1985-02-08 Formation of epitaxial layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2389885A JPS61183923A (en) 1985-02-08 1985-02-08 Formation of epitaxial layer

Publications (1)

Publication Number Publication Date
JPS61183923A true JPS61183923A (en) 1986-08-16

Family

ID=12123275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2389885A Pending JPS61183923A (en) 1985-02-08 1985-02-08 Formation of epitaxial layer

Country Status (1)

Country Link
JP (1) JPS61183923A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399230A (en) * 1992-06-05 1995-03-21 Hitachi, Ltd. Method and apparatus for etching compound semiconductor
US5527417A (en) * 1992-07-06 1996-06-18 Kabushiki Kaisha Toshiba Photo-assisted CVD apparatus
KR100504163B1 (en) * 2002-09-12 2005-07-27 주성엔지니어링(주) SOI substrate and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399230A (en) * 1992-06-05 1995-03-21 Hitachi, Ltd. Method and apparatus for etching compound semiconductor
US5527417A (en) * 1992-07-06 1996-06-18 Kabushiki Kaisha Toshiba Photo-assisted CVD apparatus
KR100504163B1 (en) * 2002-09-12 2005-07-27 주성엔지니어링(주) SOI substrate and method of manufacturing the same

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