JPS62198118A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62198118A
JPS62198118A JP3991686A JP3991686A JPS62198118A JP S62198118 A JPS62198118 A JP S62198118A JP 3991686 A JP3991686 A JP 3991686A JP 3991686 A JP3991686 A JP 3991686A JP S62198118 A JPS62198118 A JP S62198118A
Authority
JP
Japan
Prior art keywords
wafers
furnace
steps
thin film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3991686A
Other languages
Japanese (ja)
Other versions
JPH0797562B2 (en
Inventor
Yuuji Toshiro
勇治 十代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP3991686A priority Critical patent/JPH0797562B2/en
Publication of JPS62198118A publication Critical patent/JPS62198118A/en
Publication of JPH0797562B2 publication Critical patent/JPH0797562B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve the reliability of a semiconductor element and to manufacture a semiconductor device having high yield by uniformizing thermal energy applied to wafers after finishing two steps of forming a thin polycrystalline film by a reduced pressure CVD method and adding an impurity to the thin polycrystalline film by a vapor diffusing method. CONSTITUTION:In the steps of forming a conductive layer, the total C of ther mal energy distributions A, B of a furnace 1 applied to wafers 2 after finishing two steps of forming a thin polycrystalline film and adding an impurity while holding the uniformity of the film thickness in the forming step and the uniform ity of resistors in the adding step. As a result, the diameters of the particles on the many wafers 2 after finishing vapor diffusing step can be fallen within the range approx. 2,000-3,000Angstrom , and the irregularity becomes very small. There fore, the diameter of the particles, the thickness and the resistances of thin polycrystalline film after finishing the two steps all become uniform among the wafers 2, and the reflectively and the oxidizing velocity of the film all become uniform among the wafers 2.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置特に導電層を有する高歩留シ高信頼
性の半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to a method for manufacturing a high-yield, highly reliable semiconductor device having a conductive layer.

従来の技術 半導体装置における導電層形成方法のひとつに減圧CV
D法により、例えばポリシリコン等の多結晶薄膜を形成
し、続いて気相拡散法により前記多結晶薄膜に例えばリ
ン等の不純物添加を行ない前記多結晶薄膜を低抵抗化す
る方法がある。
Conventional technology Low pressure CV is one of the methods for forming conductive layers in semiconductor devices.
There is a method in which a polycrystalline thin film such as polysilicon is formed by the D method, and then an impurity such as phosphorus is added to the polycrystalline thin film by a vapor phase diffusion method to lower the resistance of the polycrystalline thin film.

第2図はこの方法の従来の技術による各工程炉の熱エネ
ルギー分布の一例を示している。各ウェハに与える熱エ
ネルギーは温度と時間の積で与えられるので、この熱エ
ネルギー分布は各炉に設定される温度分布により決定さ
れる。
FIG. 2 shows an example of the thermal energy distribution of each process furnace according to the conventional technique of this method. Since the thermal energy given to each wafer is given by the product of temperature and time, this thermal energy distribution is determined by the temperature distribution set in each furnace.

第2図aは減圧CVD炉および拡散炉内に挿入された多
数のウェハを模式的に示しだもので、炉1中にウェハ2
がボート3に載置された状態で反応ガス4が送られる。
FIG. 2a schematically shows a large number of wafers inserted into a low-pressure CVD furnace and a diffusion furnace.
The reaction gas 4 is sent while the is placed on the boat 3.

同図すおよび同図Cはそれぞれ減圧cvn炉および拡散
炉に設定される熱エネルギー分布、同図d中の実線は同
図すおよび同図Cに示した熱エネルギー分布をたし合わ
せた分布を示している。なお同図d中の破線は同図すお
よび同図Cの分布をそのまま示したものである。
Figure 1 and Figure C show the thermal energy distribution set in the reduced pressure CVN furnace and diffusion furnace, respectively. It shows. Note that the broken line in d of the same figure shows the distribution of FIG. 1 and C of the same figure as is.

同図b −cの横軸のウニノ・位置は同図4のウェハ位
置と対応している。
The position on the horizontal axis in b-c in FIG. 4 corresponds to the wafer position in FIG. 4.

一般に減圧CVD法による多結晶薄膜形成工程において
は、減圧CvD炉内に挿入された多数のウェハ上で多結
晶薄膜膜厚が同一となるように前記炉の温度分布が決定
される。同様にして気相拡散法による多結晶薄膜への不
純物添加では、拡散炉に挿入された多数のウェハ上で前
記多結晶薄膜の抵抗が同一となるように前記炉の温度分
布が決定される。したがって各戸の温度分布はそれぞれ
独立に決定されるため、前記2つの工程終了後でウェハ
に与えた熱エネルギーは第2図dに示すようにウェハ間
での不均一が生じる。
Generally, in a process of forming a polycrystalline thin film using a low pressure CVD method, the temperature distribution of the low pressure CVD furnace is determined so that the thickness of the polycrystalline thin film is the same on a large number of wafers inserted into the low pressure CVD furnace. Similarly, when adding impurities to a polycrystalline thin film using the vapor phase diffusion method, the temperature distribution of the furnace is determined so that the resistance of the polycrystalline thin film is the same on a large number of wafers inserted into the diffusion furnace. Therefore, since the temperature distribution of each house is determined independently, the thermal energy applied to the wafers after the completion of the two steps described above is non-uniform among the wafers, as shown in FIG. 2d.

発明が解決しようとする問題点 以上のように前記2つの工程終了後で、各ウェハに与え
た熱エネルギーにウニノ・間での不均一が生じているた
め、前記2つの工程終了後多結晶薄膜の粒径がウニノ・
間で不均一になる。
Problems to be Solved by the Invention As mentioned above, after the completion of the above two steps, there is non-uniformity in the thermal energy applied to each wafer. The particle size of
unevenness between the two.

例えば減圧CT/D法によシ膜厚4000人のポリシリ
コン膜の成長工程において、炉の入口と奥で30℃の温
度差を設定した場合、成長後のポリシリコンの粒径は炉
の入口と奥のウニノ\上で500〜3000人程度の範
囲でばらつく。さらに次工程の気相拡散法による不純物
添加工程で1ooO℃程度の熱処理が加わることにより
、結晶粒が2〜3倍に成長しバラツキの範囲はさらに大
きくなる。気相拡散工程終了後での結晶粒径のバラツキ
は500%以上にも及ぶ。
For example, in the process of growing a polysilicon film with a thickness of 4,000 using the reduced pressure CT/D method, if a temperature difference of 30°C is set between the entrance and the back of the furnace, the grain size of the polysilicon after growth will be The numbers vary between 500 and 3,000 people at the top of Unino in the back. Furthermore, by adding a heat treatment of about 100° C. in the next step of adding impurities using a vapor-phase diffusion method, the crystal grains grow two to three times, and the range of variation becomes even larger. The variation in crystal grain size after the completion of the gas phase diffusion step is as much as 500% or more.

その結果、例えば多結晶薄膜の反射率に不均一が生じ、
以後のマスク合わせ工程におけるレジスト露光において
レジスト寸法に不均一が生じたり、多結晶薄膜の上層部
を熱酸化して層間絶縁膜を形成する場合に、酸化速度の
違いから酸化膜厚の不均一が生じる等の問題が起こる。
As a result, for example, the reflectance of a polycrystalline thin film becomes non-uniform,
Non-uniform resist dimensions may occur during resist exposure in the subsequent mask alignment process, or non-uniform oxide film thickness may occur due to differences in oxidation speed when forming an interlayer insulating film by thermally oxidizing the upper layer of a polycrystalline thin film. Problems such as this occur.

問題点を解決するだめの手段 前記問題点を解決するために本発明による半導体装置の
製造方法では、前記2つの工程終了後で各ウェハに与え
た熱エネルギーを均一にする。すなわち各工程における
膜厚および抵抗の均一性を保ちつつ、かつ前記2つの工
程でウェハに与える熱エネルギーの合計がウニノ・間で
等しくなるように各戸の温度分布を設定することにより
、前記2つの工程終了後の多結晶薄膜の粒径を均一にす
ることが可能である。
Means for Solving the Problems In order to solve the above-mentioned problems, in the method of manufacturing a semiconductor device according to the present invention, the thermal energy applied to each wafer is made uniform after the completion of the above-mentioned two steps. In other words, while maintaining the uniformity of film thickness and resistance in each process, the temperature distribution of each unit is set so that the total thermal energy given to the wafer in the two processes is equal between the two processes. It is possible to make the grain size of the polycrystalline thin film uniform after the process is completed.

作用 本発明による半導体装置の製造方法によれば、前記2つ
の工程終了後での多結晶薄膜の粒径が均一であるため、
前記多結晶薄膜の反射率がウェハ間で均一であり、以後
のマスク工程におけるレジスト寸法のバラツキを低減す
ることが可能である。
Effect: According to the method of manufacturing a semiconductor device according to the present invention, the grain size of the polycrystalline thin film after the completion of the two steps is uniform;
The reflectance of the polycrystalline thin film is uniform between wafers, and it is possible to reduce variations in resist dimensions in subsequent mask steps.

また前記多結晶薄膜の上層部を熱酸化して眉間絶縁膜を
形成する場合にも酸化速度が均一であるため、酸化膜厚
に不均一が生じないなど、素子の信頼性を向上し、歩留
まりの高い半導体装置の製造が可能である。
Furthermore, even when the upper layer of the polycrystalline thin film is thermally oxidized to form the glabellar insulating film, the oxidation rate is uniform, so there is no unevenness in the oxide film thickness, improving device reliability and increasing yield. It is possible to manufacture semiconductor devices with high performance.

実施例 第1図に本発明による導電層形成工程の各戸の熱エネル
ギー分布の一例を示す。
Embodiment FIG. 1 shows an example of the thermal energy distribution for each house in the conductive layer forming process according to the present invention.

第1図aは減圧(、vD炉および拡散炉内に挿入された
多数のウェハを模式的に示したもので、従来のものと同
じ構成である。同図すおよび同図Cはそれぞれ減圧CV
D炉および拡散炉に設定される熱エネルギー分布、同図
dの実線は同図すおよび同図Cに示した熱エネルギー分
布をたし合わせた分布を示している。なお同図dの破線
は同図すおよび同図Cの分布をそのまま示したものでち
る。
Figure 1a schematically shows a large number of wafers inserted into a vacuum CVD furnace and a diffusion furnace, which have the same configuration as the conventional one.
The thermal energy distribution set in the D furnace and the diffusion furnace, the solid line d in the same figure shows the distribution that is the sum of the thermal energy distributions shown in the same figure and in the same figure C. Note that the broken line in d in the same figure shows the distributions in d and c in the same figure as they are.

第1図dに示すように前記2つの工程でウニ/・に与え
られた熱エネルギーは均一である。本実施例は多結晶薄
膜形成工程における膜厚の均一性および不純物添加工程
における抵抗の均一性を保ちつつ、前記2つの工程終了
後でのウニノ・に与える熱エネルギーが均一となるよう
にしたもので、各戸の温度分布を設定することにより幾
通りもの組合せが可能である。
As shown in Figure 1d, the thermal energy given to the sea urchins in the two steps is uniform. In this example, the uniformity of the film thickness in the polycrystalline thin film formation process and the uniformity of resistance in the impurity addition process are maintained, while the thermal energy applied to the unino after the completion of the above two processes is made uniform. By setting the temperature distribution of each house, many combinations are possible.

この結果、気相拡散工程終了後の多数のウニ・・上での
粒径は2000〜3000八程度におさめることが可能
でバラツキは60%と従来の10分の1以下になり極め
て小さくなる。
As a result, the particle size on a large number of sea urchins after the vapor phase diffusion process can be kept to about 2000 to 30008, and the variation is 60%, which is less than one-tenth of the conventional value, which is extremely small.

したがって、前記2つの工程終了後での多結晶薄膜の粒
径および膜厚、抵抗がすべてウェハ間で均一となる。こ
の結果、多結晶薄膜の反射率や酸化速度がすべてのウェ
ハで均一となり、信頼性及び歩留まりの高い半導体装置
の製造が可能である。
Therefore, the grain size, film thickness, and resistance of the polycrystalline thin film after the above two steps are all uniform between wafers. As a result, the reflectance and oxidation rate of the polycrystalline thin film are uniform across all wafers, making it possible to manufacture semiconductor devices with high reliability and yield.

発明の効果 上記実施例から明らかなように、本発明の半導体装置の
製造方法によれば、信頼性の高い半導体装置を高歩留ま
シで製造することが可能である。
Effects of the Invention As is clear from the above embodiments, according to the method of manufacturing a semiconductor device of the present invention, it is possible to manufacture a highly reliable semiconductor device at a high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による半導体装置の製造方法を示す実施
例の模式図及び熱エネルギー分布図、第2図は従来例の
模式図及び熱エネルギー分布図である。 1・・・・・・炉、2・・・・・・ウェハ、3・・・・
・・ボート、4・・・・・・反応ガス。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図         /−炉 ウェハ位置 ウニ△位亙 ウニ八位!
FIG. 1 is a schematic diagram and a thermal energy distribution diagram of an embodiment showing the method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is a schematic diagram and a thermal energy distribution diagram of a conventional example. 1...Furnace, 2...Wafer, 3...
...Boat, 4...Reactant gas. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure /- Furnace wafer position sea urchin △ position 亙 sea urchin 8th place!

Claims (3)

【特許請求の範囲】[Claims] (1)減圧CVD法による多結晶薄膜形成工程と気相拡
散法による前記多結晶薄膜への不純物添加工程とを含み
、前記多結晶薄膜形成工程における減圧CVD炉温度分
布および前記不純物添加工程における拡散炉温度分布を
、前記2つの炉に挿入される多数のウェハの夫々に与え
る熱エネルギーが前記2つの工程終了後に同一になるよ
うに設定することを特徴とする半導体装置の製造方法。
(1) Includes a step of forming a polycrystalline thin film by a low pressure CVD method and a step of adding impurities to the polycrystalline thin film by a vapor phase diffusion method, and includes a low pressure CVD furnace temperature distribution in the polycrystalline thin film forming step and diffusion in the impurity addition step. A method for manufacturing a semiconductor device, characterized in that the furnace temperature distribution is set so that the thermal energy applied to each of a large number of wafers inserted into the two furnaces is the same after the two steps are completed.
(2)減圧CVD炉の温度分布を前記減圧CVD炉に挿
入される多数のウェハ上に形成される多結晶薄膜膜厚が
同一となるように設定する特許請求の範囲第1項記載の
半導体装置の製造方法。
(2) The semiconductor device according to claim 1, wherein the temperature distribution of the low pressure CVD furnace is set so that the thickness of the polycrystalline thin film formed on a large number of wafers inserted into the low pressure CVD furnace is the same. manufacturing method.
(3)拡散炉の温度分布を前記拡散炉に挿入される多数
のウェハ上に形成される多結晶薄膜の抵抗が同一となる
ように設定する特許請求の範囲第1項又は第2項記載の
半導体装置の製造方法。
(3) The temperature distribution of the diffusion furnace is set so that the resistance of the polycrystalline thin film formed on a large number of wafers inserted into the diffusion furnace is the same. A method for manufacturing a semiconductor device.
JP3991686A 1986-02-25 1986-02-25 Method for manufacturing semiconductor device Expired - Lifetime JPH0797562B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3991686A JPH0797562B2 (en) 1986-02-25 1986-02-25 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3991686A JPH0797562B2 (en) 1986-02-25 1986-02-25 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS62198118A true JPS62198118A (en) 1987-09-01
JPH0797562B2 JPH0797562B2 (en) 1995-10-18

Family

ID=12566259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3991686A Expired - Lifetime JPH0797562B2 (en) 1986-02-25 1986-02-25 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0797562B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132822A (en) * 1988-11-14 1990-05-22 Mitsumi Electric Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132822A (en) * 1988-11-14 1990-05-22 Mitsumi Electric Co Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH0797562B2 (en) 1995-10-18

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