JPS6118126A - P-n junction forming method - Google Patents
P-n junction forming methodInfo
- Publication number
- JPS6118126A JPS6118126A JP13964984A JP13964984A JPS6118126A JP S6118126 A JPS6118126 A JP S6118126A JP 13964984 A JP13964984 A JP 13964984A JP 13964984 A JP13964984 A JP 13964984A JP S6118126 A JPS6118126 A JP S6118126A
- Authority
- JP
- Japan
- Prior art keywords
- type
- impurities
- junction
- layer
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title description 16
- 239000012535 impurity Substances 0.000 claims abstract description 32
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 150000001875 compounds Chemical class 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 3
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 206010013496 Disturbance in attention Diseases 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 231100000614 poison Toxicity 0.000 description 1
- 230000007096 poisonous effect Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〈発明の技術分野〉
本発明ｔ／′１ＧａＡｓ、ＩｎＰ等の化合物結晶中に、
イオン注入法を用すてｐ−ｎ接合を形成する方法の改良
に関するものである。[Detailed Description of the Invention] <Technical Field of the Invention> In the compound crystal of the present invention t/'1 GaAs, InP, etc.,
This invention relates to an improvement in a method of forming a pn junction using an ion implantation method.
〈発明の技術的背景とその問題点〉
ＧａＡｓ半導体は、電子移動度や飽和ドリフト速度が大
きいので高周波用・高速演算用デバイスに適しており、
活発な開発が行われている。Ｓｉ＋イオン注入によるｈ
層の形成技術はすでに確立されており、ｎチャネル層を
有するＧａＡｓ１用いたＭＥＳＦＥＴ ｔ／ｉ、例えば
高周波用デバイスとして多く用いられている。<Technical background of the invention and its problems> GaAs semiconductors have high electron mobility and saturation drift velocity, so they are suitable for high-frequency and high-speed calculation devices.
Active development is underway. h due to Si+ ion implantation
The layer formation technology has already been established, and MESFET t/i using GaAs1 having an n-channel layer is often used as a high frequency device, for example.
一方、Ｚｎ＋４オン注入によるｐ層の形成は、その大き
な熱拡散係数（よる濃度プロファイルの再現性不良や、
急峻な濃度プロファイルが得られにくいという問題があ
シ、赤外線ランプアニールやＺｎ−ＡＳの二重注入法、
あるいは砒素圧印加キャップレスアニールなどが試みら
れているが、満足すべき結果は得られていない。On the other hand, formation of the p-layer by Zn+4 on-implantation has a large thermal diffusion coefficient (due to poor concentration profile reproducibility,
There is a problem that it is difficult to obtain a steep concentration profile, so infrared lamp annealing and Zn-AS double injection method,
Alternatively, capless annealing by applying arsenic pressure has been attempted, but satisfactory results have not been obtained.
又、イオン注入法によるｐ−ｎ接合形成は、■ ｎ型不
純物イオン注入→アニール→ｐ型不Ｍ物イオン注入→ア
ニール
■ ｎ型不純物イオン注入→ｐ型不純物イオン注入→砒
素圧印加キャップレスアニール
等の工程によって行われるが、上記■の方法は工程上の
手間が多くかかり、かつ基板の熱変成が多くなって接合
特性が劣化するという問題がある。In addition, p-n junction formation by the ion implantation method is as follows: ■ n-type impurity ion implantation → annealing → p-type impurity ion implantation → annealing ■ n-type impurity ion implantation → p-type impurity ion implantation → arsenic pressure application capless annealing However, the above-mentioned method (1) requires a lot of time and effort, and there is a problem that thermal deformation of the substrate increases, resulting in deterioration of bonding characteristics.
また■の方法／／′１ＡｓＨ（アルシンガス）の様な猛
毒ガスを用いる為安全上の問題がある、という欠点を有
していた。In addition, method (2)//'1 has the drawback of using a highly poisonous gas such as AsH (arsine gas), which poses a safety problem.
上記■の工程を用いて形成した従来法での注入層のキャ
リア濃度プロファイルの例を第５図に示向に異常拡散し
てｐ ＝ｎ接合が形成されていない事がわかる。FIG. 5 shows an example of the carrier concentration profile of the injection layer formed by the conventional method using the process (2) above. It can be seen that no p=n junction is formed due to abnormal diffusion in the direction.
〈発明の目的〉
本発Ｆ！Ａは上記の問題点全解決すべく、高品質のｐ−
ｎ接合を少ない工程で再現性良く安全に形成するｐ−ｎ
接合の形成方法を提供する←ニーーーこ七ヲ目的として
成されたものであり、この目的を達成するため、本発明
はｐ型及びｎ型の両導電型不純物をイオン注入した化合
物半導体に対し、保護膜付同時アニールを施すことにょ
シ、両導電型不純物を同時に活性化させ、深さ方向に接
合を形成せしめるように成されている。<Purpose of the invention> The original F! In order to solve all of the above problems, A is a high quality p-
p-n that safely forms n-junctions with good reproducibility in fewer steps
The purpose of this invention is to provide a method for forming a junction, and in order to achieve this purpose, the present invention provides a method for forming a junction. By performing simultaneous annealing with a protective film, impurities of both conductivity types are simultaneously activated and a junction is formed in the depth direction.
即ち、本発８Ａはｐ型、ｎ型側導電型不純物を注入した
化合物半導体を保護膜（例えばプラズマＣＶＤによる窒
化硅素膜）を付けて一度アニールすることによシ、注入
不純物固相拡散の少ないｐ−ｎ接合を形成し、あわせて
工程数の削減や基板の熱変成の抑制、及び作業の安全性
を図るようにしたものである。That is, in the present invention 8A, a compound semiconductor into which p-type and n-type conductivity type impurities are implanted is attached with a protective film (for example, a silicon nitride film by plasma CVD) and annealed once, thereby reducing the solid-phase diffusion of the implanted impurities. A pn junction is formed, and the number of steps is reduced, thermal deformation of the substrate is suppressed, and work safety is achieved.
〈発明の実施例〉
以下、図面を参照して本発明の一実施例を図面を参照し
て詳細に説明する。<Embodiment of the Invention> Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
第１図乃至第３図は本発明によるｐ−ｎ接合の形成工程
の説明に供する図である。FIGS. 1 to 3 are diagrams for explaining the process of forming a pn junction according to the present invention.
本発明によるｐ−ｎ接合の形成工程は次の通りである。The steps for forming a pn junction according to the present invention are as follows.
まず、第１図に示すように半絶縁性ＧａＡｓ基板２にｎ
型不純物として、例えばＳｔ＋イオン全レジストにより
形成された選択注入用マスク１を介して注入して
° ｎ型不純物Ｓけ注入層３を形成し、
次に第２図に示すように同一領域にｐ型不純物として、
例えばＺｎ＋イオンをレジストにより形成された選択注
入用マスク４を介して二重注入してｐ型不純物Ｚ＋注入
層全形成する。その後第３図に示すようにＧａＡｓ基板
２上に７二−ル用保護膜６、例えばプラズマｃＶＤ法に
よって厚さ７００Ａの窒化シリコン膜を付着させ、窒素
雰囲気中でアニールを、例えば８８０℃で１５分間行な
い、ｐ型不純物とｎ型不純物を同時に活性化させてｎ型
層７及びｐ型層８を形成して、深さ方向にｐ−ｎ接合全
形成させる。上記の如き本発明による工程を用いて形成
したｐ−ｎ接合のキャリア濃度プロファイルを第４図に
示す。First, as shown in FIG. 1, a semi-insulating GaAs substrate 2 is
As a type impurity, for example, St+ ions are implanted through a selective implantation mask 1 formed entirely of resist.
° Forming an n-type impurity S injection layer 3,
Next, as shown in Figure 2, as a p-type impurity in the same region,
For example, Zn+ ions are double-implanted through a selective implantation mask 4 formed of resist to form the entire p-type impurity Z+ implanted layer. Thereafter, as shown in FIG. 3, a 700A silicon nitride film, for example, a silicon nitride film with a thickness of 700A, is deposited on the GaAs substrate 2 by plasma CVD method, and annealed in a nitrogen atmosphere at, for example, 880°C for 15 minutes. The p-type impurity and the n-type impurity are activated simultaneously to form the n-type layer 7 and the p-type layer 8, thereby forming the entire p-n junction in the depth direction. FIG. 4 shows a carrier concentration profile of a pn junction formed using the process according to the present invention as described above.
この第４図からも明らかなように、上記実施例によれば
注入不純物の理論分布に近い急峻なアクセプタ濃度分布
が得られており、イオン注入法によ多形成しｔｃｐ −
ｎ接合として理想的な形状全実現している。更にウェハ
毎のキャリア濃度プロファイルの再現性も極めて良いこ
とが判明した。この理由としては
■ 熱処理が一度なので基板の熱変成が少なく、ｐ型不
純物が異常拡散しにくい。As is clear from FIG. 4, according to the above example, a steep acceptor concentration distribution close to the theoretical distribution of implanted impurities was obtained, and a large number of tcp −
The ideal shape for an n-junction has been realized. Furthermore, it was found that the reproducibility of the carrier concentration profile for each wafer was also extremely good. The reason for this is (1) Since the heat treatment is performed only once, there is little thermal transformation of the substrate, and p-type impurities are less likely to be abnormally diffused.
■ ｎ型不純物の存在がｐ型不純物の拡散を補償してい
る。■ The presence of n-type impurities compensates for the diffusion of p-type impurities.
などが挙げられる。Examples include.
なお、ｐ型不純物、ｎ型不純物の種類や注入条件を様々
に変化させても、上記の方法により、設計通りのｐ−ｎ
接合を形成することが可能であった０
上記実施例においては、ＧａＡｓ半導体について説明し
たが、本発Ｆ！Ａはこれに限定されるものではなく、Ｉ
ｎＰ等の他の化合物半導体についても、同様に実施でき
ることは言うまでもない。Note that even if the types and implantation conditions of the p-type impurity and n-type impurity are varied, the designed p-n
It was possible to form a junction.0 In the above embodiment, a GaAs semiconductor was explained, but the F! A is not limited to this, but I
It goes without saying that the same method can be applied to other compound semiconductors such as nP.
〈発明の効果〉
以上説明した様に、本発明のｐ−ｎ接合の形成方法によ
れば、従来の実施例に比べて
■ ｐ型不純物の異常拡散を防ぎ、設計通りの急峻なｐ
−ｎ接合を再現性良く得ることができる。<Effects of the Invention> As explained above, according to the method for forming a p-n junction of the present invention, it is possible to prevent abnormal diffusion of p-type impurities and form a steep p-p junction as designed, compared to conventional embodiments.
-N junctions can be obtained with good reproducibility.
＠ 熱処理が一度なので、工程数が削減でき、かつ基板
の熱変成も最小限に抑えられ、従って、接合特性の劣化
を防止することができる。@ Since the heat treatment is performed only once, the number of steps can be reduced, thermal transformation of the substrate can be minimized, and therefore deterioration of bonding characteristics can be prevented.
θ 保護膜を用いたキャップアニールなので、砒素圧を
加える必要がな（、作業全安全に行うことが出来る。Since the cap annealing uses a θ protective film, there is no need to apply arsenic pressure (the work can be performed completely safely).
等の種々の効果を得ることが出来る。It is possible to obtain various effects such as.
第１図乃至第３図は本発明のｐ−ｎ接合の形成方法の一
実施例の工程を示す断面図、第４図は本発明によるｐ−
ｎ接合のキャリア濃度プロファイルの一例全示す図、％
５図は従来の二度アニール法により形成された瀘入４←
のキャリア濃度プロファイルの一例を示す図である。
２・・・半絶縁性ＧａＡｓ基板、３・・・ｎ型不純物Ｓ
ｉ＋注入層、５・・・ｐ型不純物りｎ＋注入層、６・・
・ＧａＡｓ基板保護膜、７・・・ｎ型層１．８・・・ｐ
型層代理人 弁理士 福 士 愛 彦 （他２名）２ｎ
＋
第２図
第３図
３粱ご シ仰〕
第４図
３５ｉ ： ５ｐＪｎ）
第５図1 to 3 are cross-sectional views showing the steps of an embodiment of the method for forming a p-n junction according to the present invention, and FIG.
A diagram showing an example of the carrier concentration profile of an n-junction, %
Figure 5 shows the filtration hole 4 formed by the conventional twice-annealing method.
FIG. 3 is a diagram showing an example of a carrier concentration profile of FIG. 2...Semi-insulating GaAs substrate, 3...n-type impurity S
i+ injection layer, 5...p-type impurity n+ injection layer, 6...
・GaAs substrate protective film, 7...n-type layer 1.8...p
Type layer agent Patent attorney Aihiko Fukushi (and 2 others) 2n
+ Figure 2, Figure 3, Figure 3) Figure 4, 35i: 5pJn) Figure 5
Claims (1)
合物半導体に対し、保護膜付同時アニールを施すことに
より、両導電型不純物を同時に活性化させ、深さ方向に
接合を形成せしめるように成したことを特徴とするｐ−
ｎ接合の形成方法。1. By applying simultaneous annealing with a protective film to a compound semiconductor into which both P-type and N-type conductivity type impurities are ion-implanted, both conductivity type impurities are simultaneously activated and a junction is formed in the depth direction. p-, which is characterized by having been achieved in
How to form an n-junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13964984A JPS6118126A (en) | 1984-07-04 | 1984-07-04 | P-n junction forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13964984A JPS6118126A (en) | 1984-07-04 | 1984-07-04 | P-n junction forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6118126A true JPS6118126A (en) | 1986-01-27 |
Family
ID=15250186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13964984A Pending JPS6118126A (en) | 1984-07-04 | 1984-07-04 | P-n junction forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6118126A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482618A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Heat treatment |
| JPS6482619A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Heat treatment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5627972A (en) * | 1979-08-17 | 1981-03-18 | Oki Electric Ind Co Ltd | Manufacture of compound semiconductor device |
-
1984
- 1984-07-04 JP JP13964984A patent/JPS6118126A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5627972A (en) * | 1979-08-17 | 1981-03-18 | Oki Electric Ind Co Ltd | Manufacture of compound semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482618A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Heat treatment |
| JPS6482619A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Heat treatment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| SE7606869L (en) | WAY TO TREAT SEMICONDUCTOR DEVICES | |
| JPH05234927A (en) | Method of forming diffusion region of semiconductor device by solid-phase diffusion | |
| JPS6118126A (en) | P-n junction forming method | |
| JPH03224241A (en) | Insulated-gate field-effect transistor and manufacture thereof | |
| JPS59175721A (en) | Manufacture of semiconductor device | |
| KR100215907B1 (en) | Manufacturing method of a zener diode | |
| JPH01245519A (en) | Manufacture of semiconductor device | |
| JPH03265131A (en) | Manufacture of semiconductor device | |
| JPH0661234A (en) | Production of semiconductor device | |
| JPS6236866A (en) | Manufacture of semiconductor device | |
| JPS6294926A (en) | Manufacture of semiconductor device | |
| JPS6123365A (en) | Formation of constant voltage diode | |
| JPS61144822A (en) | Formation of gaas conductive layer | |
| JPS60149125A (en) | Method for impurity doping into semiconductor substrate | |
| JPS63148616A (en) | Manufacture of semiconductor device | |
| JPS60219770A (en) | Manufacture of semiconductor device | |
| JPH0216008B2 (en) | ||
| JPS63273317A (en) | Manufacture of semiconductor device | |
| JPH01235333A (en) | Heat treatment of iii-v compound semiconductor | |
| JPH0322526A (en) | Manufacture of silicon carbide semiconductor device | |
| JPH0284718A (en) | Impurity introduction into semiconductor film | |
| JPH023293A (en) | Manufacture of semiconductor element | |
| JPH01274422A (en) | Heat treatment method for semiconductor substrate | |
| JPS59119761A (en) | Manufactuer of semiconductor device | |
| JPS63244842A (en) | Ion implantation into compound semiconductor |