JPH023293A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To make it possible to do recovery from crystal damage generated at the time of impurity introduction in heat process at the time of second crystal growth and impurity diffusion at the same time, and to prevent abnormal diffusion by dividing crystal growth into twice so as to introduce impurity between the first time and the second time. CONSTITUTION:An n-type InGaAs crystal layer 12, an n-type InGaAsP crystal layer 13, an n-type InP crystal layer 14, an N-type InP crystal layer 15 are formed in order on an n-type InP substrate 11 by a vapor crystal growth method. An area 23 to which Be is introduced selectively by an ion implantation method is formed near the surface of the crystal layer 15. Next, an InGaAs layer 31 is selectively formed by crystal- growth on the area 23, In the process of this crystal growth, Be introduced already is diffused into the layer 31 and the crystal layer 15, and a P-type InP area 323 can be made. Next, after removing an SiN film 21 inside a ring once, Cd is diffused selectively in the vapor phase so as to form the second p-n junction 41, and after selectively forming a Sin film 42, electrodes 43 and 44 are formed. Hereby, a semiconductor element can be constituted that the diffusion of the impurity Be introduced in advance is also done, that the inclined type p-n junction 41 can be made at the same time, and that there is no abnormal diffusion at the junction interface of different kinds of layers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing semiconductor elements such as laser diodes and light receiving elements using indium phosphide (InP) material.

(Conventional technology) Light is emitted by applying a bias to the pn junction of a semiconductor.

Semiconductor devices that utilize phenomena such as light reception and amplification require electrode metals that make ohmic contact. Conventionally, it was difficult to obtain good ohmic contact with InP material, so InP
InG has a small energy gap and can be lattice matched to
A structure in which a mixed crystal such as aAs or nGaAsP is provided between InP and an electrode metal has become common. As an example, Japanese Patent Laid-Open No. 125870/1983 has already been proposed.

In this case, InP/I is sequentially grown by continuous crystal growth.
After forming each layer of nGaAsP/InP/InGaAsP, a guard ring part was formed by ion implantation and annealing, and a P+ part was formed by Cd diffusion, and then the InGaAsP layer on the surface was selectively removed by etching to form an avalanche photodiode. Ta.

(Problem M to be Solved by the Invention) Such conventional semiconductor devices have problems such as step differences on the surface of the device, making them unsuitable for integration, and failures in conduction due to broken wires. Furthermore, it is known that when impurities are introduced into a substrate having a dissimilar semiconductor junction of InP/InGaAsP by ion implantation, annealing, diffusion, etc., abnormal diffusion occurs over the entire junction interface. This leads to the impossibility of controlling the impurity concentration distribution and the position of the pn junction when forming the pn junction in the semiconductor, and further causes defects in the semiconductor element.

This invention was made in consideration of the above circumstances, and its purpose is to eliminate steps on the element surface to prevent conduction defects, and to improve element characteristics by eliminating abnormal diffusion when introducing impurities. The object of the present invention is to provide a method for manufacturing a semiconductor device that can contribute to the present invention.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention divides crystal growth into two times, and separates the first crystal growth and the second crystal growth. The feature is that impurities are introduced in between, and the thermal process during the second crystal growth performs both recovery of crystal damage caused at the time of impurity introduction and impurity diffusion.

(Function) Recent advances in semiconductor device manufacturing technology have been remarkable. For example, in crystal growth technology, controllability has been greatly improved by chemical vapor deposition (MOCVD) or vapor phase growth using organic metals, and thickness For example, the distribution of is ± on a 2-inch wafer.
It has reached 0.5%. The key point of the present invention is that by applying such a technique, it is possible to easily manufacture a semiconductor element with a structure that was previously considered impossible.

According to the present invention, for example, a step of selectively forming an insulator on the main surface of an n-type InP crystal, a step of ion-implanting a p-type impurity into InP using the insulator as a mask, for example, an I
The method consists of a step of growing an nGaAs mixed crystal on the ion-implanted region. Among these, the step of crystal growth usually requires a temperature of 650 to 750°C. A feature of the present invention is that this thermal process is used to activate the crystal damaged during ion implantation and to diffuse p-type impurities.

Such a process can prevent abnormal diffusion at the junction interface of different types of semiconductors, which has been a problem in the past. This is because selective crystal growth is performed only on the necessary portions, excluding the portions protected by the insulator, thereby preventing diffusion. In addition, by selectively growing an InGaAs mixed crystal layer with a thickness equivalent to that of the insulator, it is possible to create a configuration in which no steps are formed on the element surface, thereby preventing conduction failures due to broken wires, and making it possible to integrate the device.

Furthermore, it has the effect of preventing scattering and re-diffusion of P-type impurities generated during the thermal process performed for activation.

By the above technical means, it is possible to construct a semiconductor element with a step-free structure and low electrode contact resistance using a relatively simple method.

(Example) The details of the present invention will be explained below with reference to the drawings.

FIG. 1 is a sectional view showing the manufacturing process of an avalanche photodiode. First, as shown in Fig. 1(a),
An n-type InGaAs crystal layer 12 is formed on the InP-type substrate 11 . n
type InGaAsP crystal layer 13, n-type InP crystal layer 14,
An n-type InP crystal layer 15 is sequentially formed by a vapor phase crystal growth method. The impurity concentration of each crystal layer 12 to 15 is sequentially 5.
X10"am-37XIO"an-32XIO"am-
' 5 x 10" and 1 m-", and the thickness of each crystal layer is sequentially 2 μm, 0.2 μs, 1 μs, and 1.5 μs.

Next, as shown in FIG. 1(b), a SiN film 21. is formed on the n-type InP crystal layer 15. Made of 2 SiO films 0.2p
, o, g thicknesses are selectively formed. The formation method was to selectively leave a film formed by a plasma CVD apparatus using a photoresist process. The window removed by etching has a ring shape with an inner diameter of 50 μs and an outer diameter of 90 μs, and through this window, Be, which becomes a p-type impurity for the InP crystal, is selected by ion implantation near the surface of the n-type InP crystal layer. A region 23 is formed in which the material is introduced.

Be ion implantation was carried out at an accelerating voltage of 200 KeV and 3XIO
The test was carried out at a dose of "C11-". In this state Be
The crystal in region 23 into which the
The n-type InP crystal layer 15 must be activated. Activation requires a temperature of 650° C. or higher, and in order to prevent surface deterioration during activation, a thermal process under phosphorous pressure has already been carried out.

Next, as shown in FIG. 1(C), Be-introduced region 2
An InGaAs layer 31 is selectively crystal-grown on the SiN film 2 to a thickness of 1 (0, 2). Crystal growth is performed by a vapor phase growth method, and the crystal growth temperature is 700°C. At this time, Si was provided as a mask during Be ion implantation.
The O film 22 is removed in advance. InGaAs layer 3
In the process of crystal growth in step 1, the already introduced Be becomes In
It is diffused into the GaAs layer 31 and the n-type InP crystal layer 15 to form a p-type InP region 323. This p-type InP
A sloped p-n junction 33 is formed between the region 323 and the n-type InP crystal layer 15 to prevent local breakdown when a reverse bias is applied to the p-n junction. That is, it is a guard ring junction of an avalanche photodiode.

Next, as shown in FIG. 1(d), the S inside the ring is
After removing the iN film 2, Cd is selectively diffused in a vapor phase to form a second p-n junction 41, and after selectively forming a new SiN layer 42 to serve as an anti-reflection film, the electrode 43 and 44 are formed to complete the avalanche photodiode. Here, the second p-n junction 41 is diffused at a temperature of 580 DEG C. so that it becomes a one-sided stepped junction type, and this is used as a light-receiving section junction. The electrode 43 can be provided without any step at the boundary between the InGaAs layer 31 and the SiN film.

This enables selective crystal growth of an InGaAs layer or an InGaAsP layer provided for the purpose of reducing contact resistance, and activation of a damaged region at the same time. By selective crystal growth, it is possible to simultaneously form a sloped p-n junction by diffusing previously introduced impurities, and moreover, it is possible to form a semiconductor device without abnormal diffusion at the heterojunction interface.

Moreover, this stepless planar structure can prevent failures in conduction, and also enables integration with a drive circuit and an amplifier circuit.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of an avalanche photodiode according to an embodiment of the present invention. 11...n-type InP substrate 12, 31-n-type InGaAs crystal layer 13-n-type In
GaAsP crystal layer 14...n-type InP crystal layer 15...n-type InP crystal layer 21, 42...SiN film 22...SiO film 23...p-type impurity introduced region 323/P-type InP Regions 33, 41...p-n junctions 43, 44...Electrode agent Patent attorney Noriyuki Chika Noriyuki Mitsuru Matsuyama Figure 1

Claims (1)

[Claims] In a method for manufacturing a semiconductor device in which a group III-V mixed crystal layer containing In as a constituent element is provided between an InP crystal of one conductivity type and an electrode metal, an insulator is selectively formed on the surface of the InP crystal. a step of selectively introducing an opposite conductivity type impurity into the vicinity of the InP crystal surface excluding the insulator portion;
A step of selectively growing a group III-V mixed crystal layer containing In as a constituent element on the region into which the opposite conductivity type impurity is introduced to a thickness equal to or less than that of the insulator, and together with the selective crystal growth. Manufacturing a semiconductor device, comprising a step of activating a region into which the opposite conductivity type impurity is introduced, and diffusing the opposite conductivity type impurity into a III-V group mixed crystal layer and an InP crystal. Method.