JPS616820A - Manufacture of compound semiconductor device - Google Patents

Manufacture of compound semiconductor device

Info

Publication number
JPS616820A
JPS616820A JP59127904A JP12790484A JPS616820A JP S616820 A JPS616820 A JP S616820A JP 59127904 A JP59127904 A JP 59127904A JP 12790484 A JP12790484 A JP 12790484A JP S616820 A JPS616820 A JP S616820A
Authority
JP
Japan
Prior art keywords
layer
diffusion
inxga1
xasyp1
inp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59127904A
Other languages
Japanese (ja)
Inventor
Katsuya Hasegawa
克也 長谷川
Seiji Onaka
清司 大仲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59127904A priority Critical patent/JPS616820A/en
Publication of JPS616820A publication Critical patent/JPS616820A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2233Diffusion into or out of AIIIBV compounds

Abstract

PURPOSE:To form the PN junction in different depth through single diffusion to each InxGa1-xAsyP1-y layer by the thermal diffusion to the region including the interface of InxGa1-xAsyP1-y layers in different compositions, utilizing the fact that impurity diffusion rate to InxGa1-xAsyP1-y is different depending on the compositions x, y. CONSTITUTION:The InxGa1-xAsyP1-y layer 12 which becomes a photosensitive layer and InP layer are formed by epitaxial growth on the N type Inp substrate 11. Next, the InxGa1-xAsyP1-y layer 15 is selectively formed with the photosensitive region masked by adequate material 14 such as SiO2, Si3N4, etc. In this case, the planar surface can be formed by the melt-back in the case of LPE or by adequate etching in the case of the other growth method. After the mask 14 is removed, the P type regions 16, 17 are formed by the sealed tube thermal diffusion method with ZnP2 used as the diffusion source.

Description

【発明の詳細な説明】 産業上の利用分野 本発明に化合物半導体装置の製造方法に関し、特に不純
物の熱拡散の方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for thermally diffusing impurities.

従来例の構成とその問題点 GaAsやInPを基板とした化合物半導体は、その吸
収波長域が光通信で使用はれる赤外領域にあるため、受
発光材料として用いられる。受光素子としてフォトダイ
オードやアバランシェフォトダイオードが用いられる。
Conventional Structure and Problems Compound semiconductors using GaAs or InP as substrates are used as light-receiving and emitting materials because their absorption wavelength range is in the infrared region used in optical communications. A photodiode or an avalanche photodiode is used as the light receiving element.

第1図はアバランシェフォトダイオードの一構成例を示
す説明図である。
FIG. 1 is an explanatory diagram showing one configuration example of an avalanche photodiode.

n型のInP基板1上に受光層となるInxGa、−エ
Asyp 、−y (○<z<1.o<、y層1)層2
、アバランシェ増倍をおこす領域となるInP 層3を
エピタキシャル成長させた後、受光領域4を形成すべく
p型頭域6を形成する。p領域の形成にげ、Zn、Cd
等の熱拡散、Be、Zn、Cd等のイyt−ンg人など
の方法がとられる。しかし、通常アバ2ンシエフオトダ
イオードの製造においてはガードリング6の形成工程が
必要となる。すなわち、ガードリングのないpn接合で
に、接合端部7において電界集中が起こりやすく、他の
部分よシケやくアバランシェブレイクダウンが起こって
し捷う。
InxGa, -Asyp, -y (○<z<1.o<, y layer 1) layer 2 which becomes a light-receiving layer on an n-type InP substrate 1
After epitaxially growing the InP layer 3 which becomes a region where avalanche multiplication occurs, a p-type head region 6 is formed to form a light receiving region 4. Formation of p region, Zn, Cd
Methods such as thermal diffusion, such as Be, Zn, Cd, etc., are used. However, in the manufacture of an avalanche photodiode, a step of forming the guard ring 6 is usually required. That is, in a pn junction without a guard ring, electric field concentration tends to occur at the junction end 7, and avalanche breakdown occurs quickly in other parts.

これを防ぐためp型頭域6を受光範囲4の外側に浅い接
合で設ける。このようなガードリング6を設けることに
よって、受光領域下でのInP層の厚σ8に、ガードリ
ング領域下でのInP層の厚さ9より薄くすることがで
き、従ってアバランランシェ降伏は受光域4内のみで均
一におこる。このようなガードリングの形成は、接合深
での異なる2種類のpn接合を必要とするため、2度の
熱拡散捷たけイオン注入工程が不可避である。しかし、
一般に化合物半導体表面はシリコン等に比し非常に不安
定である。熱拡散によf)ts○0〜600″Cの雰囲
気にさらσねるInP  やIn、2:Ga1−xA5
yP1−y表面でのAsやPの選択的脱離、表面酸化、
汚染等を考えると、高温熱拡散の工程数は極力少ない方
が良いことに勿論でめる。捷たイオンY十人工程を用い
たとしても、結晶性回復のための800〜900℃での
アニール工程が必要となることを考えれば同様である。
To prevent this, the p-type head area 6 is provided outside the light receiving area 4 with a shallow junction. By providing such a guard ring 6, the thickness σ8 of the InP layer under the light-receiving region can be made thinner than the thickness 9 of the InP layer under the guard ring region. Therefore, avalanche breakdown occurs in the light-receiving region 4. Occurs uniformly only within the body. Formation of such a guard ring requires two types of pn junctions with different junction depths, so two thermal diffusion and ion implantation steps are unavoidable. but,
In general, compound semiconductor surfaces are much more unstable than silicon and the like. InP, In, 2:Ga1-xA5 exposed to an atmosphere of f)ts○0~600''C due to thermal diffusion
Selective desorption of As and P on the yP1-y surface, surface oxidation,
Considering contamination, etc., it is of course better to minimize the number of high-temperature thermal diffusion steps. The same is true if you consider that an annealing step at 800 to 900° C. is required to recover crystallinity even if the shredded ion Y ten-nin process is used.

発明の目的 本発明はこのような従来技術の問題点を解決するもので
、一度の拡散工程でふたつの異なる拡散深σのpn接合
を形成することのできる化合物半導体装置の製造方法を
提供することを目的とする。
OBJECTS OF THE INVENTION The present invention solves the problems of the prior art, and provides a method for manufacturing a compound semiconductor device that can form pn junctions with two different diffusion depths σ in a single diffusion step. With the goal.

発明の構成 本発明Fi InxGa 、 −、AsyP 、−yへ
の不純物拡散速度が、組成I、yによって異なることを
利用し、組成の違ったIn、 Ga1−xAs、、 P
l−y層の界面を含む領域に熱拡散を施し、各々のIn
xGa、−エAs、 P 1−y層に、一度の拡散によ
って異なる深さのpn接合を形成するもので勘る。
Structure of the Invention The present invention takes advantage of the fact that the impurity diffusion rate into Fi InxGa, -, AsyP, -y differs depending on the composition I and y,
Thermal diffusion is applied to the region including the interface of the ly layer, and each In
It is assumed that pn junctions of different depths are formed in the xGa, -air As, P1-y layers by one-time diffusion.

実施例の説明 第2図に本発明者らが測定したInxGa1−エA S
 y P 1− yへのZnO熱拡熱拡散深水す図でる
る。
DESCRIPTION OF EXAMPLES FIG. 2 shows the InxGa1-air AS
A diagram of ZnO thermal expansion diffusion into y P 1- y is shown in deep water.

第2図A[ノンドープInP に、ZnP2(1mg/
cc  )を拡散ソースとして封管熱拡散した時の拡散
深さを測定した図である。一方策2図Bに、In(、、
53G4o、 47 As ヘの同様の条件でのZn(
7)熱拡散性σを示す図である。第2図A、Bの縦軸の
違いに注意すると、ZnO熱拡散速度に、InP中での
方が、Ino、ss GJ、47 As K比べて2〜
3倍大きいことがわかる。一般にIn工Ga、−エAs
yP、−9でにその組成がInP からGaAsに近づ
くニ従って、Znの拡散速度に遅くなっていく。第2図
c(4その様子を示したものでInP  に格子整合し
たIn、2:Ga1−fxAsyP1、、のバンドギャ
ップが大きくなる程、即ち組成がInP に近づく程、
拡散速度が大きくなっていく様子を示している。
Figure 2 A [Non-doped InP, ZnP2 (1 mg/
cc) as a diffusion source and the diffusion depth was measured when thermal diffusion was carried out in a sealed tube. On the other hand, in Figure 2B, In(,,
53G4o, 47As under similar conditions to Zn(
7) It is a figure showing thermal diffusivity σ. Paying attention to the difference in the vertical axes in Figure 2 A and B, it can be seen that the ZnO thermal diffusion rate in InP is 2 to
It turns out that it is three times larger. Generally In-Ga, -Air As
As the composition approaches GaAs from InP at yP, -9, the diffusion rate slows down to that of Zn. Figure 2c (4) shows this situation.The larger the bandgap of In, 2:Ga1-fxAsyP1, which is lattice matched to InP, the closer the composition approaches InP,
This shows how the diffusion rate increases.

本発明にこのような現象に基づき、拡散速度の異なる層
に熱拡散することによって、1回の拡散で異なる拡散深
σのpn接合を同時に形成しようとするものである。
Based on this phenomenon, the present invention attempts to simultaneously form pn junctions with different diffusion depths σ in one diffusion by thermally diffusing layers with different diffusion rates.

第3図に本発明の一実施例のアバランシェフォトダイオ
ードの製作工程図を示す。n型InP基板11上に受光
層となるInxGa1−、:AsyPl−y。
FIG. 3 shows a manufacturing process diagram of an avalanche photodiode according to an embodiment of the present invention. InxGa1-, :AsyPl-y, which becomes a light-receiving layer on the n-type InP substrate 11.

(例えばJ=0.53.、!/=1 )層12、InP
層13をエピタキシャル成長σせる。次vtc 5i0
2 。
(For example, J=0.53.,!/=1) Layer 12, InP
The layer 13 is epitaxially grown. Next vtc 5i0
2.

Si3N4  等適当な材料14で受光領域をマスクし
て、I n xG a 1−xAs y P 1++ 
y (例えば1−0.27゜I−0,60)層15を選
択的に成長きせる。このとき、エピタキシャル成長前に
、LPEであればメルトバック、その他の成長方法でロ
レば適当なエツチングを施してやれば、第3図Bの如く
プレーナーな表面を作ることができる。マスク14除去
後、ZnP2を拡散ソースとした封管熱拡散によってp
型領域16.17を形成する。拡散温度550’C,拡
散時間15分なる条件を選ぶと、InP層16には約3
.5117# 、 In0.73 ”’0.27AS0
,60 po、、lo層17には約2.5μmの深さの
p型領域が形成σれる。
The light-receiving area is masked with a suitable material 14 such as Si3N4, and In xG a 1-xAs y P 1++
y (eg 1-0.27°I-0,60) layer 15 is selectively grown. At this time, by performing melt-back in the case of LPE or appropriate etching in the case of other growth methods before epitaxial growth, a planar surface as shown in FIG. 3B can be created. After removing the mask 14, p is removed by sealed tube thermal diffusion using ZnP2 as a diffusion source.
Forming mold regions 16,17. If we choose the conditions of diffusion temperature 550'C and diffusion time 15 minutes, the InP layer 16 will have about 3
.. 5117#, In0.73”'0.27AS0
, 60 po, , a p-type region with a depth of about 2.5 μm is formed in the lo layer 17.

第4図にこのようにして製作でれたアバラン/エフオド
ダイオードである。受光領域での拡散領域16の深さが
領域17よりなるガードリング領域での拡散深さより深
く形成されているため、エツジブレイクダウンが緩和て
れてアバランフ工降伏に受光領域22で均一に起こる。
Figure 4 shows the avalan/efodo diode manufactured in this manner. Since the depth of the diffusion region 16 in the light receiving region is formed deeper than the diffusion depth in the guard ring region formed by the region 17, edge breakdown is relaxed and avalanche breakdown occurs uniformly in the light receiving region 22.

このように、ガードリングを1回の拡散によって形成す
ることによって、高温熱処理プロセスを減らし、安定な
素子を再現性良く製作することができる。
In this way, by forming the guard ring by one-time diffusion, it is possible to reduce the high-temperature heat treatment process and manufacture a stable element with good reproducibility.

本発明にこのようなアバラン/エフォトターイオードの
ガードリング形成のみでなく、In工Ga1−アAsy
P、y系化合物に広く適用できる。第6図に本発明をI
ng、53 Gao、a7As  7 オドダイオード
に゛適用した別の一実施例である。n+型InP基板1
01上に成長したノンドープInP  層102中に、
受光部とXるIno、ss GiLo、47 As層1
03を選択的に成長式せる。ここに5i02. Si3
N4等からなる適当な拡散マスク104を通してZnの
熱拡散を行なう。拡散温度5o○°c、拡散時間15分
の条件を採用すると、InPへに1.6μm〜2μmI
n0.53 can、47 As ヘHO,5〜111
1Hの深さの接合が形成σJする。このようにして作成
したフォトダイオードが第5図Bでめるが、InP へ
の深い拡散層105がチャンネルストッパーとして働き
暗電流を低減する効果がある。またこのような構成をと
ることによって安定なばらつきの少ないpn接合を得る
ことができる。
The present invention not only forms a guard ring of such an avalan/ephototer diode, but also forms a
It can be widely applied to P,y-based compounds. The present invention is shown in FIG.
This is another example in which the present invention is applied to a ng, 53 Gao, a7As 7 odd diode. n+ type InP substrate 1
In the non-doped InP layer 102 grown on 01,
Ino, ss GiLo, 47 As layer 1 with light receiving part
03 can be selectively grown. Here 5i02. Si3
Thermal diffusion of Zn is performed through a suitable diffusion mask 104 made of N4 or the like. When the conditions of diffusion temperature 5o○°C and diffusion time 15 minutes are adopted, 1.6 μm to 2 μm I
n0.53 can, 47 As heHO, 5~111
A junction with a depth of 1H is formed σJ. The photodiode thus produced is shown in FIG. 5B, and the deep diffusion layer 105 into InP acts as a channel stopper and has the effect of reducing dark current. Moreover, by adopting such a configuration, a stable pn junction with little variation can be obtained.

上記の実施例においては拡散不純物としてZnを使用し
たが、Cd、Mn、Mg等I n x G al−x 
A SyP、−yの組成によって拡散速度が異なるよう
な不純物であれば構わfX+/−1ことにもちろんであ
る。また受光素子に限らず、インバットダイオード等の
電気素子にも応用可能でるる。
In the above embodiment, Zn was used as the diffusion impurity, but Cd, Mn, Mg, etc.
Of course, any impurity whose diffusion rate differs depending on the composition of A SyP, -y may be used as fX+/-1. Moreover, it can be applied not only to light-receiving elements but also to electric elements such as invat diodes.

発明の詳細 な説明したように本発明i Inx(、a 、−エA邑
The present invention is described in detail below.

P、−yから成る化合物半導体装置に対して単一の熱拡
散によって異なる拡散深σのpn接合を形成することを
可能にするもので、bす、その実用的価値に極めて大き
い。
This makes it possible to form pn junctions with different diffusion depths σ in a compound semiconductor device consisting of P and -y by a single thermal diffusion, and its practical value is extremely great.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のアバランシェフォトダイオードの一構成
例の断面図、第2図(A)fiInP 中へのZnの拡
散深さを示す図、第2図(B )I−jxnO,53c
a[1,47As ヘのZn)拡散深さを示す図、第2
図(C) Q In、Ga 、−xAs、yP 、−y
 ノバンドギャノプと拡散速度の関係を示す図、第3図
(A)〜(C)u本発明の一実施例であるアバランシェ
フォトダイオードの製作工程説明図、第4図に本発明の
一実施例でめるアバランシェフォトダイオードの構造断
面図、第5図(A)、(B)は本発明の別の実施例であ
るフォトダイオードの構造断面図である。 21.107・・・・反射防止膜、20,108・・・
・・n側電極、19,109・・・n側電極、18゜1
04・・・・拡散マスク。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 TIME  (mi、n) 丁1fJHEVe   (secVt)第2図 丁1図E(7T′l翔) TIMEゾ’z  (secyB 第2図 工木ル〒゛−〜′−、ソフ0Eグ(e、V)第3図
Figure 1 is a cross-sectional view of an example of the configuration of a conventional avalanche photodiode, Figure 2 (A) is a diagram showing the depth of Zn diffusion into fiInP, Figure 2 (B) I-jxnO, 53c.
a[1,47As Zn) Diagram showing the diffusion depth, 2nd
Figure (C) QIn, Ga, -xAs, yP, -y
Figures 3 (A) to 3 (C) are diagrams showing the relationship between the band gap and the diffusion rate; FIGS. 5A and 5B are structural cross-sectional views of a photodiode according to another embodiment of the present invention. 21.107...Antireflection film, 20,108...
...n-side electrode, 19,109...n-side electrode, 18°1
04...Diffusion mask. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 TIME (mi, n) 1f JHEVe (secVt) 2nd Figure 1 E (7T'l 翔) TIME zo'z (secyB Figure 2) e, V) Figure 3

Claims (1)

【特許請求の範囲】[Claims] 一方導電型の第1のIn_xGa_1_−_xAs_y
P_1_−_y(0≦x≦1、0≦y≦1)層と、前記
In_xGa_1_−_xAs_yP_1_−_y層と
同一導電型で組成の異なる第2のIn_zGa_1_−
_zAs_uP_1_−_u(0≦z≦1、0≦u≦1
)層を形成し、前記第1のIn_xGa_1_−_xA
s_yP_1_−_y層と第2のIn_zGa_1_−
_zAs_uP_1_−_u層の界面を含む領域に熱拡
散を施すことにより、前記第1のIn_xGa_1_−
_xAs_yP_1_−_y層に、第2のIn_zGa
_1_−_zAs_uP_1_−_u層よりも深い反対
導電型領域を形成することを特徴とする化合物半導体装
置の製造方法。
On the other hand, the first conductivity type In_xGa_1_-_xAs_y
P_1_-_y (0≦x≦1, 0≦y≦1) layer, and a second In_zGa_1_- having the same conductivity type as the In_xGa_1_-_xAs_yP_1_-_y layer but having a different composition.
_zAs_uP_1_-_u(0≦z≦1, 0≦u≦1
) layer, and the first In_xGa_1_-_xA
s_yP_1_-_y layer and second In_zGa_1_-
By applying thermal diffusion to the region including the interface of the _zAs_uP_1_-_u layer, the first In_xGa_1_-
In the _xAs_yP_1_-_y layer, the second In_zGa
_1_-_zAs_uP_1_-_u A method for manufacturing a compound semiconductor device characterized by forming a region of an opposite conductivity type deeper than the layer.
JP59127904A 1984-06-21 1984-06-21 Manufacture of compound semiconductor device Pending JPS616820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59127904A JPS616820A (en) 1984-06-21 1984-06-21 Manufacture of compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59127904A JPS616820A (en) 1984-06-21 1984-06-21 Manufacture of compound semiconductor device

Publications (1)

Publication Number Publication Date
JPS616820A true JPS616820A (en) 1986-01-13

Family

ID=14971532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59127904A Pending JPS616820A (en) 1984-06-21 1984-06-21 Manufacture of compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS616820A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6449283A (en) * 1987-08-19 1989-02-23 Nec Corp Planar-type heterojunction semiconductor photodetector
JPS6449284A (en) * 1987-08-19 1989-02-23 Nec Corp Planar-type heterojunction semiconductor photodetector
JP2007080920A (en) * 2005-09-12 2007-03-29 Mitsubishi Electric Corp Avalanche photodiode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6449283A (en) * 1987-08-19 1989-02-23 Nec Corp Planar-type heterojunction semiconductor photodetector
JPS6449284A (en) * 1987-08-19 1989-02-23 Nec Corp Planar-type heterojunction semiconductor photodetector
JP2007080920A (en) * 2005-09-12 2007-03-29 Mitsubishi Electric Corp Avalanche photodiode

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