JPS61170058A - レベルシフト複合回路 - Google Patents

レベルシフト複合回路

Info

Publication number
JPS61170058A
JPS61170058A JP60010096A JP1009685A JPS61170058A JP S61170058 A JPS61170058 A JP S61170058A JP 60010096 A JP60010096 A JP 60010096A JP 1009685 A JP1009685 A JP 1009685A JP S61170058 A JPS61170058 A JP S61170058A
Authority
JP
Japan
Prior art keywords
electrode
region
conductivity type
level shift
terminal connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60010096A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0337314B2 (en:Method
Inventor
Hiroyuki Ishikawa
弘之 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP60010096A priority Critical patent/JPS61170058A/ja
Publication of JPS61170058A publication Critical patent/JPS61170058A/ja
Publication of JPH0337314B2 publication Critical patent/JPH0337314B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H10D84/406—Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP60010096A 1985-01-23 1985-01-23 レベルシフト複合回路 Granted JPS61170058A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60010096A JPS61170058A (ja) 1985-01-23 1985-01-23 レベルシフト複合回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60010096A JPS61170058A (ja) 1985-01-23 1985-01-23 レベルシフト複合回路

Publications (2)

Publication Number Publication Date
JPS61170058A true JPS61170058A (ja) 1986-07-31
JPH0337314B2 JPH0337314B2 (en:Method) 1991-06-05

Family

ID=11740792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60010096A Granted JPS61170058A (ja) 1985-01-23 1985-01-23 レベルシフト複合回路

Country Status (1)

Country Link
JP (1) JPS61170058A (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6376998U (en:Method) * 1986-11-05 1988-05-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6376998U (en:Method) * 1986-11-05 1988-05-21

Also Published As

Publication number Publication date
JPH0337314B2 (en:Method) 1991-06-05

Similar Documents

Publication Publication Date Title
JPH02126669A (ja) 複合ｍｏｓトランジスタと自由輪ダイオード
JPS61182264A (ja) 縦型ｍｏｓトランジスタ
JPS6142862U (ja) 縦形ｐｎｐトランジスタを含む集積回路
JPS61296770A (ja) 絶縁ゲ−ト電界効果型半導体装置
JPS61170058A (ja) レベルシフト複合回路
JP2712448B2 (ja) 半導体装置
JPH0440867B2 (en:Method)
JPS59161059A (ja) 半導体装置
JP3199857B2 (ja) 伝導度変調型ｍｏｓｆｅｔ
JPS60254651A (ja) Ｃｍｏｓ回路の入力保護回路
JP2690776B2 (ja) 半導体装置
JPH0530365Y2 (en:Method)
JPH069505Y2 (ja) パルス発生回路装置
JPH02132854A (ja) エミッタカップルドロジック回路
JPH0525234Y2 (en:Method)
JPS6083361A (ja) 半導体装置
JPH0342680Y2 (en:Method)
JP3071819B2 (ja) 絶縁ゲート型半導体装置
JPS61296760A (ja) 半導体装置
JPS63128746A (ja) 半導体記憶装置
JPH0222545B2 (en:Method)
JPS61135148A (ja) 半導体集積回路装置
JPS61208864A (ja) Ｃ−ｍｏｓ集積回路装置
JPS61102074A (ja) シリ−ズダイオ−ド
JPH02201930A (ja) 半導体集積回路