JPS61168948A - Leadframe for semiconductor device and semiconductor device using same - Google Patents
Leadframe for semiconductor device and semiconductor device using sameInfo
- Publication number
- JPS61168948A JPS61168948A JP60009039A JP903985A JPS61168948A JP S61168948 A JPS61168948 A JP S61168948A JP 60009039 A JP60009039 A JP 60009039A JP 903985 A JP903985 A JP 903985A JP S61168948 A JPS61168948 A JP S61168948A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- aluminum
- aluminum layer
- lead
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
し技術分野〕
本発明は、各種半導体装置に用いて好適なＩＪ −ドフ
レームに関し、特に耐湿性の向上と大喝なコストダウン
とが要求される半導体集積回路に適用して有効な技術に
関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to an IJ-doped frame suitable for use in various semiconductor devices, and is particularly applicable to semiconductor integrated circuits that require improved moisture resistance and significant cost reduction. It is related to effective technology.
半導体装置の低コスト化、高信頼性を達成すべく本願出
願人は、アルミニウム（ＡＪ ｉ線を用いたボーＭボ／
ディング技術の開発に成功した。この技術は、日経マグ
ロウヒル社発行、日経エレクトロニクス誌、１９８４年
６月１１日号、Ｐ９５〜Ｐ１０２に開示されている。In order to achieve low cost and high reliability of semiconductor devices, the applicant has developed aluminum
succeeded in developing the ding technology. This technique is disclosed in Nikkei Electronics magazine, published by Nikkei McGraw-Hill, June 11, 1984, pages 95 to 102.
本発明者らは、このアルミ・ボール・ボンディング技術
を、量産品の樹脂封止半導体装置（以下率ＫＩＣとも称
す）に適用し、低コストでしかも耐湿性の高いＩｃを提
供すべく、実用化検討を行なった結果、種々の改善すべ
き点があることに黒付いた。The present inventors applied this aluminum ball bonding technology to mass-produced resin-encapsulated semiconductor devices (hereinafter also referred to as KIC), and aimed to commercialize it in order to provide ICs with low cost and high moisture resistance. As a result of our review, we found that there are various points that need improvement.
すなわち、単にボンディング方法を、金ボールボンディ
ング技術からアルミ・ボール・ボンディング技術に変更
しただけでは、十分に耐湿性の向上ができないというこ
とである。それは、後述するごとき、リードフレーム材
料やリードフレームにメッキする金属の椙類及びその部
分も問題となってくるということである。In other words, simply changing the bonding method from gold ball bonding technology to aluminum ball bonding technology cannot sufficiently improve moisture resistance. This means that, as will be described later, the lead frame material, the metal plates plated on the lead frame, and their parts also become problems.
本発明は、上記したアルミ・ボール・ボンディング技術
を安価な樹脂封止半導体装置に適用する忙あたり、アル
ミ・ボール・ボンディング技術を使用したことＫよる耐
湿性の向上効果ばかりではなく、その他の耐湿性改善対
策をもリードフレームに施しそれらの相乗効果により、
高い耐湿性を有するＩＣを開発する過程の中で生まれた
ものである。While applying the above-mentioned aluminum ball bonding technology to inexpensive resin-sealed semiconductor devices, the present invention aims to improve moisture resistance not only by using the aluminum ball bonding technology, but also to improve other moisture resistance. We also applied measures to improve the quality of the lead frame, and due to their synergistic effect,
It was created in the process of developing an IC with high moisture resistance.
Ｌ発明の目的〕
本発明の目的は、耐湿性が良好である上に安価な半導体
装置を提供することにある。LObject of the Invention An object of the invention is to provide a semiconductor device that has good moisture resistance and is inexpensive.
本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面から明らかになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に述べれば、下記の通りである。A brief summary of typical inventions disclosed in this application is as follows.
すなわち、本発明のリードフレームは、そのタブ、タブ
吊りリード、外部接続端子の少なくとも樹脂封止がなさ
れる部分にアルミニウム層を有している。このアルミニ
ウム層の存在により、リードフレームとレジン材との密
着性が良好釦なるため、半導体装置の耐湿性が良好にで
きる。That is, the lead frame of the present invention has an aluminum layer on at least the resin-sealed portions of the tab, tab suspension lead, and external connection terminal. The presence of this aluminum layer provides good adhesion between the lead frame and the resin material, so that the semiconductor device can have good moisture resistance.
以上の構成により、本発明の目的を連成する。The above configuration achieves the objectives of the present invention.
本発明の説明にさきだって、まず、本発明者らの行なっ
た、アルミ・ボール−ボンディング技術の実用化検討に
よりあきらかとなった問題点について説明する・
樹脂封止半導体装置に用いられるリードフレーム（４２
％ニッケル入り鉄合金）のタブやインナーリード先端部
分は、金（Ａｕ）、銀（Ａｇ ）等のメッキ層が施され
ている。これらのメッキ層は、半導体ベレットとタブの
接着やインナーリードとＡｕからなるボンディングワイ
ヤとの接着を良好とするために不可欠である。Before explaining the present invention, we will first explain the problems that became clear through the practical application study of aluminum ball bonding technology conducted by the present inventors. 42
% nickel-containing iron alloy) and the tips of the inner leads are plated with gold (Au), silver (Ag), etc. These plating layers are essential for achieving good adhesion between the semiconductor pellet and the tab and between the inner lead and the bonding wire made of Au.
しかし、（１１Ａｕ、Ａｇ等はコストが高く、低価格を
その特徴とする樹脂封止半導体装置には不向きである。However, (11Au, Ag, etc.) are high in cost and are not suitable for resin-sealed semiconductor devices, which are characterized by low cost.
さらに、（２）アルミ・ボール・ボンディング技術を用
いてボンディングを行なった場合、ＡＡｔ、ｉ！とＡｕ
メッキ、Ａｇメッキとの接合部分に何らかの原因で水分
が侵入してきた時を想定すると、ＡＪとＡｕ、またはＡ
ｇとの接触電位差の違いにより、局部的に電池が発生し
てしまう。この電池により、Ａｌがイオン化しＣＡＡ！
線が腐蝕し、ＩＣの信頼度の低下をまねいてしまう。（
３１水分がＡｌ線とＡｕメッキ（Ａｇメッキ）との接合
部分に侵入してこなければ上記した問題は発生しないが
、Ａｕメッキ（Ａｇメッキ）と樹脂封止体を構成するレ
ジン（エポキシ系樹脂）とは接着力が弱いため、ＩＣ内
への水分の侵入は容易と考えられる。Furthermore, (2) when bonding is performed using aluminum ball bonding technology, AAt,i! and Au
Assuming that moisture has entered the joint between plating and Ag plating for some reason, AJ and Au or A
Due to the difference in contact potential with g, a battery is generated locally. With this battery, Al is ionized and CAA!
The wires will corrode, leading to a decrease in the reliability of the IC. (
31 If moisture does not enter the joint between the Al wire and the Au plating (Ag plating), the above problem will not occur, but if the Au plating (Ag plating) and the resin (epoxy resin) that constitutes the resin sealing body Since the adhesive force is weak, it is thought that moisture can easily enter into the IC.
以上簡単に問題点を説明した。The problems have been briefly explained above.
次に図面を用いて本発明について説明する。Next, the present invention will be explained using the drawings.
第１図は本発明を適用した半導体装置用リードフレーム
の１実施例を示す平面図である〇本実施例の特徴は、タ
ブ、タブ吊りリード、インナーリードにアルミニウム層
な形成したことにある。FIG. 1 is a plan view showing one embodiment of a lead frame for a semiconductor device to which the present invention is applied. The feature of this embodiment is that an aluminum layer is formed on the tab, the tab suspension lead, and the inner lead.
第１図は本発明を適用したリードフレームの一例を示す
ものであり、１〜４４はインナーリードな示し、その中
央部にタブ５１がタブ吊りリード５２ ａ、 ５２
ｂによって保持されている。FIG. 1 shows an example of a lead frame to which the present invention is applied. Reference numerals 1 to 44 indicate inner leads, and a tab 51 is located in the center of the lead frame, and tab hanging leads 52a, 52 are provided.
It is held by b.
ここで注目すべきは、上記タブ５１．タブ吊りリード５
２ ａ、 ５２ ｂ−更に各インナーリード１〜４４
の先端部にアルミニウムによるメッキ層５３．５４が施
されていることである。図示の位置にアルミニウム層を
施すことにより、耐湿性を著しく向上させることができ
る。What should be noted here is the tab 51. Tab hanging lead 5
2 a, 52 b-further each inner lead 1 to 44
Plating layers 53 and 54 made of aluminum are applied to the tip of the tip. By applying an aluminum layer at the locations shown, the moisture resistance can be significantly improved.
すなわち、アルミニウムとパッケージに使用されるレジ
ン材とは接着性が極めてよい。半導体集積回路（以下に
お（・”ＣＩＣという）Ｋ水分の浸透は、タブ吊りリー
ド５２ａ、５２ｂからタブ５１、更に第２図についてｖ
ｋ述するボンディングワイヤー、ＩＣチップへの径路が
一番多く、次いで各インナーリード１〜４４を介して浸
透する水分が多い。また、パッケージ自体を浸透する水
分もある。That is, aluminum and the resin material used for the package have extremely good adhesion. Semiconductor integrated circuit (hereinafter referred to as "CIC") K moisture permeates from the tab suspension leads 52a, 52b to the tab 51, and further as shown in FIG.
The route to the bonding wire and the IC chip as described in k is the largest, and the second largest amount of moisture permeates through each inner lead 1 to 44. There is also some moisture that permeates the packaging itself.
し−かじ、上記の如くレジン材とアルミニウム層との接
着性がよいため、浸透した水分はアルミニウム層の形成
位置で、それ以上の浸透が困難になリ、これにより耐湿
性が向上する。However, as mentioned above, since the adhesiveness between the resin material and the aluminum layer is good, it becomes difficult for the moisture that has penetrated to penetrate further at the position where the aluminum layer is formed, thereby improving the moisture resistance.
更に注目すべきことは、浸透する水分により多く含有さ
れていると思われる（１（塩素）に対する作用である。What is also noteworthy is the effect on (1 (chlorine)), which is thought to be contained in a large amount in the water that permeates.
イオン化されたＣ１−は、水分とともにＩＣチップ方向
に浸透するが、３価の元素であるＣ１−と１価の元素で
あるアルミニウムとが等価になったとき、ＣＩ−によっ
てアルミニウムの腐蝕が開始される。換言すれば、アル
ミニウムの腐蝕によって、Ｃ１−の消費が行なわれる。Ionized C1- permeates toward the IC chip along with moisture, but when C1-, a trivalent element, and aluminum, a monovalent element, become equivalent, corrosion of aluminum begins due to CI-. Ru. In other words, C1- is consumed by corrosion of aluminum.
したがって、ＣＩ−が継続して供給され、かつタブ吊り
リード５２ ａ、 ５２ ｂ、更にタブ５１に形成さ
れたアルミニウム層５３が腐蝕しきれないうちは、ＩＣ
チップへの悪影響を阻止することかできる。Therefore, until CI- is continuously supplied and the tab suspension leads 52a, 52b and the aluminum layer 53 formed on the tab 51 are not fully corroded, the IC
It is possible to prevent adverse effects on the chip.
キして、各インナーリード１〜４４についても、アルミ
ニウム層５４を形成することにより、上記同様の効果が
得られる。By forming the aluminum layer 54 on each of the inner leads 1 to 44, the same effect as described above can be obtained.
第２図、第３図、第４図の如（リードフレームにアルミ
ニウム層を形成すれば、上記した効果はさらに向上する
。If an aluminum layer is formed on the lead frame as shown in FIGS. 2, 3, and 4, the above-mentioned effects will be further improved.
第２図は、インナーリード１〜４４及びタブ５１、タブ
吊りリード５２ａ、５２ｔ）の樹脂により封止される部
分５６（図面にお〜・ては破線で囲まれた部分）内にア
ルミニウム層５３．５４を形成したリードフレームを示
す。６４はダイパー、６５はアウタリードを示す。FIG. 2 shows an aluminum layer 53 in a resin-sealed portion 56 (a portion surrounded by a broken line in the drawing) of the inner leads 1 to 44, the tab 51, and the tab suspension leads 52a and 52t. A lead frame formed with .54 is shown. Reference numeral 64 indicates a diper, and reference numeral 65 indicates an outer lead.
第３図は、アルミニウム層５３，５４の形成領域ｔダイ
パー６４内のインナーリード１〜４４、タブ５１及びタ
ブ吊りリード５２ａ、５２ｂの全面に形成したリードフ
レームを示す。FIG. 3 shows a lead frame formed on the entire surface of the inner leads 1 to 44, the tab 51, and the tab suspension leads 52a and 52b in the forming region t-diaper 64 of the aluminum layers 53 and 54.
第４図は、アルミニウム層５５をダイパー６４の途中ま
で形成したリードフレームを示す。FIG. 4 shows a lead frame in which the aluminum layer 55 is formed halfway up the dieper 64.
上記の如く少なくとも樹脂封止される部分にアルミニウ
ム層５３．５４．５５を形成することにより、アルミニ
ウムと樹脂であるレジン材との良好な接着性により、レ
ジン材とインナーリードｌ〜４４、タブ５１及びタブ吊
りリード５２ａ。By forming the aluminum layers 53, 54, 55 on at least the parts to be resin-sealed as described above, good adhesion between aluminum and the resin material allows the inner leads l to 44 and the tab 51 to be bonded to the resin material. and a tab hanging lead 52a.
５２ｂとが強固に接着するため耐湿性の向上が計れる。52b, the moisture resistance can be improved.
さらに破線で示されるモールドライン（樹脂により封止
される部分）５５とインナーリード１〜４４の先端及び
タブ５１までの長い距離の間すべてにアルミニウム層が
存在することより、もし、（１−イオンを含む水分がモ
ールドライン５５からリードフレームに沿って浸入して
きても、その水分の浸入部分（モールドライン付近）の
アルミニウム層だけが腐蝕してＣＩ−イオンが全て消費
される。換言すればモールドライン付近のアルミニウム
層の腐蝕により、ＣＩ−イオンが完全に消費され、イン
ナーリード１〜４４の先端部分やタブ５１近傍にまで水
が浸入する忙は長時間を用するということである。この
ことは、ＩＣの耐湿性の向上を意味する〇
上記では、リードフレームの平面図を用いてアルミニウ
ム層の形成場所を図面を用−・℃説明した０次′に、そ
のアルミニウム層とリードフレームとの断面について耐
湿性の高いものから順に説明する。Furthermore, since the aluminum layer exists all along the long distance between the mold line (the part sealed with resin) 55 shown by the broken line, the tips of the inner leads 1 to 44, and the tab 51, it can be seen that if (1-ion Even if water containing water enters from the mold line 55 along the lead frame, only the aluminum layer in the part where the water enters (near the mold line) will be corroded and all the CI- ions will be consumed.In other words, the CI- ions will be consumed. Due to the corrosion of the nearby aluminum layer, the CI- ions are completely consumed, and it takes a long time for water to enter the tips of the inner leads 1 to 44 and the vicinity of the tab 51. , which means improved moisture resistance of the IC 〇 In the above, the plan view of the lead frame is used to show where the aluminum layer is formed. These will be explained in order of moisture resistance.
水分の浸入はリードフレームやタブ吊りリードの上面、
下面及び両側面から浸入するためアルミニウム層はリー
ドフレームの上面、下面及び側面全てに形成するのが耐
湿性の向上の点で好まし〜・。Water can get into the top of the lead frame or tab-suspended lead.
Since the aluminum layer penetrates from the bottom and both sides, it is preferable to form the aluminum layer on the top, bottom, and sides of the lead frame to improve moisture resistance.
また、リードフレームの上面や下面、リードフレームの
上面だけに形成しても十分な効果を有する。しかし、量
産性の点から見た場合、リードフレームの上面にアルミ
ニウム層を形成する方法が低コストでしかも耐湿性も十
分であるため好ましいと思われる。Further, sufficient effects can be obtained even if the film is formed only on the upper surface or lower surface of the lead frame, or only on the upper surface of the lead frame. However, from the point of view of mass production, the method of forming an aluminum layer on the top surface of the lead frame is considered preferable because it is low cost and has sufficient moisture resistance.
〔実施例２〕
次に、本発明の第２実施例を第★図を参照して説明する
。[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIG.
なお、本実施例と上記第１実施例と同一の部分には同一
の符号を付し、説明の重複を避けるものとする。Note that the same parts as in this embodiment and the first embodiment described above are given the same reference numerals to avoid duplication of explanation.
本実施例の特徴は、第１図に示したリードフレームをＩ
Ｃに用いたことにある。The feature of this embodiment is that the lead frame shown in FIG.
It was used for C.
タブ５１上には、ｌＣチップ６１が設けられ、各パッド
６２と各インナーリード１〜４４の先端部、すなわちア
ルミニウム層５４の形成位置とは、アルミニウム線６３
に工つ℃ボンディングされている。なお、６４はタイバ
ーであり、この部分は切りとられ、その外部に示したリ
ード部（一部のみ図示）６５が外部接続端子となる。An IC chip 61 is provided on the tab 51, and the tips of each pad 62 and each inner lead 1 to 44, that is, the position where the aluminum layer 54 is formed, are located on the aluminum wire 63.
It is bonded in the process. Note that 64 is a tie bar, this portion is cut off, and a lead portion 65 shown outside (only a portion is shown) serves as an external connection terminal.
そして、上記構成によればアルミニウム線６３とアルミ
ニウム層５４とがボンディングされるのであるから、両
者の間に電位差がない上に、イオン化傾向が同じである
ため、いわゆる局部電池ができ忙くい。したがって、ボ
ンディング位置におけるアルミニウムの腐蝕現象の発生
がすくなく、これが品質向上の一層となる。According to the above configuration, since the aluminum wire 63 and the aluminum layer 54 are bonded, there is no potential difference between them, and their ionization tendency is the same, so that a so-called local battery is formed. Therefore, corrosion of aluminum at the bonding position is less likely to occur, which further improves quality.
なお、インナーリード１〜４４のボンディング位置に、
金あるいは銀をメッキし、アルミニウム線を用いてボン
ディングした場合は、アルミニウム線と金あるいは銀と
の間に電位差が発生し、接続位置において腐蝕が発生す
る。In addition, at the bonding positions of inner leads 1 to 44,
When gold or silver is plated and bonded using an aluminum wire, a potential difference occurs between the aluminum wire and the gold or silver, causing corrosion at the connection location.
しかし、本発明を適用したＩＣによれば、上記理由によ
り、接続位置忙おいて腐蝕が発生せず、製品信頼度の向
上等の効果か得られ°る。However, according to the IC to which the present invention is applied, for the above-mentioned reasons, corrosion does not occur even if the connection position is busy, and effects such as improved product reliability can be obtained.
また、パッケージをレジン材にて封止する時、封止金型
とリードフレームとのすきまより、レジンがもれ、いわ
ゆる、レジンパリが形成されてしまう。然るに、本発明
の第２図、第３図、第４図のリードフレームを適用した
ＩＣによれば、上記パリの形成を低減することが可能に
なる。Furthermore, when the package is sealed with a resin material, the resin leaks through the gap between the sealing mold and the lead frame, resulting in the formation of so-called resin leaks. However, according to an IC to which the lead frames of FIGS. 2, 3, and 4 of the present invention are applied, it is possible to reduce the formation of the above-mentioned flash.
この場合、各インナーリード１〜４４の全体、或いは第
６図に示すパッケージ７１の外周囲の外までアルミニウ
ム層を形成する。但し、アルミニウムにははんだが付き
にくい為融溶にはリードフレームにはんだ付をする。そ
して、第２図、第３図、第４図の如く構成されたリード
フレームを金型＄１．８２内の所定位置く固定し、注入
孔（図示せず）からパッケージ７１となるレジン材を注
入する。この際、アルミニウム層は柔らか〜・ので、金
ｆｉ８１．８２の圧力により℃つぶれるようになり、金
型とリードフレームとのすきまをふさぎパリが表れない
。リードフレームに使用されるＮｉ４２％入り鉄合金は
竪いため、金型８１．８２の圧力でもつぶれずレジンの
パリが容易にでてしまう。レジンバリは、はんだの潰き
を悪くしたり、外観不艮の原因となるため、防止しなけ
ればいけない。そのため、レジンバリ取工程等の人手な
用する工程が必要となり、ＩＣのコストアップの原因と
なっている。さらに、近年の面付実装品においては、重
大な問題となっている。In this case, the aluminum layer is formed over the entirety of each inner lead 1 to 44 or to the outside of the outer periphery of the package 71 shown in FIG. However, since solder is difficult to adhere to aluminum, the lead frame must be soldered to melt it. Then, the lead frame configured as shown in FIGS. 2, 3, and 4 is fixed at a predetermined position in the mold, and the resin material that will become the package 71 is poured through the injection hole (not shown). inject. At this time, since the aluminum layer is soft, it will be crushed by the pressure of the gold fi81.82, closing the gap between the mold and the lead frame and preventing any cracks from appearing. The 42% Ni-containing iron alloy used for the lead frame is vertical, so it does not collapse under the pressure of the mold 81, 82, and resin flakes easily appear. Resin burrs must be prevented because they can cause poor solder crushing and an unsatisfactory appearance. Therefore, a manual process such as a resin deburring process is required, which causes an increase in the cost of the IC. Furthermore, this has become a serious problem in recent surface-mounted products.
上記パリの低減は、ＩＣの外観の仕上げ感が良好になる
ことを意味し、いわゆる外観不艮を低減して製品歩留り
を向上させるとともに、顧客に不快感を与えない、とい
う利点もある。Reduction of the above-mentioned Paris means that the finish of the external appearance of the IC becomes better, which has the advantage of reducing so-called appearance discoloration, improving product yield, and not causing discomfort to customers.
し効果〕
（１）、リードフレームのタブ、タブ吊りリード、イン
ナーリードにメッキ等によりアルミニウム層を形成した
ので、上記アルミニウム層とパッケージ材であるレジン
との接着性が良好になり、タブ吊りリード等を伝わって
浸透しようとする水分を低減し、ＩＣの耐湿性を向上さ
せることができる０（２）、インナーリードのボンディ
ング位置にアルミニウム層を形成し、アルミニウム線に
よるワイヤボンディングを行うことにエリ、ＩＣの生産
コストを低減させる、と〜・う効果が得られる。Effects] (1) Since an aluminum layer is formed by plating on the lead frame tab, tab suspension lead, and inner lead, the adhesion between the aluminum layer and the resin package material is good, and the tab suspension lead 0(2) can improve the moisture resistance of the IC by reducing moisture that tries to penetrate through the inner leads. , the effect of reducing the production cost of IC can be obtained.
（３）、浸透する水分中に含まれているイオン化した元
素と上記アルミニウム層との化学的変化にエリ、イオン
化した元素の浸透を低減することができる。(3) Due to the chemical change between the ionized elements contained in the permeating water and the aluminum layer, the permeation of the ionized elements can be reduced.
（４）、アルミニウムが軟質であるため、外部接続端子
のパリを金型の圧力により低減し、外観不良を低減する
、という効果かえられる。(4) Since aluminum is soft, it is possible to reduce the appearance of external connection terminals by the pressure of the mold, thereby reducing appearance defects.
以上に本発明者により℃なされた発明を実施例にもとづ
き具体的に説明したが、本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることは言うまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
例えば、上記各実施例では、タブ吊りリードはタブ下げ
構造になされているが、これに限定されず他の構造のも
のであってよい。For example, in each of the above embodiments, the tab hanging lead has a tab hanging structure, but is not limited to this and may have other structures.
また、タブ吊りリードの全体にアルミニウム層を形成し
てもよい。この場合、水分の浸透防止、並びにイオン化
された元素の浸透防止作用は、アルミニウム層の距離に
対応して大となり、信頼度もより一層向上する。Alternatively, an aluminum layer may be formed over the entire tab suspension lead. In this case, the effect of preventing moisture penetration and ionized element penetration increases in proportion to the distance of the aluminum layer, and reliability is further improved.
〔利用分野〕
以上の説明では、主として本発明者によってなされた発
明をその背景となった技術分野であるす−ドフレームに
適用した場合につい℃説明したが、それに限定されず、
例えば上記形状の半導体集積回路以外のデエアルインラ
イン型のＩＣ，いわゆる面付は構造のｌＣにも広く利用
することができる。[Field of Application] In the above explanation, the invention made by the present inventor has mainly been explained in the case where it is applied to a frame, which is the technical field in which the invention is based, but the invention is not limited thereto.
For example, in-line type ICs other than semiconductor integrated circuits having the above-mentioned shape, so-called surface mounting, can be widely used for IC structures.
テ
第含図は本発明の第２実施例を示すＩｃの内部構造の平
面図を示し、
第↓図は上記ＩＣの製造工程を示す要部の断面図を示す
。Figures 1 and 2 show a plan view of the internal structure of an IC showing a second embodiment of the present invention, and Figures 2 and 3 show cross-sectional views of essential parts showing the manufacturing process of the above IC.
１〜４４・・・インナーリード、５１・・・タブ、５２
ａ、５２ｂ・・・タブ吊りリード、５３．５４・・・ア
ルミニウム層、６１・・・ＩＣチップ、６２・・・パッ
ド、６３・・・アルミニウム線、６４・・・タイバー、
７１・・・パッケージ、８１．８２・・・金型。1 to 44...Inner lead, 51...Tab, 52
a, 52b... Tab suspension lead, 53.54... Aluminum layer, 61... IC chip, 62... Pad, 63... Aluminum wire, 64... Tie bar,
71...Package, 81.82...Mold.
、７′″二・、
代理人 弁理士 小 川 勝 男 −′第 １
図,7'''2., Agent Patent Attorney Katsuo Ogawa -'1st
figure
Claims (1)
るタブ吊りリード及び外部接続端子にアルミニウム層を
形成したことを特徴とする半導体装置用リードフレーム
。 ２、半導体チップが載置されるタブ、上記タブを保持す
るタブ吊りリード及び外部接続端子にアルミニウム層を
形成したリードフレームを用い、上記半導体チップのパ
ッドと上記外部接続端子のアルミニウム層形成位置とを
アルミニウム線にて結線したことを特徴とする半導体装
置。[Scope of Claims] 1. A lead frame for a semiconductor device, characterized in that an aluminum layer is formed on a tab on which a semiconductor chip is placed, a tab hanging lead for holding the tab, and an external connection terminal. 2. Using a lead frame in which an aluminum layer is formed on the tab on which the semiconductor chip is placed, the tab suspension lead that holds the tab, and the external connection terminal, the aluminum layer formation position of the pad of the semiconductor chip and the external connection terminal is determined. A semiconductor device characterized in that these are connected with aluminum wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60009039A JPS61168948A (en) | 1985-01-23 | 1985-01-23 | Leadframe for semiconductor device and semiconductor device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60009039A JPS61168948A (en) | 1985-01-23 | 1985-01-23 | Leadframe for semiconductor device and semiconductor device using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61168948A true JPS61168948A (en) | 1986-07-30 |
Family
ID=11709503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60009039A Pending JPS61168948A (en) | 1985-01-23 | 1985-01-23 | Leadframe for semiconductor device and semiconductor device using same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61168948A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6047467A (en) * | 1995-10-12 | 2000-04-11 | Vlsi Technology, Inc. | Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads |
| JP2014187180A (en) * | 2013-03-22 | 2014-10-02 | Mitsubishi Materials Corp | Assembly for semiconductor device, substrate for power module and power module |
-
1985
- 1985-01-23 JP JP60009039A patent/JPS61168948A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6047467A (en) * | 1995-10-12 | 2000-04-11 | Vlsi Technology, Inc. | Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microelectronics packages via conduction through the package leads |
| JP2014187180A (en) * | 2013-03-22 | 2014-10-02 | Mitsubishi Materials Corp | Assembly for semiconductor device, substrate for power module and power module |
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