JPS6175554A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6175554A
JPS6175554A JP59196664A JP19666484A JPS6175554A JP S6175554 A JPS6175554 A JP S6175554A JP 59196664 A JP59196664 A JP 59196664A JP 19666484 A JP19666484 A JP 19666484A JP S6175554 A JPS6175554 A JP S6175554A
Authority
JP
Japan
Prior art keywords
wire
resin
gold
semiconductor device
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59196664A
Other languages
Japanese (ja)
Inventor
Masamoto Akeyama
明山　正元
Susumu Okikawa
進 沖川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59196664A priority Critical patent/JPS6175554A/en
Publication of JPS6175554A publication Critical patent/JPS6175554A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4554—Coating
    • H01L2224/4557—Plural coating layers
    • H01L2224/45572—Two-layer stack coating
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/01—Chemical elements
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To strengthen the bonding between wire surface and package forming resin as compared with that of wire consisting of gold only and prevent exfolia tion at the interface of wire and resin by electrically connecting pellet and lead with a wire consisting of copper-clad gold. CONSTITUTION:A wire 6 to be used for electrical connection between pellet 1 and lead 5 is formed by placing gold wire 6a with copper 6b. The physical and chemical characteristics of gold can be used and bonding ability of copper with resin can also be utilized by forming a wire through coverage of copper 6b at the surface. Thereby, stronger bonding between package forming resin 7 and lead 6 can be attained in comparison with the case where a wire consisting only of gold is used for electrical connection.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、ペレットとリードとの電気的接続に使用され
るワイヤに関し、半導体装置の耐湿性向上に適用して有
効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a wire used for electrical connection between a pellet and a lead, and relates to a technique that is effective when applied to improving the moisture resistance of a semiconductor device.

〔背景技術〕[Background technology]

半導体装置の１つに、いわゆる樹脂封止型半導体装置が
ある。これは、通常リードフレームのベレット取イ１部
であるタブにペレットを取りイ」けた後、該ペレットと
り−ト−とをワイヤで電気的に接続を行い、次いでこれ
らペレットおよびワイヤ等をエポキシ樹脂等で所定形状
にモールドして封止することによりパンケージを形成し
、さらにその後リードを切断成形することにより完成さ
れてなるものである。One type of semiconductor device is a so-called resin-sealed semiconductor device. After the pellet is placed in the tab, which is the first part of the pellet receptacle of the lead frame, electrical connection is made between the pellet receptacle and the tab, and then these pellets and wires are attached to the tab using epoxy resin. A pancage is formed by molding and sealing into a predetermined shape, and then the leads are cut and molded to complete the package.

前記半導体装置において、ペレットとり−１・との電気
的接続に用いるワイヤとして、通常金ワイヤが使用され
ている。In the semiconductor device, a gold wire is usually used as the wire for electrical connection with the pellet receiver-1.

ところが、金ワイヤはパッケージ形成樹脂と接着性が悪
いため、該ワイヤ表面と樹脂との間でＩ、１１離が起こ
り、極めてわずかな隙間が両者の界面に発生し易いとい
う問題がある。However, since the gold wire has poor adhesion to the package forming resin, there is a problem in that I, 11 separation occurs between the surface of the wire and the resin, and an extremely small gap is likely to occur at the interface between the two.

一方、前記半導体装置のリードは、一部がパッケージ形
成樹脂に埋設され、その先端部に前記金ワイヤが接続さ
れている。この樹脂に埋設されているリードは、前記リ
ードの切断成形工程等において樹脂との剥がれが生し、
樹脂とリードとの界面に隙間が発生し易いという問題も
ある。On the other hand, a portion of the lead of the semiconductor device is embedded in a package forming resin, and the gold wire is connected to the tip end of the lead. The leads embedded in this resin may peel off from the resin during the lead cutting and molding process, etc.
Another problem is that gaps are likely to occur at the interface between the resin and the lead.

したがって、外部からの影響、たとえば水分等の腐食性
物質がペレットのアルミニウム電極等を腐食に至らしめ
る経路は、前記り−１・と樹脂との界面に牛した隙間お
よび金ワイ−・と樹脂との界面に生した隙間の両者から
なるもので、水分等がこれら隙間を伝って浸透していき
、ポンティングパンｌに到達し、該パノ１−を、ひいて
は内部配線等を腐食させるものである。Therefore, the routes through which external influences, such as corrosive substances such as moisture, lead to corrosion of the aluminum electrodes of the pellets are the gaps formed at the interface between the metal wire and the resin as described above. It consists of gaps created at the interface between the two, and moisture, etc. penetrates through these gaps, reaches the ponting pan, and corrodes the pan and, by extension, the internal wiring, etc. .

なお、樹脂材１１−型半導体装置については、王業調査
会、１９８０年１月１５日発行ｒｌｃ化実装技術ＪＰＩ
３７〜Ｐ１３９に説明されている。Regarding resin material 11-type semiconductor devices, please refer to the RLC Mounting Technology JPI published by Wang Ying Research Group, January 15, 1980.
37 to P139.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ペレットとり−トとの電気的接続のた
めに用いられるワイヤに関し、樹脂封止型半導体装置の
面Ｊ湿性向上に適用して有効な技術を提（Ｊｊすること
にある。SUMMARY OF THE INVENTION An object of the present invention is to provide an effective technique for improving surface moisture of a resin-sealed semiconductor device regarding a wire used for electrical connection with a pellet tray.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添（＝Ｊ図面外ら明らかになるであ
ろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Ｃ発明の概要〕 本願において開示される発明のうら代表的なものの概要
を簡単に説明すれば、次の通りである。C. Summary of the Invention] A brief summary of the typical inventions disclosed in this application is as follows.

ずなわら、樹脂材１ト型半導体装置について、ペレ・ノ
ドとり−１・との電気的接続を、金に樹脂との接着性の
良い銅を被覆してなるワイヤで行うことにより、ワイヤ
と樹脂との界面に隙間が発生ずることを防止できること
より、半導体装置の耐湿性を向」ニさせることができる
ものである。However, for the resin-made 1-T type semiconductor device, electrical connection with the Pele Nodori-1 can be made using a wire made of gold coated with copper, which has good adhesion to the resin. By preventing the formation of gaps at the interface with the resin, the moisture resistance of the semiconductor device can be improved.

また、前記ワイヤの被覆銅の表面に酸化膜を形成したワ
イヤを用いて電気的接続を行うことにより、樹脂との接
着性をさらに向上させ、一段と面ｌ湿性を向−ヒさせる
と同時に、ワイヤに絶縁性が付与されることより、ワイ
ヤ間の接触またはワイヤとペレットコーナー等との接触
によるショートの発生をも防止できるものである。In addition, by making an electrical connection using a wire with an oxide film formed on the surface of the coated copper of the wire, the adhesion with the resin is further improved, and at the same time, the surface moisture is further improved. By imparting insulation properties to the wires, it is possible to prevent the occurrence of short circuits due to contact between wires or contact between wires and pellet corners or the like.

〔実施例１〕 第１図（ａｌは、本発明による実施例１である樹脂封止
型半導体装置において、ペレットとり一部との電気的接
続のために使用されているワイヤを、その横断面図で示
すものである。[Example 1] Figure 1 (al is a cross-sectional view of a wire used for electrical connection with a part of the pellet tray in a resin-sealed semiconductor device according to Example 1 of the present invention) This is shown in the figure.

第１図＋ｂ＋は、本実施例１の半導体装置をそのほぼ中
心を切る面における断面図で示すものである。FIG. 1+b+ is a cross-sectional view of the semiconductor device of Example 1 taken approximately at its center.

本実施例１の半導体装置は、ペレット１がタブ２ムこ金
−シリコン共晶３で取り付けられ、かつ該ペレットｌの
ボンディングバノト４とり−１−５の内端部とがワイヤ
６で電気的に接続された状態で、エボ；１−ン等の樹脂
７を所定形状にモールドして刺止するごとにより、パッ
ケージ形成されてなるものである。また、前記リート′
５はパッケージ８の側方で下方に折り曲げられ、基板へ
の実装に適した形状に成形されている。In the semiconductor device of Example 1, the pellet 1 is attached with a tab 2 and a gold-silicon eutectic 3, and the inner end of the bonding plate 4 of the pellet 1-1-5 is electrically connected with a wire 6. A package is formed by molding a resin 7 such as Evo-1 into a predetermined shape and pricking the resin 7 in the connected state. In addition, the REIT'
5 is bent downward at the side of the package 8 and formed into a shape suitable for mounting on a board.

本実施例１の特徴は、ペレノ１−１とり−ト５との電気
的接続に使用されるワイヤにある。The feature of the first embodiment lies in the wire used for electrical connection with the pereno 1-1 tray 5.

すなわぢ、本実施例のワイヤ６は、前記第１図（ａｌに
その断面を示すように、金６ａの周囲に銅６ｂをめっき
等の方法で被覆してなるものである。In other words, the wire 6 of this embodiment is made by coating gold 6a with copper 6b by a method such as plating, as the cross section is shown in FIG. 1 (al).

このように、表面に銅６ｂを被覆してワイヤ６を形成す
るごとにより、金が有する優れた物理的、化学的特性を
活かした上で、銅が有する樹脂との接着性をも利用する
ことができるものである。In this way, by coating the surface with copper 6b to form the wire 6, it is possible to take advantage of the excellent physical and chemical properties of gold and also to utilize the adhesion of copper with resin. It is something that can be done.

したがって、前記電気的接続に金のみからなるワイヤを
用いる場合に比べ、パッケージ形成樹脂７とり−１６と
の強固な接着が達成されるので、一段とパッケージの耐
湿性を向」−ざ廿ることができるものである。Therefore, compared to the case where a wire made only of gold is used for the electrical connection, strong adhesion with the package forming resin 7-16 is achieved, so that the moisture resistance of the package can be further improved. It is possible.

〔実施例２〕 本発明による実施例２である半導体装置は、前記実施例
１と同様の樹脂封止型半導体装置である。[Example 2] A semiconductor device according to Example 2 of the present invention is a resin-sealed semiconductor device similar to Example 1.

本実施例２の特徴は、前記実施例１で電気的接続に使用
したワイヤ６の表面に酸化膜を形成したことにある。す
なわち、ワイヤ６がその断面を第２図に示す如く、金６
ａに被覆されている銅６ｂの表面に銅の酸化膜６ｃが形
成された構造からなるものである。The feature of this second embodiment is that an oxide film is formed on the surface of the wire 6 used for electrical connection in the first embodiment. That is, the cross section of the wire 6 is shown in FIG.
It has a structure in which a copper oxide film 6c is formed on the surface of a copper 6b coated with a copper oxide film 6c.

このように、ワイヤ６の最外表面に酸化膜６ｃを形成す
ることにより、ワイヤ６と樹脂７との接着を極めて強固
にすることができるため、前記実施例１より更に大巾に
パッケージの耐湿性を向上させることができるものであ
る。In this way, by forming the oxide film 6c on the outermost surface of the wire 6, the adhesion between the wire 6 and the resin 7 can be made extremely strong. It is something that can improve your sexuality.

また、前記酸化膜６ｃは、たとえば酸化剤をアルカリ性
水溶液に溶解して調整した酸化浴に、前記実施例１で使
用したワイヤを所定条件下で浸漬した後、中和、水洗を
行うことにより、また必要に応して所定１品度に加熱処
理することにより形成することかできるもので、酸化浴
の種類およびｌツイヤの処理条件等により、第１酸化１
１’ｌ　（ｃ　ｕ　２（、））、第２酸化銅（ＣＩＪＯ
）またはこれら両者が共存するものとして形成されるも
のである。そして、＋ｉｉｉ記酸化脱酸化膜ｃは絶縁１
りであるため、本実施例２の半導体装置においては、ワ
イヤ６どうし７の接触またはワイヤ〔ｊとペレソｌ−コ
ーナー等との接触が発生ずる場合であってもソヨ−１・
を防止できる利点も備えている。The oxide film 6c can be formed by, for example, immersing the wire used in Example 1 in an oxidizing bath prepared by dissolving an oxidizing agent in an alkaline aqueous solution under predetermined conditions, followed by neutralization and washing with water. It can also be formed by heat treatment to a predetermined grade if necessary, and the first oxidation
1'l (c u 2(, )), cupric oxide (CIJO
) or a combination of both. The oxidation/deoxidation film c in +iii is an insulator 1.
Therefore, in the semiconductor device of the second embodiment, even when contact occurs between the wires 6 and 7 or between the wire [j and the Peresol l-corner, etc., the Soyo-1.
It also has the advantage of preventing

（効果］ （１）、樹脂封止型半導体装置について、べｌ／　ソト
とリートとの電気的接続を、金に銅を被覆してなるワイ
ヤで行うことにより、金のみからなるワイヤの場合に仕
ベワイヤ表面とパッケージ形成樹脂との接着を強化する
ことができるので、該ワイヤと樹脂との界面におけるｑ
、ＩＩ　ＸＩ（の発生を防止できる。(Effects) (1) For resin-sealed semiconductor devices, by making the electrical connection between the belt and the lead with a wire made of gold coated with copper, it is possible to Since it is possible to strengthen the adhesion between the surface of the wire and the package forming resin, q at the interface between the wire and the resin can be strengthened.
, II XI (can be prevented from occurring.

（２）、前記（１）に、Ｌす、耐湿性が優れたパッケー
ジを有する半導体装置を提供できる。(2) In accordance with (1) above, a semiconductor device having a package with excellent moisture resistance can be provided.

（３）、樹脂封１１−型半導体装置について、ベレット
とリードとの電気的接着を、金に被覆されている銅の外
表面に酸化膜を形成してなるワイヤで行うことにより、
ワイヤ表面と樹脂との接着を一段と強化することができ
るので、前記（１）に比べさらに耐湿性が向上された半
導体装置を提供できる。(3) Regarding the resin-sealed 11-type semiconductor device, by electrically bonding the bullet and the lead with a wire made of gold-coated copper with an oxide film formed on its outer surface,
Since the adhesion between the wire surface and the resin can be further strengthened, it is possible to provide a semiconductor device with further improved moisture resistance compared to (1) above.

（４）、前記（３）に記載する如く、ワイヤ表面に酸化
膜を形成することにより、該酸化膜が絶縁性であること
から、ワイヤどうしの接触またはワイヤとベレットコー
ナー等との接触が発生してもショートすることがないの
で、電気的にも極めて信頼性の高い半導体装置を提供で
きる。(4) As described in (3) above, by forming an oxide film on the wire surface, since the oxide film is insulating, contact between wires or contact between the wire and a bullet corner, etc. occurs. Since there is no short-circuit even when the semiconductor device is used, it is possible to provide a semiconductor device that is electrically extremely reliable.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、酸化膜の形成方法として酸化浴を用いる例に
ついて示したが、これに限るものでなく酸化性雰囲気中
における気相酸化等、いかなる方法によっても良いこと
はいうまでもない。For example, although an example in which an oxidation bath is used as a method for forming an oxide film has been shown, the method is not limited to this, and it goes without saying that any method may be used, such as gas phase oxidation in an oxidizing atmosphere.

〔利用分野〕[Application field]

以」二の説明では主として本発明者によってなされた発
明をその背景となった利用分野である、いわゆるＤＩＰ
型半導体装置に適用した場合について説明したが、それ
に限定されるものではなく、たとえば、樹脂封止にてパ
ッケージ形成されてなる半導体装置であれば、フラット
パッケージ型等種々のものに適用して有効な技術である
。In the following explanation, the invention made by the present inventor will be mainly explained in terms of the field of application which is its background, so-called DIP.
Although the case where the application is applied to a type semiconductor device has been described, it is not limited thereto. For example, if it is a semiconductor device whose package is formed by resin sealing, it can be applied effectively to various types such as a flat package type. It is a great technology.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図Ｆａｌは、本発明による実施例１である半導体装
置に適用されるワイヤを示す横断面図、第１図ｆｂｌは
、本実施例１の半導体装置を示す断面図、 第２図は、本発明による実施例２である半導体装置に適
用されるワイヤを示す横断面図である。 ■・・・ペレット、２・・・タブ、３・・・金−シリコ
ン共晶、４・・・ポンディングパッド、５・・・リード
、６・・・ワイヤ、６ａ・・・金、６ｂ・・・銅、６Ｃ
・・・酸化膜、７・・・樹脂、８・・・パッケージ。FIG. 1Fal is a cross-sectional view showing a wire applied to a semiconductor device according to Example 1 of the present invention, FIG. 1FBL is a cross-sectional view showing the semiconductor device of Example 1, and FIG. FIG. 2 is a cross-sectional view showing a wire applied to a semiconductor device according to a second embodiment of the present invention. ■... Pellet, 2... Tab, 3... Gold-silicon eutectic, 4... Bonding pad, 5... Lead, 6... Wire, 6a... Gold, 6b...・・Copper, 6C
... Oxide film, 7... Resin, 8... Package.

Claims (2)

【特許請求の範囲】[Claims] １．パッケージが樹脂モールドされてなり、かつペレッ
トと外部端子とが銅を金に被覆して形成されたワイヤで
電気的に接続されてなる半導体装置。1. A semiconductor device in which a package is molded with resin, and a pellet and an external terminal are electrically connected by a wire made of copper coated with gold. ２．金を被覆する銅の外表面に酸化膜が形成されている
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。2. 2. The semiconductor device according to claim 1, wherein an oxide film is formed on the outer surface of the copper covering the gold.
JP59196664A 1984-09-21 1984-09-21 Semiconductor device Pending JPS6175554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59196664A JPS6175554A (en) 1984-09-21 1984-09-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59196664A JPS6175554A (en) 1984-09-21 1984-09-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6175554A true JPS6175554A (en) 1986-04-17

Family

ID=16361539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59196664A Pending JPS6175554A (en) 1984-09-21 1984-09-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6175554A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291123A (en) * 1986-06-11 1987-12-17 Hitachi Ltd Semiconductor device and manufacture thereof
JPH0766233A (en) * 1993-08-25 1995-03-10 Nec Corp Wire bonding method of semiconductor device and bonding wire

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291123A (en) * 1986-06-11 1987-12-17 Hitachi Ltd Semiconductor device and manufacture thereof
JPH0478173B2 (en) * 1986-06-11 1992-12-10 Hitachi Ltd
JPH0766233A (en) * 1993-08-25 1995-03-10 Nec Corp Wire bonding method of semiconductor device and bonding wire

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