JPS61164266A - Semiconductor device with reinforced radiation resistance - Google Patents

Semiconductor device with reinforced radiation resistance

Info

Publication number
JPS61164266A
JPS61164266A JP542685A JP542685A JPS61164266A JP S61164266 A JPS61164266 A JP S61164266A JP 542685 A JP542685 A JP 542685A JP 542685 A JP542685 A JP 542685A JP S61164266 A JPS61164266 A JP S61164266A
Authority
JP
Japan
Prior art keywords
silicon
silicon oxide
fluorine
ion
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP542685A
Other languages
Japanese (ja)
Inventor
Fumitoshi Toyokawa
豊川 文敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP542685A priority Critical patent/JPS61164266A/en
Publication of JPS61164266A publication Critical patent/JPS61164266A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To form a semiconductor device with high reliability for a long time under the severe radioactive environment by a method wherein fluorine is contained in an insulating film formed on a semiconductor substrate. CONSTITUTION:Element isolating silicon oxide films 105b containing fluorine are formed on overall surface of substrate 1 by means of ion-implanting 106 the surface with silicon tetrafluoride. At this time, the ion-implanting energy is arbitrarily set up in terms of the film thickness of element isolating silicon oxide film 105b, a silicon oxide film 102 and a silicon nitride film 103 not to implant the silicon substrate 101 with needless fluorine. Moreover, the silicon nitride film 103 and silicon oxide films 4 on the element regions of silicon substrate 101 are removed removed to ion-implant the overall surface of silicon substrate 101 again with silicon tetrafluoride amounting to around 3X10<15>cm<-2>. At this time, the ion-implanting energy is restircted to around 20keV or less to reduce any damage due to ion-implantation in the element regions while it is recommanded to implant the element regions with ion obliquely.

Description

【発明の詳細な説明】 (技術分野) 本発明は半導体装置に関するものであり、特に耐放射線
性の強化されたMIS電界効果型半導体装置に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device, and particularly to a MIS field effect semiconductor device with enhanced radiation resistance.

近年の宇宙開発、原子力発電の発展に伴い、厳しい放射
線環境下においても、長期にわたり高い信頼性を有する
半導体装置の開発が望まれている。
With the recent development of space exploration and nuclear power generation, there is a desire to develop semiconductor devices that have high reliability over a long period of time even under harsh radiation environments.

以上の様な放射線環境下では、半導体装置の一部全構成
する絶縁膜全電離放射線が透過する際、その絶縁膜中に
電子・正孔対が多数発生し、移動速度の遅い正孔は絶縁
膜中の固定正電荷全増加させ、また絶縁膜/半導体基板
界面に界面準位を発生させる原因となる。この様にして
生じた正電荷や界面単位は、リーク電流の発生や寄生ト
ランジスタ効果等、半導体装置の特性劣化を引き起こし
ている。
Under the above-mentioned radiation environment, when all the ionizing radiation passes through the insulating film that makes up all parts of the semiconductor device, many electron-hole pairs are generated in the insulating film, and the holes that move slowly are insulated. This increases the total fixed positive charges in the film and causes interface states to be generated at the insulating film/semiconductor substrate interface. The positive charges and interface units generated in this manner cause deterioration of characteristics of semiconductor devices, such as generation of leakage current and parasitic transistor effect.

(従来技術) 従来、この様な問題解決のため、シリコンを基板とする
半導体装置に絶縁膜として用いられているシリコン酸化
膜に関し、酸化条件の最適化、あるいは化学的気相成長
法によるシリコン酸化膜の適用等の試みがなされてきて
いる。址た、塩素を酸化宴曲気中に混入して、シリコン
酸化膜中に導入し、固定正電荷を低減し、界面準位の原
因となるシリコンダングリングボンド全減少させようと
する試みもなされている。しかしながら、この様な従来
技術を用Aた場合、P型シリコン基板と、40oha度
のシリコン酸化膜から成るMOS ダイオードで、吸収
線量1メガラド(Si)程度の電離放射線により、フラ
ットバンド電圧は数ポルトル十数ボルトの負のシフト全
示し、界面準位(rl 10 ” 2〜10  eV−
・cm   程度増加することから、充分な効果をあげ
て′いるとは言いがたい。また、塩素をシリコン酸化膜
中に導入する手法についても、充分な量の塩素をシリコ
ン酸化膜中に導入するには1100℃程度以上の高温酸
化が必要であり、この様な高温酸化では界面ストレス増
加、電子トラップ減少等に工って、塩素導入による、同
性電荷及び界面準位の低減効果が相殺されるという問題
があった。
(Prior art) Conventionally, in order to solve such problems, optimization of oxidation conditions for silicon oxide films used as insulating films in semiconductor devices with silicon substrates, or silicon oxidation using chemical vapor deposition has been attempted. Attempts have been made to apply membranes. Attempts have also been made to mix chlorine into the oxidation atmosphere and introduce it into the silicon oxide film to reduce fixed positive charges and completely reduce the silicon dangling bonds that cause interface states. ing. However, when such conventional technology is used, a flat band voltage of a MOS diode made of a P-type silicon substrate and a silicon oxide film of 40 oha degree is a few poTorr due to an absorbed dose of ionizing radiation of about 1 megarad (Si). A negative shift of several tens of volts is fully shown, and the interface state (rl 10 ”2~10 eV-
・It is difficult to say that the effect is sufficient, as the increase is approximately 1 cm. Furthermore, regarding the method of introducing chlorine into the silicon oxide film, high-temperature oxidation of approximately 1100°C or higher is required to introduce a sufficient amount of chlorine into the silicon oxide film, and such high-temperature oxidation causes interfacial stress. There was a problem in that the effect of reducing isostatic charges and interface states due to the introduction of chlorine was offset by increasing the number of electrons and reducing electron traps.

(発明の目的) 本発明の目的は、かかる問題点を改善するため、塩素エ
リ反応性に富んだフッ素を、半導体基板上に形成された
絶縁膜中に導入し、厳しい放射線環境下において、従来
工Vも長期にわたり、高い信頼性を有する半導体装置を
提供することにある。
(Object of the Invention) In order to improve the above-mentioned problems, the object of the present invention is to introduce fluorine, which is highly reactive with chlorine chloride, into an insulating film formed on a semiconductor substrate. Our aim is to provide semiconductor devices that have high reliability over a long period of time.

(発明の構成) 本発明の特徴は、フッ素が、半導体基板上に形成された
絶縁膜中に導入あるいは、絶縁膜/半導体基板界面に蓄
積されている点にあり、そのフッ素の導入に除し、イオ
ン注入によって、フッ素を半導体基板表面あるいは絶縁
膜中に注入し、その後低温の熱処理を行なう点にある。
(Structure of the Invention) A feature of the present invention is that fluorine is introduced into an insulating film formed on a semiconductor substrate or is accumulated at the interface between the insulating film and the semiconductor substrate. , in which fluorine is injected into the surface of a semiconductor substrate or into an insulating film by ion implantation, and then low-temperature heat treatment is performed.

(発−の要約) この発明は半導体基板上の絶縁膜中にフッ素原子全含有
させる。これにエフ耐放射線の強化された半導体装置が
得られる。
(Summary of the Development) The present invention allows all fluorine atoms to be contained in an insulating film on a semiconductor substrate. In this way, a semiconductor device with enhanced radiation resistance can be obtained.

従来、塩素の絶縁膜への導入は、高純度に精製された塩
素系ガスを酸化雰囲気中に混入し、高温でシリコン半導
体基板の酸化を行なう手法がとられていた。この様な酸
化により、酸化膜中の固定電荷を減少させ、また、シリ
コン酸化膜/シ・リコン基板界面に発生する界面準位を
減少させて、半導体装置の耐放射線性を強化しようとす
るものである。しかし、充分な量の塩素全シリコン酸化
膜中に導入するには、酸化温度を1100′0程度以上
の高温にする必要があり、シリコン酸化膜/シリコン基
板界面のストレス増大等の原因となり不適当である。
Conventionally, chlorine has been introduced into an insulating film by mixing a highly purified chlorine-based gas into an oxidizing atmosphere and oxidizing a silicon semiconductor substrate at high temperatures. Through such oxidation, the fixed charges in the oxide film are reduced, and the interface states generated at the silicon oxide film/silicon substrate interface are reduced, thereby increasing the radiation resistance of semiconductor devices. It is. However, in order to introduce a sufficient amount of chlorine into the all-silicon oxide film, it is necessary to raise the oxidation temperature to a high temperature of approximately 1100'0 or higher, which is inappropriate as it may increase stress at the silicon oxide film/silicon substrate interface. It is.

本発明では、反応性の高いフッ素を用いる事で、塩素よ
り低温で絶縁膜中に導入し、塩素の絶縁膜中への導入エ
リも効果的な耐放射線性の強化が可能である。また、絶
縁膜中へのフッ素の導入に際してはイオン注入技術全応
用する。これは、現状でtま、高純度のフッ素系ガスの
入手が困難なためであり、イオン注入時の質量分離によ
って、フッ素を含有する化学種のみ全半導体基板あるい
は絶縁膜中に導入することが可能となる。フッ素のイオ
ン注入に続いて、半導体基板にフッ素全注入した場合は
低温で酸化を行ない、絶縁膜中にフッ素全注入した場合
は、低温でアニールを行なう。この低温での酸化あるい
はアニールに工り、フッ素は絶縁膜/半導体基板界面に
蓄積される。
In the present invention, by using highly reactive fluorine, it is introduced into the insulating film at a lower temperature than chlorine, and the radiation resistance can be effectively strengthened even when chlorine is introduced into the insulating film. In addition, all ion implantation techniques will be applied when introducing fluorine into the insulating film. This is because it is currently difficult to obtain high-purity fluorine-based gases, and mass separation during ion implantation makes it possible to introduce only fluorine-containing chemical species into the entire semiconductor substrate or insulating film. It becomes possible. Following fluorine ion implantation, if all fluorine is implanted into the semiconductor substrate, oxidation is performed at low temperature, and if all fluorine is implanted into the insulating film, annealing is performed at low temperature. Due to this low temperature oxidation or annealing, fluorine is accumulated at the insulating film/semiconductor substrate interface.

(発明の効果) ここで、低温の酸化あるいはアニールは、絶縁膜/半導
体基板界面のストレス低減だけでなく、フッ素の雰囲気
中への避散防止の効果をも有する。
(Effects of the Invention) Here, low-temperature oxidation or annealing not only reduces stress at the insulating film/semiconductor substrate interface but also has the effect of preventing fluorine from escaping into the atmosphere.

(発明の作用) 以上の様に、絶縁膜/半導体基板上面に導入されたフッ
素は、固定電荷全減少させ、また、界面準位全低減させ
る作用を有する。
(Action of the Invention) As described above, fluorine introduced into the upper surface of the insulating film/semiconductor substrate has the effect of reducing the total fixed charge and the interface state.

(発明の効果) また、以上の様に、絶縁1反中にフッ素の導入された半
導体装置では、絶縁膜中の電子トラップ増加により、電
離放射線によって生じる固定正電荷の低減あるいは、電
子・正孔対の再結合が促進され、界面準位の増加も抑制
されるため、放射線環境下での特性劣化は改嵜され、長
期にわたる誦い信頼1生が41I11採される。
(Effects of the Invention) As described above, in a semiconductor device in which fluorine is introduced into an insulating film, an increase in electron traps in the insulating film reduces fixed positive charges caused by ionizing radiation, and Since pair recombination is promoted and the increase in interface states is suppressed, characteristic deterioration in a radiation environment is improved, and long-term reliability is achieved in 41I11.

(実施例〕 ここで、本発明の一実施例について図面を用いて説明音
訓える。以後の説明においては、便宜上、現在広く用い
られているP型シリコン及びシリコン酸化膜を例として
とりあげる。
(Embodiment) Here, an embodiment of the present invention will be explained with reference to the drawings.In the following explanation, for convenience, P-type silicon and silicon oxide films, which are currently widely used, will be taken as examples.

第1図に示した様に、P型シリコン基板101上に、シ
リコン酸化膜102及び、シリコン窒化j摸103を形
成し、所望の部分全除去して、素子分離用チャンネルス
トッパーとなるP 領域104を形成する。続いて、第
2図の様に、シリコン窒化膜全マスクとしてP 領域1
04の押込み酸化を行ない、素子分離用シリコン酸化膜
105・aを形成する。ここで、第3図の様に、基板全
面に四フッ化ケイ素をイオン注入106してフッ素の導
入された累子分雛用シリコン酸化膜105・b全形成す
る。この時、イオン注入エネルギーは素子分離用シリコ
ン酸化lN105・a1シリコン酸化膜102、シリコ
ン窒化膜103の膜厚全考慮し、不要のフッ素がシリコ
ン基板101に注入されない様、任意に設定する。さら
に、第4図に示した様にシリコン基板101の素子領域
上にあるシリコン窒化膜103、シリコン酸化膜104
を除去し、再びシリコン基板101全面に四フッ化ケイ
累全3×1015 crn 2程度イオン注入する。こ
の時のイオン注入エネルギーは、素子領域でのイオン注
入による損傷全低減するため20KeV程度以下に抑制
し、注入イオンは斜め入射させる事が望ましい。
As shown in FIG. 1, a silicon oxide film 102 and a silicon nitride film 103 are formed on a P-type silicon substrate 101, and a desired portion is completely removed to form a P region 104 that will serve as a channel stopper for device isolation. form. Next, as shown in FIG.
04 is performed to form a silicon oxide film 105.a for element isolation. Here, as shown in FIG. 3, silicon tetrafluoride is ion-implanted 106 over the entire surface of the substrate to form the entire silicon oxide film 105.b for the molecular droplets into which fluorine is introduced. At this time, the ion implantation energy is arbitrarily set so that unnecessary fluorine is not implanted into the silicon substrate 101, taking into account the entire film thickness of the silicon oxide lN105.a1 silicon oxide film 102 and silicon nitride film 103 for element isolation. Furthermore, as shown in FIG. 4, a silicon nitride film 103 and a silicon oxide film 104 on the element region of the silicon substrate 101 are
is removed, and silicon tetrafluoride ions are again implanted into the entire surface of the silicon substrate 101 at a total concentration of about 3×10 15 crn 2. It is desirable that the ion implantation energy at this time be suppressed to about 20 KeV or less to completely reduce damage caused by ion implantation in the element region, and that the implanted ions be obliquely incident.

なお素子領域のイオン注入による損傷全低減するには、
第2図のシリコン酸化膜102を除去せず、イオン注入
を行ない、後にシリコン酸化膜102を除去してもよい
。続いて第5図に示した様に乾燥酸素雰囲気中で酸化全
行ない、フッ素の導入されたゲートシリコン酸化膜10
8を形成する。この時、酸化温度If;1950 ’0
以下とし、シリコン酸化膜/シリコン基板界面のストレ
スを緩和する。
In order to completely reduce damage caused by ion implantation in the element region,
Instead of removing the silicon oxide film 102 in FIG. 2, ion implantation may be performed and the silicon oxide film 102 may be removed later. Subsequently, as shown in FIG. 5, oxidation is carried out in a dry oxygen atmosphere to form a gate silicon oxide film 10 into which fluorine has been introduced.
form 8. At this time, oxidation temperature If; 1950'0
The stress at the silicon oxide film/silicon substrate interface is alleviated by using the following conditions.

950℃以下という比較的低温の酸化で、シリコン酸化
膜の成長速度をあげるため、ガロ圧醒化を用いてもよい
。なお、この段階で、フッ素の導入された素子分離用シ
リコン酸化膜105・bはアニールされ、フッ素原子は
シリコン・酸素のネットワーク内に化学的結合をもって
組み込まれる。続いて、第6図に示した様に、ゲート電
極109及び絶縁シリコン酸化膜110全形成し、さら
に、ソースあるいはドレイン部111を設け、後に、第
7図の様にソースあるいはドレイン部111上に開口部
112を設け、配線113を施して、カバー絶縁膜11
4で被覆する。
Gallo pressure reduction may be used to increase the growth rate of the silicon oxide film by oxidation at a relatively low temperature of 950° C. or lower. At this stage, the element isolation silicon oxide film 105.b into which fluorine has been introduced is annealed, and the fluorine atoms are incorporated into the silicon-oxygen network with chemical bonds. Subsequently, as shown in FIG. 6, a gate electrode 109 and an insulating silicon oxide film 110 are completely formed, a source or drain part 111 is provided, and later, as shown in FIG. An opening 112 is provided, wiring 113 is provided, and the cover insulating film 11 is
Cover with 4.

以上の工程によって、シリコン酸化膜、主CCシリコン
酸化膜/シリコン基板界面にフッ素の導入された素子分
離用シリコン酸化膜105・b及びゲートシリコン酸化
膜108を有すること全特徴とするNチャネルMO8電
界効果型半導体装置が完成する。
Through the above steps, a silicon oxide film, an element isolation silicon oxide film 105/b with fluorine introduced into the main CC silicon oxide film/silicon substrate interface, and a gate silicon oxide film 108 are formed. An effective semiconductor device is completed.

(発明のまとめ) なお、本発明の実施例においては、シリコン基板にフッ
素をイオン注入した後ゲートシリコン酸化膜全形成する
場合につbて説明したが、ゲートシリコン酸化膜を形成
した後、フッ素をイオン注入し、アニールを行なう場合
でも同等の効果を有する。またNチャネルMUS電界効
果型半導体装置以外の場合、Pチャネル、あるいは相補
的MO8電界効果型半導体装置においても同等の効果を
有する。さらに、シリコン以外の半導体基板及びシリコ
ン酸化膜以外の絶縁膜、あるいは複数の絶縁膜の組合せ
による多層構造絶縁膜によるMI8電界効果型半導体装
置についても同様に有効である。
(Summary of the Invention) In the embodiment of the present invention, a case has been described in which the entire gate silicon oxide film is formed after ion implantation of fluorine into a silicon substrate. The same effect can be obtained even when ions are implanted and annealing is performed. Furthermore, in cases other than N-channel MUS field-effect semiconductor devices, similar effects can be obtained in P-channel or complementary MO8 field-effect semiconductor devices. Furthermore, the present invention is similarly effective for MI8 field effect semiconductor devices using semiconductor substrates other than silicon, insulating films other than silicon oxide films, or multilayer structure insulating films formed by combining a plurality of insulating films.

また、イオン注入する化学種においても、フッ素単体あ
るいは、四フフ化ケイ素以外のフッ素化合物を用いても
同等の効果を有する。
Further, as for the chemical species to be ion-implanted, the same effect can be obtained even if fluorine alone or a fluorine compound other than silicon tetrafluoride is used.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第7図は本発明の一実施例の断面構造図である
。 なお、図中において、101・・・・・・P型シリコン
基板、102・・・・シリコン酸化膜、103・・・・
・・シリコン窒化膜、104・・・・・・チャネルスト
ッパーP+領域、105・a・・・・・・菓子分離用シ
リコン酸化膜、105・b・・・・・フッ素の導入され
た素子分離用シリコン酸化膜、106・・・・・・四フ
ッ化ケイ素のイオン注入、107・・・・・四フッ化ケ
イ累のイオン注入、108・・・・・・フッ素の尋人さ
れたゲートシリコン酸化膜、109・・・・・絶縁シリ
コン酸化膜、110・・・・・・ケート電極、111・
・・・・・ソースあるいはドレイン部、112・・・・
・・開口部、113・・・・・・配線、114・・・・
・・カバー絶縁膜、である。 %1図 第2図 粥3図
1 to 7 are cross-sectional structural views of an embodiment of the present invention. In the figure, 101...P-type silicon substrate, 102...silicon oxide film, 103...
...Silicon nitride film, 104...Channel stopper P+ region, 105.a...Silicon oxide film for confectionery isolation, 105.b...For element isolation into which fluorine is introduced Silicon oxide film, 106...Ion implantation of silicon tetrafluoride, 107...Ion implantation of silicon tetrafluoride, 108...Fluorine gate silicon oxide Film, 109... Insulating silicon oxide film, 110... Kate electrode, 111.
...Source or drain section, 112...
...Opening, 113...Wiring, 114...
...Cover insulating film. %1 Figure 2 Figure 3 Porridge

Claims (5)

【特許請求の範囲】[Claims] (1)半導体基板上に形成された絶縁膜において、該絶
縁膜中にフッ素原子の導入された領域が設けられたこと
を特徴とする半導体装置。
(1) A semiconductor device characterized in that an insulating film formed on a semiconductor substrate is provided with a region into which fluorine atoms are introduced.
(2)半導体基板上に形成された絶縁膜において、該半
導体基板と該絶縁膜との界面にフッ素が蓄積されている
ことを特徴とする特許請求の範囲第(1)記載の半導体
装置。
(2) The semiconductor device according to claim 1, wherein, in an insulating film formed on a semiconductor substrate, fluorine is accumulated at an interface between the semiconductor substrate and the insulating film.
(3)イオン注入によりフッ素原子が半導体基板の表面
に導入された後、該半導体基板表面が酸化されることを
特徴とする特許請求の範囲第(1)項もしくは第(2)
項記載の半導体装置。
(3) Claims (1) or (2) characterized in that after fluorine atoms are introduced into the surface of the semiconductor substrate by ion implantation, the surface of the semiconductor substrate is oxidized.
1. Semiconductor device described in Section 1.
(4)イオン注入により、フッ素原子が半導体基板上に
形成された絶縁膜の少なくとも一部に導入された後アニ
ールされることを特徴とする特許請求の範囲第(1)項
もしくは第(2)項記載の半導体装置。
(4) Claims (1) or (2) characterized in that fluorine atoms are introduced into at least a portion of an insulating film formed on a semiconductor substrate by ion implantation and then annealed. 1. Semiconductor device described in Section 1.
(5)酸化もしくはアニールが低温で行なわれることを
特徴とする特許請求の範囲第(1)項もしくは第(2)
項記載の半導体装置。
(5) Claim (1) or (2) characterized in that the oxidation or annealing is performed at a low temperature.
1. Semiconductor device described in Section 1.
JP542685A 1985-01-16 1985-01-16 Semiconductor device with reinforced radiation resistance Pending JPS61164266A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP542685A JPS61164266A (en) 1985-01-16 1985-01-16 Semiconductor device with reinforced radiation resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP542685A JPS61164266A (en) 1985-01-16 1985-01-16 Semiconductor device with reinforced radiation resistance

Publications (1)

Publication Number Publication Date
JPS61164266A true JPS61164266A (en) 1986-07-24

Family

ID=11610842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP542685A Pending JPS61164266A (en) 1985-01-16 1985-01-16 Semiconductor device with reinforced radiation resistance

Country Status (1)

Country Link
JP (1) JPS61164266A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03296270A (en) * 1990-04-16 1991-12-26 Nec Corp Semiconductor device and manufacture thereof
US8114722B2 (en) 2007-08-24 2012-02-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US9034709B2 (en) 2012-03-08 2015-05-19 Asahi Kasei Microdevices Corporation Method for manufacturing semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS516475A (en) * 1974-06-06 1976-01-20 Rca Corp 2sankashirikonhimakunoshoriho
JPS5585068A (en) * 1978-12-21 1980-06-26 Sony Corp Preparation of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS516475A (en) * 1974-06-06 1976-01-20 Rca Corp 2sankashirikonhimakunoshoriho
JPS5585068A (en) * 1978-12-21 1980-06-26 Sony Corp Preparation of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03296270A (en) * 1990-04-16 1991-12-26 Nec Corp Semiconductor device and manufacture thereof
US8114722B2 (en) 2007-08-24 2012-02-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US9034709B2 (en) 2012-03-08 2015-05-19 Asahi Kasei Microdevices Corporation Method for manufacturing semiconductor device

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