JPH05217931A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05217931A JPH05217931A JP4017977A JP1797792A JPH05217931A JP H05217931 A JPH05217931 A JP H05217931A JP 4017977 A JP4017977 A JP 4017977A JP 1797792 A JP1797792 A JP 1797792A JP H05217931 A JPH05217931 A JP H05217931A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- implanted
- oxide film
- silicon oxide
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り, 特に絶縁膜の処理方法に関する。近年, メモリ素
子の微細化に伴い, キャパシタやゲートの絶縁膜高い電
界がかかるようになった。このとき, 絶縁膜に流れるト
ンネルリーク電流は素子寿命の低下や電荷保持時間の低
下等の悪影響を与える。このため,トンネルリーク電流
が少ない絶縁膜が要求される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to an insulating film processing method. In recent years, with the miniaturization of memory devices, high electric fields have been applied to the insulating films of capacitors and gates. At this time, the tunnel leak current flowing in the insulating film has an adverse effect such as a decrease in device life and a decrease in charge retention time. Therefore, an insulating film with a small tunnel leak current is required.
【0002】[0002]
【従来の技術】従来の半導体装置の製造方法素子におい
ては, 絶縁膜に酸化膜や窒化膜, あるいはそれらの多層
膜が用いられている。ところが素子が微細化されると絶
縁膜に加わる電界が高くなり, 絶縁膜に流れるトンネル
リーク電流が増加する。2. Description of the Related Art In a conventional semiconductor device manufacturing method element, an oxide film, a nitride film, or a multilayer film thereof is used as an insulating film. However, when the device is miniaturized, the electric field applied to the insulating film increases and the tunnel leakage current flowing in the insulating film increases.
【0003】[0003]
【発明が解決しようとする課題】従来例による素子に形
成されている絶縁膜では, 微細化に伴い絶縁膜に流れる
トンネルリーク電流が増加し, 素子の信頼性が低下する
という問題があった。The insulating film formed on the device according to the conventional example has a problem that the tunnel leakage current flowing through the insulating film increases with the miniaturization and the reliability of the device decreases.
【0004】本発明は高電界印加時に絶縁膜に流れるト
ンネルリーク電流を低減することを目的とする。An object of the present invention is to reduce tunnel leak current flowing in an insulating film when a high electric field is applied.
【0005】[0005]
【課題を解決するための手段】上記課題の解決は, 1)半導体基板(11)上に形成された酸化シリコン膜(12)
にフッ素イオン(F+ ) をドーズ量 1×1013cm-2以上注入
し, 該半導体基板を 900℃以下の温度で熱処理を行う半
導体装置の製造方法,あるいは 2)半導体基板(11)上に形成された酸化シリコン膜(12)
に酸素イオン(0+ ) をドーズ量 1×1012cm-2以上注入
し, 該半導体基板を 800℃以下の温度で熱処理を行う半
導体装置の製造方法,あるいは 3)半導体基板(11)に表面からフッ素イオン(F+ ) をド
ーズ量 1×1013cm-2以上注入し, 次いで該半導体基板表
面に熱酸化による酸化シリコン膜(14)を形成し,次いで
該半導体基板を 900℃以下の温度で熱処理を行う半導体
装置の製造方法,あるいは 4)半導体基板(11)に表面から酸素イオン(0+ ) をドー
ズ量 1×1012cm-2以上注入し, 次いで該半導体基板表面
に熱酸化による酸化シリコン膜(14)を形成し,次いで該
半導体基板を 800℃以下の温度で熱処理を行う半導体装
置の製造方法により達成される。[Means for Solving the Problems] 1) The silicon oxide film (12) formed on the semiconductor substrate (11) is solved.
Fluorine ion (F + ) is implanted into the substrate at a dose of 1 × 10 13 cm -2 or more, and the semiconductor substrate is heat-treated at a temperature of 900 ° C. or less, or 2) a semiconductor device is manufactured on the semiconductor substrate (11). Silicon oxide film formed (12)
Oxygen ion (0 + ) is implanted into the substrate at a dose of 1 × 10 12 cm -2 or more, and the semiconductor substrate is heat-treated at a temperature of 800 ° C or lower, or 3) a semiconductor substrate (11) has a surface. Fluorine ion (F + ) is implanted at a dose of 1 × 10 13 cm -2 or more, and then a silicon oxide film (14) is formed on the surface of the semiconductor substrate by thermal oxidation. 4) A method for manufacturing a semiconductor device in which heat treatment is performed at 4 or 4) Oxygen ions (0 + ) are implanted into the semiconductor substrate (11) from the surface by a dose of 1 × 10 12 cm -2 or more, and then the semiconductor substrate surface is thermally oxidized. This is achieved by a method of manufacturing a semiconductor device in which a silicon oxide film (14) is formed and then the semiconductor substrate is heat-treated at a temperature of 800 ° C. or lower.
【0006】[0006]
【作用】図1(A) 〜(C) は本発明の原理説明図(1) であ
る。図2(A) 〜(C) は本発明の原理説明図(2) である。(Function) FIGS. 1 (A) to 1 (C) are explanatory views (1) of the principle of the present invention. 2 (A) to 2 (C) are explanatory views (2) of the principle of the present invention.
【0007】図において,11はシリコン(Si)ウエハ, 12
は二酸化シリコン(SiO2)膜, 13は注入イオン, 14は注入
された元素が取り込まれたSiO2膜である。図1はSiウエ
ハに酸化膜を形成後イオン注入した場合, 図2はSiウエ
ハにイオン注入した後酸化膜を形成したものである。In the figure, 11 is a silicon (Si) wafer, 12
Is a silicon dioxide (SiO 2 ) film, 13 is an implanted ion, and 14 is an SiO 2 film in which the implanted element is incorporated. FIG. 1 shows a case where an oxide film is formed on a Si wafer and then ion implantation is performed. FIG. 2 shows a case where the oxide film is formed after ion implantation on the Si wafer.
【0008】いずれの酸化膜も,後記図3〜6から分か
るように取り込まれた元素がトンネルリーク電流を抑制
している。取り込まれた元素がトンネルリーク電流を抑
制する理由は以下のように考えられる。In any of the oxide films, the incorporated elements suppress the tunnel leak current, as will be seen from FIGS. The reason why the incorporated element suppresses the tunnel leak current is considered as follows.
【0009】注入された元素(F, O) は注入時には+1
価でSiO2中に注入されるが, SiO2のネットワークに取り
込まれたとき負に帯電する。これは, これらの元素の電
気陰性度が高いためである。SiO2膜の中程に負電荷の領
域ができると, AlよりSiに向け下がるように傾斜したSi
O2の伝導帯端を上方へ曲げるため, Alのフェルミ準位に
おけるAl/Si 間のSiO2膜によるバリア厚さがこれらの元
素を注入しないSiO2膜と比較して厚くなるため, 注入し
たSiO2膜を通過するトンネル電子数が減少し,リーク電
流が抑制されることになる。The implanted element (F, O) is +1 at the time of implantation.
It is injected into SiO 2 at a valency, but it becomes negatively charged when incorporated into the SiO 2 network. This is due to the high electronegativity of these elements. When a region of negative charge is formed in the middle of the SiO 2 film, Si tilted so that it goes down from Al toward Si.
Since the conduction band edge of O 2 is bent upward, the barrier thickness due to the SiO 2 film between Al / Si at the Fermi level of Al becomes thicker than that of the SiO 2 film not implanted with these elements. The number of tunnel electrons passing through the SiO 2 film is reduced and the leak current is suppressed.
【0010】[0010]
【実施例】図1に対応する実施例を説明する。まず,乾
燥雰囲気中で1000℃の熱処理により, p型シリコン(p-S
i)ウエハ11にSiO2膜12を形成し,SiO2膜12にフッ素イオ
ン(F+ ) または酸素イオン(O+ ) を注入した。EXAMPLE An example corresponding to FIG. 1 will be described. First, p-type silicon (pS
i) A SiO 2 film 12 was formed on the wafer 11, and fluorine ions (F + ) or oxygen ions (O + ) were implanted into the SiO 2 film 12.
【0011】注入条件の一例は次の通りである。入射角
7°,エネルギー 4 KeV, ドーズ量 1×1012, 1×1013
cm-2である。注入後のアニールは 700, 800, 900℃でそ
れぞれ10分間行って, AlゲートMOSを作製した。An example of injection conditions is as follows. Incident angle 7 °, energy 4 KeV, dose amount 1 × 10 12 , 1 × 10 13
cm -2 . The post-implantation annealing was performed at 700, 800, and 900 ℃ for 10 minutes to fabricate Al gate MOS.
【0012】次に, 図2に対応する実施例を説明する。
半導体基板表面に F+ をエネルギー 10 KeV 以下, ドー
ズ量 1×1013cm-2以上注入し, 次いで該半導体基板表面
に熱酸化(850〜900 ℃) によるSiO2膜を形成し,次いで
該半導体基板を 900℃以下の温度で熱処理を行う。Next, an embodiment corresponding to FIG. 2 will be described.
F + energy of 10 KeV or less and a dose of 1 × 10 13 cm -2 or more are implanted on the surface of a semiconductor substrate, and then a SiO 2 film is formed on the surface of the semiconductor substrate by thermal oxidation (850 to 900 ° C). The substrate is heat-treated at a temperature of 900 ° C or lower.
【0013】あるいは,半導体基板表面に 0+ をエネル
ギー 10 KeV 以下, ドーズ量1×1012cm-2以上注入し,
次いで該半導体基板表面に熱酸化(850〜900 ℃) による
酸化シリコン膜を形成し,次いで該半導体基板を 800℃
以下の温度で熱処理を行う。Alternatively, 0 + is injected into the surface of the semiconductor substrate at an energy of 10 KeV or less and a dose amount of 1 × 10 12 cm -2 or more,
Next, a silicon oxide film is formed on the surface of the semiconductor substrate by thermal oxidation (850 to 900 ° C), and then the semiconductor substrate is heated to 800 ° C.
Heat treatment is performed at the following temperature.
【0014】図3は F+ を 1×1012cm-2注入した試料の
Fowler-Nordheimプロットを示した図である。図は, 1
/E(cm/V)に対するJ/E2(A/V2) を示す。FIG. 3 shows a sample in which 1 × 10 12 cm −2 of F + was injected.
It is the figure which showed the Fowler-Nordheim plot. The figure is 1
J / E 2 (A / V 2 ) with respect to / E (cm / V) is shown.
【0015】ここで,Jは電流密度 (A/cm2), Eは電界
(V/cm) である。この場合, 注入していない no doseと
比較して, F+ を注入するとアニールなしおよび各アニ
ール温度に対するいずれの場合もトンネルリーク電流が
低下していることが分かる。Here, J is the current density (A / cm 2 ) and E is the electric field (V / cm). In this case, it can be seen that the tunnel leakage current is decreased when F + is injected, in both cases without annealing and for each annealing temperature, as compared with the case where no dose is injected.
【0016】図4は F+ を 1×1013cm-2注入した試料の
Fowler-Nordheimプロットを示した図である。この場合
も, 注入していない no doseと比較して, F+ を注入す
るとアニールなしおよび各アニール温度に対するいずれ
の場合もトンネルリーク電流が低下していることが分か
る。ドーズ量が 1×1012cm-2の場合と比較してリーク電
流低減の効果は大きい。FIG. 4 shows a sample in which F + is injected at 1 × 10 13 cm -2.
It is the figure which showed the Fowler-Nordheim plot. In this case as well, it can be seen that the tunnel leakage current decreases when F + is injected, in both cases of no annealing and for each annealing temperature, as compared with the case where no dose is injected. The effect of reducing the leakage current is greater than when the dose is 1 × 10 12 cm -2 .
【0017】図5は O+ を 1×1012cm-2注入した試料の
Fowler-Nordheimプロットを示した図である。この場
合, 注入していない no doseと比較して, 1×1012cm-2
ではトンネルリーク電流低減の効果はない。FIG. 5 shows a sample injected with 1 × 10 12 cm -2 of O + .
It is the figure which showed the Fowler-Nordheim plot. In this case, 1 × 10 12 cm -2 compared to no dose without injection
Does not have the effect of reducing the tunnel leak current.
【0018】図6は O+ を 1×1013cm-2注入した試料の
Fowler-Nordheimプロットを示した図である。この場
合, 注入していない no doseと比較して, 800℃アニー
ルではトンネルリーク電流は低減し, 900℃アニールで
は no doseより高くなる。FIG. 6 shows a sample in which 1 × 10 13 cm -2 of O + was injected.
It is the figure which showed the Fowler-Nordheim plot. In this case, the tunnel leakage current is lower in the 800 ° C anneal and higher than the no dose in the 900 ° C anneal, as compared to the no-dose implantation.
【0019】図7は F+ を 1×1012cm-2注入した試料の
F 濃度の深さ方向のプロファイルである。図8は F+ を
1×1013cm-2注入した試料のF 濃度の深さ方向のプロフ
ァイルである。FIG. 7 shows a sample in which 1 × 10 12 cm −2 of F + was injected.
It is a profile of F concentration in the depth direction. Figure 8 shows F +
This is a profile of F concentration in the depth direction of the injected sample at 1 × 10 13 cm -2 .
【0020】いずれのドーズ量の場合も1000℃以上でア
ニールするとフッ素は殆ど外方拡散してしまってフッ素
による効果は期待できないので, 900℃以下でアニール
することが必要である。In any of the dose amounts, if annealing is performed at 1000 ° C. or higher, fluorine almost diffuses outward, and the effect of fluorine cannot be expected. Therefore, it is necessary to anneal at 900 ° C. or lower.
【0021】図9は各元素を 1×1013cm-2注入した試料
のアニール温度に対するフラットバンド電圧Vfbを示し
た図である。no doseと比較して各元素による影響は少
なく, アニール温度に対するVfbシフト量は 0.2 V以内
に入っている。FIG. 9 is a diagram showing the flat band voltage V fb with respect to the annealing temperature of a sample in which 1 × 10 13 cm −2 of each element is implanted. The effect of each element is less than that of no dose, and the V fb shift amount with respect to the annealing temperature is within 0.2 V.
【0022】[0022]
【発明の効果】本発明はによれぱ, 微細化に伴う高電界
印加に対し, 絶縁膜に流れるトンネルリーク電流を低減
することができた。この結果, キャパシタの誘電体膜や
ゲート絶縁膜の信頼性が向上し,半導体装置の微細化に
寄与することができた。According to the present invention, the tunnel leak current flowing through the insulating film can be reduced when a high electric field is applied due to miniaturization. As a result, the reliability of the dielectric film and gate insulating film of the capacitor was improved, which contributed to the miniaturization of semiconductor devices.
【図1】 本発明の原理説明図(1)FIG. 1 is an explanatory diagram of the principle of the present invention (1)
【図2】 本発明の原理説明図(2)FIG. 2 is an explanatory view of the principle of the present invention (2)
【図3】 F+ を 1×1012cm-2注入した試料の Fowler-
Nordheimプロットを示した図[Fig. 3] Fowler- of a sample in which 1 × 10 12 cm -2 of F + was injected
Diagram showing the Nordheim plot
【図4】 F+ を 1×1013cm-2注入した試料の Fowler-
Nordheimプロットを示した図[Fig. 4] Fowler- of a sample in which 1 × 10 13 cm -2 of F + was injected
Diagram showing the Nordheim plot
【図5】 O+ を 1×1012cm-2注入した試料の Fowler-
Nordheimプロットを示した図FIG. 5: Fowler-of a sample in which O + is injected at 1 × 10 12 cm -2
Diagram showing the Nordheim plot
【図6】 O+ を 1×1013cm-2注入した試料の Fowler-
Nordheimプロットを示した図FIG. 6 Fowler-of a sample into which 1 × 10 13 cm -2 of O + was injected
Diagram showing the Nordheim plot
【図7】 F+ を 1×1012cm-2注入した試料のF 濃度の
深さ方向のプロファイルFIG. 7 Depth profile of F concentration of the sample in which F + is injected at 1 × 10 12 cm -2
【図8】 F+ を 1×1013cm-2注入した試料のF 濃度の
深さ方向のプロファイルFIG. 8: Profile of F concentration in the depth direction of the sample in which 1 × 10 13 cm -2 of F + was injected
【図9】 各元素を 1×1013cm-2注入した試料のアニー
ル温度に対するフラットバンド電圧Vfbを示した図FIG. 9 is a diagram showing a flat band voltage V fb with respect to an annealing temperature of a sample in which 1 × 10 13 cm −2 of each element is implanted.
11 半導体基板でSiウエハ 12 酸化シリコン膜 13 注入イオン 14 注入された元素が取り込まれた酸化シリコン膜 11 Si wafer on semiconductor substrate 12 Silicon oxide film 13 Implanted ions 14 Silicon oxide film with implanted elements
Claims (4)
コン膜(12)にフッ素イオン(F+ ) をドーズ量 1×1013cm
-2以上注入し, 該半導体基板を 900℃以下の温度で熱処
理を行うことを特徴とする半導体装置の製造方法。1. A dose of 1 × 10 13 cm of fluorine ions (F + ) is added to a silicon oxide film (12) formed on a semiconductor substrate (11).
A method for manufacturing a semiconductor device, which comprises injecting -2 or more and heat-treating the semiconductor substrate at a temperature of 900 ° C. or lower.
コン膜(12)に酸素イオン(0+ ) をドーズ量 1×1012cm-2
以上注入し, 該半導体基板を 800℃以下の温度で熱処理
を行うことを特徴とする半導体装置の製造方法。2. A dose amount of oxygen ions (0 + ) of 1 × 10 12 cm -2 to a silicon oxide film (12) formed on a semiconductor substrate (11).
A method for manufacturing a semiconductor device, comprising the steps of implanting the above and subjecting the semiconductor substrate to a heat treatment at a temperature of 800 ° C. or lower.
(F+ ) をドーズ量1×1013cm-2以上注入し, 次いで該半
導体基板表面に熱酸化による酸化シリコン膜(14)を形成
し,次いで該半導体基板を 900℃以下の温度で熱処理を
行うことを特徴とする半導体装置の製造方法。3. Fluorine ions from the surface of the semiconductor substrate (11)
(F + ) is implanted at a dose of 1 × 10 13 cm -2 or more, then a silicon oxide film (14) is formed on the surface of the semiconductor substrate by thermal oxidation, and then the semiconductor substrate is heat treated at a temperature of 900 ° C or less. A method for manufacturing a semiconductor device, comprising:
+ ) をドーズ量1×1012cm-2以上注入し, 次いで該半導
体基板表面に熱酸化による酸化シリコン膜(14)を形成
し,次いで該半導体基板を 800℃以下の温度で熱処理を
行うことを特徴とする半導体装置の製造方法。4. A semiconductor substrate (11) is provided with oxygen ions (0
+ ) Is implanted at a dose of 1 × 10 12 cm -2 or more, then a silicon oxide film (14) is formed on the surface of the semiconductor substrate by thermal oxidation, and then the semiconductor substrate is heat-treated at a temperature of 800 ° C or less. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01797792A JP3453764B2 (en) | 1992-02-04 | 1992-02-04 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01797792A JP3453764B2 (en) | 1992-02-04 | 1992-02-04 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05217931A true JPH05217931A (en) | 1993-08-27 |
JP3453764B2 JP3453764B2 (en) | 2003-10-06 |
Family
ID=11958787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP01797792A Expired - Lifetime JP3453764B2 (en) | 1992-02-04 | 1992-02-04 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3453764B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1052686A2 (en) * | 1999-05-14 | 2000-11-15 | Lucent Technologies Inc. | Oxidation of silicon using fluorine implants |
EP1052685A2 (en) * | 1999-05-14 | 2000-11-15 | Lucent Technologies Inc. | Integrated circuit device having a fluorine implanted oxide layer |
DE102004031453A1 (en) * | 2004-06-29 | 2006-02-09 | Infineon Technologies Ag | Method for producing a dielectric and semiconductor structure |
-
1992
- 1992-02-04 JP JP01797792A patent/JP3453764B2/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1052686A2 (en) * | 1999-05-14 | 2000-11-15 | Lucent Technologies Inc. | Oxidation of silicon using fluorine implants |
EP1052685A2 (en) * | 1999-05-14 | 2000-11-15 | Lucent Technologies Inc. | Integrated circuit device having a fluorine implanted oxide layer |
EP1052686A3 (en) * | 1999-05-14 | 2001-09-19 | Lucent Technologies Inc. | Oxidation of silicon using fluorine implants |
EP1052685A3 (en) * | 1999-05-14 | 2001-11-07 | Lucent Technologies Inc. | Integrated circuit device having a fluorine implanted oxide layer |
US6358865B2 (en) * | 1999-05-14 | 2002-03-19 | Agere Systems Guardian Corp. | Oxidation of silicon using fluorine implant |
DE102004031453A1 (en) * | 2004-06-29 | 2006-02-09 | Infineon Technologies Ag | Method for producing a dielectric and semiconductor structure |
DE102004031453B4 (en) * | 2004-06-29 | 2009-01-29 | Qimonda Ag | Method for producing a dielectric and semiconductor structure |
Also Published As
Publication number | Publication date |
---|---|
JP3453764B2 (en) | 2003-10-06 |
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