JPH0433375A - Mos transistor - Google Patents

Abstract

PURPOSE:To suppress generation of positive charge in a field oxide film due to an ionizing radioactive ray emission and to also suppress a variation in a threshold voltage by implanting fluorine ions in the film directly under a gate electrode, and simultaneously implanting fluorine ions in a silicon substrate directly under a gate oxide film. CONSTITUTION:A p-type well region 14 and an n-type well region 15 are formed on a silicon substrate 13, and a field oxide film 2 is formed. The surface of the substrate except the film 2 is covered with a silicon oxide film 19. Here, it is coated with a photoresist film 16, and patterned according to a fluorine implanted region 12. Then, fluorine ions 17 are implanted by an ion implanting method. Fluorine ions 5 are implanted in the thick film 2, and also implanted in a p-type well region 14 in the region of the thin film 19. The film 16 is removed, cleaned, and then fluorine ions are diffused. Further, after the thin film 19 is removed, a gate oxide film 7, a gate electrode 3, an insulating film 20, and an electrode 6 are respectively formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for improving reliability of a field oxide film in a semiconductor device.

[Conventional technology]

Conventionally, it has been known that external factors such as ionizing radiation irradiation cause characteristic deterioration in MOS transistors. IE Transactions on Nuclear Science, N.N. 36. (
1989) pages 2205 to 2211 (IEEE
Transactions on NuclearS
science, NS-36 (1989) pp, 2205
~2211), the conventional n
In a channel MOS transistor, ionizing radiation irradiation lowers the threshold voltage in the gate oxide film region and further isolates the MOS transistor region.
Field oxide with thick oxide and LOGO5
(Local Oxidation of 5ilic
(on) A threshold voltage fluctuation occurs in a birds' beak region, which is a transition region between an oxide film and a gate oxide film, and a leakage current occurs between the source and drain terminals.

Further, in the gate oxide film region, as the threshold voltage changes, interface states are generated at the gate oxide film/silicon substrate interface, reducing the driving ability of the MOS transistor.

Countermeasures have been taken to address the two problems mentioned above, namely, the generation of leakage current through a parasitic region such as a field oxide film, and the generation of interface states at the gate oxide film/silicon substrate interface.

As a method to deal with leakage current generation, Japanese Patent Application No. 60-1
03672. That is, the drain region is surrounded by the gate region on the surface of the semiconductor substrate,
By adopting a transistor structure having a source region on the outer periphery of a gate region, the influence of parasitic regions is prevented.

Also, as a method to prevent the generation of interface states, see the Journal of Applied Physics.

66, On 8 (1989) pp. 3909-3912
Page (Journal of Applied Phys.
ics, voQ 66, Na8(1,989)pp3
909-3912), a gate oxide film forming method using fluorine treatment is mentioned. In this method, after a gate oxide film is formed in a MOS transistor formation region, an electrode using polycrystalline silicon is formed, and after patterning, fluorine is introduced by ion implantation under low energy (25 KeV) conditions. After that, 95
High temperature annealing is performed at 0° C. to allow fluorine ions to reach the gate oxide film/silicon substrate interface. This generates 5i-F bonds and prevents the generation of interface states.

[Problem to be solved by the invention]

Although the above-mentioned conventional technology shows a method for solving individual problems that occur during ionizing radiation irradiation, in order to prevent an increase in leakage current through the parasitic region, it is necessary to change the layout pattern of the MO8h transistor. In addition, it is not possible to suppress the amount of positive charge that is required and accumulates in the field oxide film.

The present invention suppresses the generation of leakage current between the source and train terminals by suppressing hole traps in the field oxide film in the MOS transistor formation process using current field oxide film technology such as LOGO5 oxide film. At the same time, the purpose is to prevent the occurrence of interface state density between the gate oxide film and the silicon substrate.

[Means to solve the problem]

The above object can be achieved by introducing fluorine or chlorine ions into the field oxide film and fixing them. In particular, in a semiconductor device having a bird's peak region, the maximum impurity concentration of introduced fluorine or chlorine ions is set in a region deep from the center of the field oxide film thickness, and the silicon in the silicon oxide film is This can be achieved more effectively by alleviating stress near the substrate.

[Effect]

Introducing fluorine or chlorine ions into the silicon oxide film/silicon system suppresses the increase in interface state density that occurs after ionizing radiation irradiation or hot carrier injection. This is because the stress distribution existing at the silicon oxide film/silicon interface and its vicinity is relaxed by the introduction of fluorine or chlorine ions. In other words, bonds between stressed elements are easily broken by ionizing radiation, holes induced by radiation, hydrogen ions, etc.
Interface states such as pb centers are likely to occur. Therefore, fluorine or chlorine ions are introduced near the interface to relieve stress on the bonds between the elements, thereby preventing bonds from breaking due to external factors.

Similarly, by introducing fluorine or chlorine ions into the bird's peak region or field oxide film where stress is easily applied, stress on silicon-silicon bonds and silicon-oxygen bonds in the silicon oxide film can be alleviated. becomes possible.

This makes it possible to suppress the generation of hole traps due to ionizing radiation and hot carrier injection.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1 shows a cross-sectional structure of an n-type MOS transistor in the gate width direction. A field oxide film 2 or a gate oxide film 7 is formed on the surface of a p-type silicon substrate. Further, a patterned gate electrode 3 is formed on the gate oxide film 7 and field oxide film 2, and an insulating film 4 and wiring 6 are formed. Here, fluorine ions 5 were introduced into at least the field oxide film 2 immediately below the gate electrode. The region into which fluorine ions are introduced will be explained with reference to FIG. 2, and the method of introducing fluorine ions will be explained with reference to FIG. 3.

FIG. 2 shows a layout pattern of an inverter circuit using complementary MOS transistors. (I) is
Indicates a p-type MOS transistor region, (n) indicates an n-type M
The OS transistor area is shown. For field oxide film formation boundary 1o.

Gate electrode patterning region 9, p-type well formation region 1
1. A fluorine introduction region 12 is arranged.

The fluorine introduction region 12 is the gate electrode patterning region 9
It is formed so as to include at least an overlapping region of the P-type well forming region 11 and the P-type well forming region 11. This is because the threshold voltage fluctuation due to ionizing radiation irradiation depends on the direction of the electric field in the oxide film during radiation irradiation, and when the electric field is applied from the gate electrode toward the silicon substrate, the threshold voltage changes in a large negative direction. This causes a problem of inversion of the surface of the p-type silicon layer.

Therefore, fluorine was introduced into at least the region including the shaped region.

A method of introducing fluorine ions is shown in FIGS. 3(a) to 3(c). 3(a) to 3(C) show the cross-sectional structure of the element taken along straight line AA' in FIG. 2. FIG.

(a) A p-type well region 14 and an n-type well region 15 are formed on a silicon substrate 13, and a field oxide film 2 with a thickness of about 500 nm is formed using the LOCO5 formation method. The surface of the silicon substrate other than the field oxide film 2 is
It is covered with a silicon oxide film 19 of about 20 nm. Here, a photoresist film 16 was applied and patterned according to the fluorine introduced region 12 shown in FIG. Thereafter, fluorine ions 17 were introduced using an ion implantation technique. Here, the fluorine ion implantation energy is approximately 10
0keν, and the ion implantation amount was 1014~10”an
-2. As a result, the fluorine ions 5.

It is implanted into the thick field oxide film 2 and also into the p-type well region 14 in the region of the thin silicon oxide film 19. Fluorine ions 17 are located in the bird's beak region 18
The implantation energy was adjusted so that the maximum impurity concentration of fluorine ions in the oxide film was located in a deep region from the center of the film thickness in the field oxide film 2.

(b) After removing and cleaning the photoresist film 16, high temperature annealing at 900° C. 10' was performed in an N2 atmosphere to diffuse fluorine ions. Further, after removing the thin silicon oxide film 19, at a temperature of 850°C.

A new gate oxide film 7 was formed. Subsequently, after depositing a polycrystalline silicon layer and diffusing impurities, patterning was performed to form a gate electrode tri7A3.

(c) After performing ion implantation to form the source and drain regions of each of the p-type MOS transistor and the n-type MOS transistor, and performing high-temperature annealing in an inert gas, the insulating film 20 is formed and the electrode 6 is formed. went.

The heat treatment temperature after the introduction of fluorine ions must be 950° C. or lower in order to prevent diffusion of fluorine ions. Since the fluorine ion impurity profile in the field oxide film changes depending on the heat treatment conditions, the implantation amount of fluorine ions is 1014 to 1015a! ,−
The study was conducted within the scope of 2.

FIG. 4 shows the DC characteristics of the MOS transistor formed by the above method after being irradiated with X-rays. The amount of fluorine ion implanted is 320 Gy according to the characteristics of I O”an-2.
Even after X-ray irradiation, the leakage current at the input terminal was suppressed to less than 0.1nA, but due to the characteristics of the element without fluorine ion implantation, the leakage current was 1μ8° with the same irradiation dose. Occurrence was observed. Also, regarding parasitic MOS transistors using field oxide films, by introducing 10151-2 fluorine ions, the threshold voltage fluctuation after X-ray irradiation is reduced to about 50% compared to the case without introducing fluorine ions. Introducing fluorine ions into the field oxide film directly under the gate is also effective as a countermeasure against threshold voltage deterioration.

A second embodiment of the invention is shown in FIG. FIG. 5 is a cross-sectional structural diagram of an n-type transistor in the gate width direction. Silicon substrate 1. Silicon oxide film 23 and P-type silicon substrate 2
An n-type MOS transistor was formed on the substrate having the three-layer structure No. 4 by the method shown in FIG. In particular, after forming the field oxide film 2, fluorine ions were introduced into the silicon oxide film 23 using an ion implantation method using high energy of about 2 MeV. The amount of fluorine ions implanted at this time was 10ts, -z. Furthermore, before forming the gate oxide film 7, fluorine ions are implanted into at least the field oxide film 2 under the gate electrode with an implant energy of 100 KeV.
The fluorine ions were introduced into the p-type silicon substrate 24 and under the gate oxide film 7 formed after fluorine ion implantation.

In this example, since the silicon oxide film 23 is formed in the silicon substrate, the amount of charge generated in the silicon substrate is suppressed even under a high-energy heavy particle beam irradiation environment. Therefore, by applying this embodiment to a static random access memory, it is possible to prevent the data retention state from being reversed (soft error, single event upset) due to high-energy heavy particle beams. Furthermore, even in an ionizing radiation environment, silicon oxide film 2
It becomes possible to suppress inversion of impurity polarity or depletion near the interface of the silicon oxide film 23 of the p-type silicon substrate 24, which is caused by positive charges generated and fixed in the p-type silicon substrate 24. Therefore, in the complementary MOS transistor circuit using this embodiment, an increase in latch-up breakdown voltage can be achieved.

A third embodiment of the present invention will be described using FIG. 6. 6th
The figure shows a cross-sectional structure of an n-type MOS transistor in the gate width direction. In this embodiment, in the second embodiment of the present invention shown in FIG. 5, the p-type silicon substrate 24 has a three-layer structure (silicon substrate 1/silicon oxide film 23/p-type silicon substrate 24) using n-type MO8)
- Formed a transistor. Before forming the field oxide film 2, fluorine ions were implanted under high energy conditions of IKel/ to introduce fluorine ions into the silicon oxide film. At this time, the amount of fluorine ions implanted was 10
1sc++-2. The method for forming the n-type MOS transistor is based on the first embodiment shown in FIG. less than,
Indicate changes and important points. Field oxide film 2 is formed by etching and thermally oxidizing p-type silicon substrate 24, and is in contact with silicon oxide film 23.

In addition, before forming the gate oxide film 7, fluorine ions are again injected into the field oxide film 2 directly under the gate electrode 3 and into the p-type silicon substrate 24 under the gate oxide film 7 formed after the fluorine ion implantation with an energy of 100 KeV. It was also introduced.

In this embodiment, the fluorine ions introduced into the silicon oxide film 23 are effective in suppressing fluctuations in threshold voltage of a back channel transistor using the silicon oxide film 23 as a gate oxide film. That is, under an ionizing radiation environment, positive charges are accumulated not only in the field oxide film 2 and the gate oxide film 7 but also in the silicon oxide film 23. In particular, since the silicon oxide film 23 is thicker than the gate oxide film 7, it accumulates a large amount of positive charge, which tends to cause fluctuations in the threshold voltage. Therefore, leakage current occurs between the source and drain through the back channel transistor.

In a device in which fluorine ions are introduced into the silicon oxide film 23, fluctuations in threshold voltage can be suppressed, and generation of a nok current through the back channel transistor can be prevented.

As described above, in the second and third embodiments, fluorine is introduced into the silicon oxide film, and the fluorine ions are also fixed at the interface with the silicon substrate 24 through the diffusion process. The amount of interface states at the interface of the film 23 is suppressed, and an increase in generation/recombination current can be prevented.

In each of the embodiments of the present invention, fluorine ions were used to explain the embodiments, but chlorine ions, which are homologous elements, are also effective.

In addition, as a method of introducing fluorine ions, fluorine ions were directly introduced into the field oxide film by an ion implantation method, but after depositing a polycrystalline silicon layer for the gate electrode, higher implantation energy was used to introduce fluorine ions through the polycrystalline silicon layer. It is also possible to introduce fluorine into the field oxide film.

Furthermore, in the second and third embodiments, the silicon oxide film 2
Although a P-type silicon substrate 24 is formed on the substrate 3, it is also possible to realize this by introducing boron into a low concentration n-type silicon substrate to form a P-type well region.

〔Effect of the invention〕

As explained above, in the present invention, fluorine ions are introduced into the field oxide film directly below the gate electrode, and at the same time, fluorine ions are also introduced into the silicon substrate immediately below the gate oxide film. By introducing fluorine ions with a density of 101 Gan-' or higher into the field oxide film,
It is thought that stress within the field oxide film is alleviated. As a result, the generation of positive charges in the field oxide film due to ionizing radiation irradiation was suppressed, and the threshold voltage fluctuation was suppressed to about 50% compared to a device in which fluorine ions were not implanted. Furthermore, since fluorine ions are simultaneously implanted into the silicon substrate immediately below the gate oxide film, the heat treatment process after fluorine ion introduction causes the fluorine ions to diffuse into the gate oxide film/silicon interface, causing the threshold of the MOS transistor to rise. Effects have also been seen on voltage fluctuations. Note that the present invention is effective not only in reducing deterioration caused by ionizing radiation irradiation, but also in reducing various damages in the element manufacturing process.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram in the gate width direction of a MOS transistor showing a first embodiment of the present invention, and FIG. 2 is a schematic diagram of a layout pattern of an inverter circuit in the first embodiment.
Fig. 3 is a cross-sectional structural diagram taken along line AA' in Fig. 2, Fig. 4 shows the DC characteristics of the n-type MOS transistor of the first embodiment, and Fig. 5 shows the second embodiment of the present invention. FIG. 6 is a cross-sectional structural diagram of a MOS transistor in the gate width direction showing a third embodiment of the present invention. 1.13... Silicon substrate, 2... Field oxide film, 3... Gate electrode, 4... Insulating film, 5... Fluorine introduced into the oxide film, 6... Electrode, 7... Gate oxide film, 8... Fluorine introduced into silicon substrate, 9... Gate electrode pattern, 10... Field oxide film boundary pattern, 11... P-type well region pattern , 12...Fluorine ion implantation region pattern, 14
...p-type well region, 15...n-type well region, 1
6... Photoresist, 17... Fluorine ion implantation, 18... Bird's beak region, 19... Silicon oxide film, 20°21... Insulating film, 23... Silicon oxide film..., 24 ...p-type silicon substrate, 25...
Fluorine introduced through high-energy ion implantation.

Claims (1)

[Scope of Claims] 1. A MOS transistor characterized in that fluorine or chlorine is introduced into at least a field oxide film under a gate electrode. 2. A MOS transistor according to claim 1, characterized in that fluorine or chlorine is introduced into the silicon substrate under the gate oxide film. 3. The MOS transistor according to claim 1, wherein the maximum density of fluorine or chlorine exists at a deep position from the center of the thickness of the field oxide film.
OS transistor. 4. A MOS transistor using a silicon/silicon oxide film/silicon substrate structure, characterized in that fluorine or chlorine is introduced into the silicon oxide film.
transistor.