JPH02268441A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02268441A JPH02268441A JP8983389A JP8983389A JPH02268441A JP H02268441 A JPH02268441 A JP H02268441A JP 8983389 A JP8983389 A JP 8983389A JP 8983389 A JP8983389 A JP 8983389A JP H02268441 A JPH02268441 A JP H02268441A
- Authority
- JP
- Japan
- Prior art keywords
- film
- adhered
- transistor
- insulating film
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 239000000969 carrier Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 20
- 239000011229 interlayer Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体装置の製造方法、特に信頼性の高い半
導体素子の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a highly reliable semiconductor element.
(従来の技術)
近年、半導体素子の高集積化、微細化に伴い、L D
D (Lightly Doped Drain)構造
を有したトランジスタが広く使われている。電子バンド
ギャップエネルギーを越え、シリコン(Si)格子と衝
突して電子−正孔対を発生し、これがゲート酸化膜に捕
獲されてトランジスタ特性を劣化させる現象(ホットキ
ャリア現象)がある。ホットキャリアは高い電界によっ
て発生するので同じ電源電圧を保つと微細化されたトラ
ンジスタはど問題が大きいため、高い電界を緩和するた
め最も電界の高いドレイン近傍に濃度の低い不純物領域
を設けるLDD構造が必要となる。(Prior art) In recent years, with the increasing integration and miniaturization of semiconductor devices, L D
Transistors having a D (Lightly Doped Drain) structure are widely used. There is a phenomenon (hot carrier phenomenon) that exceeds the electronic band gap energy and collides with the silicon (Si) lattice to generate electron-hole pairs, which are captured by the gate oxide film and deteriorate transistor characteristics. Hot carriers are generated by a high electric field, so maintaining the same power supply voltage will cause problems in miniaturized transistors. Therefore, in order to alleviate the high electric field, an LDD structure is developed in which a low concentration impurity region is placed near the drain where the electric field is highest. It becomes necessary.
第2図は従来の半導体装置の製造工程を示すものである
。第2図において、1は半導体基板、2はゲート酸化膜
、3はゲート電極、4は不純物イオン(Po)、5は薄
い不純物拡散層(n−)、6はサイドウオール絶縁膜、
6′は酸化珪素膜、7は不純物イオン(As”)、8は
濃い不純物拡散層(n9)、9は眉間絶縁膜、10はア
ルミ配線である。FIG. 2 shows the manufacturing process of a conventional semiconductor device. In FIG. 2, 1 is a semiconductor substrate, 2 is a gate oxide film, 3 is a gate electrode, 4 is an impurity ion (Po), 5 is a thin impurity diffusion layer (n-), 6 is a sidewall insulating film,
6' is a silicon oxide film, 7 is an impurity ion (As''), 8 is a dense impurity diffusion layer (n9), 9 is an insulating film between the eyebrows, and 10 is an aluminum wiring.
次に従来の製造工程について説明する。第2図(a)に
おいて、半導体基板(p型)1上にゲート酸化膜2を被
着しゲートt443を形成する0次に例えばPlの不純
物イオン4をイオン注入法などを用いて注入し、薄い不
純物拡散層5を形成する。Next, the conventional manufacturing process will be explained. In FIG. 2(a), a gate oxide film 2 is deposited on a semiconductor substrate (p type) 1 and a gate t443 is formed. Next, impurity ions 4 of, for example, Pl are implanted using an ion implantation method. A thin impurity diffusion layer 5 is formed.
その後第2図(b)に示すように全面に酸化珪素膜6゛
を2500人程度被着させる0次に第2図(e)に示す
ように、異方性ドライエツチングにより全面エツチング
を行いサイドウオール絶縁膜6を形成する。次に第2図
(d)に示すように、例えばAs+イオンなどの不純物
イオン7をイオン注入法により注入し、窒素雰囲気中で
熱処理を行ない、濃い不純物拡散層8を形成する。次に
層間絶縁膜9を気相成長(c v D)法などにより被
着させ、レジストパターンを用いてコンタクト窓を開孔
し、アルミ配線10を形成し完成させる(第2図(e)
)。Thereafter, as shown in FIG. 2(b), a silicon oxide film of about 2,500 layers is deposited on the entire surface.Next, as shown in FIG. 2(e), the entire surface is etched by anisotropic dry etching to remove the side surfaces. A wall insulating film 6 is formed. Next, as shown in FIG. 2(d), impurity ions 7 such as As+ ions are implanted by an ion implantation method, and heat treatment is performed in a nitrogen atmosphere to form a dense impurity diffusion layer 8. Next, an interlayer insulating film 9 is deposited by a vapor phase epitaxy (CVD) method, a contact window is opened using a resist pattern, and an aluminum wiring 10 is formed and completed (FIG. 2(e)).
).
(発明が解決しようとする課M)
しかしながら、上記従来の製造方法では、ドレイン近傍
で発生したホットキャリアは、サイドウオールを形成し
ている絶縁膜中に捕獲され、デバイスを長時間使用のも
とでは閾値電圧変動などのトランジスタ特性を劣化させ
るというfnR性の問題がある。(Problem M to be solved by the invention) However, in the conventional manufacturing method described above, hot carriers generated near the drain are captured in the insulating film forming the sidewall, and the device cannot be used for a long time. However, there is a fnR problem in that transistor characteristics such as threshold voltage fluctuation are degraded.
本発明はこのような従来の問題を解決するものであり、
信頼性の高い半導体装置の製造方法を提供することを目
的とするものである。The present invention solves these conventional problems,
It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device.
(課題を解決するための手段)
本発明は上記目的を達成するために、半導体装置の製造
方法は、レジストパターンを用いてゲート電極を形成す
る際、エツチングを途中まで行う工程と、サイドウオー
ル絶縁膜を形成する際に、サイドウオール絶縁膜とその
下部の導電層を同時にエツチングを行い、サイドウオー
ル絶縁膜下部に導電層を含む構造のサイドウオールを形
成する工程とを備えているものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device that includes a step of performing etching halfway when forming a gate electrode using a resist pattern, and a step of performing sidewall insulation. When forming the film, the sidewall insulating film and the conductive layer below the sidewall insulating film are etched at the same time to form a sidewall having a structure including the conductive layer below the sidewall insulating film.
(作 用)
したがって、本発明の製造方法によって製造された半導
体装置は、サイドウオール絶縁膜にポットキャリアは捕
獲されず、またサイドウオール部の導電層はゲート電極
に接続されているため、その下の酸化珪素膜に捕獲され
たポットキャリアのトランジスタ特性に与える影響もな
くなる。(Function) Therefore, in the semiconductor device manufactured by the manufacturing method of the present invention, pot carriers are not captured in the sidewall insulating film, and since the conductive layer in the sidewall portion is connected to the gate electrode, the conductive layer is connected to the gate electrode. The effect of pot carriers trapped in the silicon oxide film on transistor characteristics is also eliminated.
(実施例)
第1図は本発明の一実施例における半導体製造工程を示
すものである。第1図において、1は半導体基板(p型
シリコン)、2はゲート酸化膜、3ハケート電極、4は
不純物イオン(Pl)、5は薄い不純物拡散層(n−)
、6はサイドウオール絶縁膜、7は不純物イオン(As
”)、8は濃い不純物拡散層(n゛)、9は層間絶縁膜
、10はアルミ配線である。(Embodiment) FIG. 1 shows a semiconductor manufacturing process in an embodiment of the present invention. In Figure 1, 1 is a semiconductor substrate (p-type silicon), 2 is a gate oxide film, 3 is a metal electrode, 4 is an impurity ion (Pl), and 5 is a thin impurity diffusion layer (n-).
, 6 is a sidewall insulating film, 7 is an impurity ion (As
''), 8 is a dense impurity diffusion layer (n''), 9 is an interlayer insulating film, and 10 is an aluminum wiring.
次に製造工程について説明する。第1図(a)において
、半導体基板(P型)1上にゲート酸化膜2を被着し、
さらに多結晶シリコン3を約4000人波着させ、ホト
レジストパターンにより、SF、ガスを用いたドライエ
ツチングを用いて多結晶シリコンが500人残6程度ま
でエツチングを行いゲート電極を形成する。さらに、P
+イオンなどの不純物イオン4を2.0XIO”>−”
程度イオン注入法により注入を行い、薄い不純物拡散層
5を形成する0次に第1図(b)に示すように、酸化珪
素膜6′約2500人被着させる。さらに、第1図(c
)に示すようにCHF3ガスなどを用いたドライエツチ
ングにより全面エツチングを行い、酸化珪素膜および酸
化珪素膜下部の導電膜のエツチングを行いサイドウオー
ル絶縁膜6を形成する1次に第1図(d)に示すように
、 As”イオンなどの不純物イオン7を5.OXlo
lfm−”程度イオン注入法により注入し、900℃で
30分窒素雰囲気中で熱処理を行い濃い不純物拡散層8
を形成する。次に第1図(a)に示すように、層間絶縁
膜9を被着し、レジストパターンによりコンタクト窓を
開孔しアルミ配線10を形成し完成させる。Next, the manufacturing process will be explained. In FIG. 1(a), a gate oxide film 2 is deposited on a semiconductor substrate (P type) 1,
Further, approximately 4,000 layers of polycrystalline silicon 3 are deposited, and a photoresist pattern is etched by dry etching using SF and gas until approximately 500 layers of polycrystalline silicon 6 remain, thereby forming a gate electrode. Furthermore, P
+ ions and other impurity ions 4 to 2.0XIO">-"
In order to form a thin impurity diffusion layer 5, approximately 2,500 silicon oxide films 6' are deposited as shown in FIG. 1(b). Furthermore, Figure 1 (c
) As shown in FIG. ), impurity ions such as As” ions are added to 5.OXlo
The dense impurity diffusion layer 8 is implanted by ion implantation method to the extent of lfm-'' and heat-treated at 900°C for 30 minutes in a nitrogen atmosphere.
form. Next, as shown in FIG. 1(a), an interlayer insulating film 9 is deposited, a contact window is opened using a resist pattern, and an aluminum wiring 10 is formed to complete the process.
なお、本実施例ではサイドウオール絶縁膜下部の導電層
を多結晶シリコンとしたが、シリサイド若しくは他の導
電膜を用いることもできる。In this embodiment, the conductive layer under the sidewall insulating film is made of polycrystalline silicon, but silicide or other conductive film may also be used.
(発明の効果)
本発明は上記実施例から明らかなように、サイドウオー
ル絶縁膜にホットキャリアは捕獲されないこと、またサ
イドウオール下の多結晶シリコン層はゲート電極に接続
されているため、その下の酸化珪素膜に捕獲されたホッ
トキャリアのトランジスタ特性を与える影響も少ない等
の効果を有する8例えば、ゲート電圧5V、ドレイン電
圧5vにおいて従来例では、トランジスタしきい値電圧
が数年から10年で約10%変動するのに対し、実施例
では、数%となり、長時間使用時のトランジスタ特性の
劣化が改善され信頼性の問題が解決できる。(Effects of the Invention) As is clear from the above embodiments, the present invention is characterized in that hot carriers are not captured in the sidewall insulating film, and that the polycrystalline silicon layer under the sidewall is connected to the gate electrode. 8 For example, in the conventional example, when the gate voltage is 5V and the drain voltage is 5V, the transistor threshold voltage will decrease within a few years to 10 years. While the variation is about 10%, in the example it is only a few percent, which improves the deterioration of transistor characteristics during long-term use and solves the reliability problem.
第1図は本発明の一実施例における半導体装置の製造方
法の工程図、第2図は従来の半導体装置の製造方法の工
程図である。
1 ・・・半導体基板、 2・・・ゲート酸化膜、3
・・・ゲート電極、 4 ・・・不純物イオン、5 ・
・・薄い不純物拡散層、 6 ・・・サイドウオール絶
縁膜、 7・・・不純物イオン。
8 ・・・濃い不純物拡散層、 9 ・・・層間絶縁膜
、10・・・アルミ配m。
第
図
第
図
第
図FIG. 1 is a process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process diagram of a conventional method for manufacturing a semiconductor device. 1... Semiconductor substrate, 2... Gate oxide film, 3
...gate electrode, 4 ...impurity ion, 5.
... Thin impurity diffusion layer, 6 ... Sidewall insulating film, 7 ... Impurity ion. 8...Dense impurity diffusion layer, 9...Interlayer insulating film, 10...Aluminum metal layer. Figure Figure Figure
Claims (1)
ート酸化膜上に導電膜を被着する工程と、前記導電膜を
ホトレジストをマスクとして途中までエッチングする工
程と、前記導電膜をマスクとして前記半導体基板上に不
純物イオンを注入する工程と、前記導電膜上に絶縁膜を
被着する工程と、前記ゲート酸化膜および前記絶縁膜を
エッチングして前記導電膜の側壁に沿って残す工程と、
前記導電膜および前記絶縁膜をマスクにして不純物イオ
ンを前記半導体基板上に注入する工程とを備えたことを
特徴とする半導体装置の製造方法。a step of depositing a gate oxide film on a semiconductor substrate; a step of depositing a conductive film on the gate oxide film; a step of etching the conductive film halfway using a photoresist as a mask; and a step of etching the conductive film halfway using the conductive film as a mask. a step of implanting impurity ions onto the semiconductor substrate; a step of depositing an insulating film on the conductive film; and a step of etching the gate oxide film and the insulating film to leave them along sidewalls of the conductive film. ,
A method for manufacturing a semiconductor device, comprising the step of implanting impurity ions onto the semiconductor substrate using the conductive film and the insulating film as masks.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8983389A JPH02268441A (en) | 1989-04-11 | 1989-04-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8983389A JPH02268441A (en) | 1989-04-11 | 1989-04-11 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02268441A true JPH02268441A (en) | 1990-11-02 |
Family
ID=13981765
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8983389A Pending JPH02268441A (en) | 1989-04-11 | 1989-04-11 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02268441A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5210435A (en) * | 1990-10-12 | 1993-05-11 | Motorola, Inc. | ITLDD transistor having a variable work function |
-
1989
- 1989-04-11 JP JP8983389A patent/JPH02268441A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5210435A (en) * | 1990-10-12 | 1993-05-11 | Motorola, Inc. | ITLDD transistor having a variable work function |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4182023A (en) | Process for minimum overlap silicon gate devices | |
US5372957A (en) | Multiple tilted angle ion implantation MOSFET method | |
US4078947A (en) | Method for forming a narrow channel length MOS field effect transistor | |
US7220650B2 (en) | Sidewall spacer for semiconductor device and fabrication method thereof | |
JPS62113474A (en) | Manufacture of semiconductor integrated circuit | |
JP4093855B2 (en) | Manufacturing method of semiconductor device | |
US6548363B1 (en) | Method to reduce the gate induced drain leakage current in CMOS devices | |
US5225357A (en) | Low P+ contact resistance formation by double implant | |
US3550256A (en) | Control of surface inversion of p- and n-type silicon using dense dielectrics | |
JPH02268441A (en) | Manufacture of semiconductor device | |
JPS63271971A (en) | Mos type semiconductor device and manufacture thereof | |
JP3453764B2 (en) | Method for manufacturing semiconductor device | |
JPH04715A (en) | Manufacture of semiconductor device | |
JP3156246B2 (en) | Field effect type semiconductor device and manufacturing method | |
KR0131992B1 (en) | Semiconductor device | |
JP2007048882A (en) | Semiconductor device and its manufacturing method | |
JPH02268442A (en) | Manufacture of semiconductor device | |
JP2968548B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH11176959A (en) | Manufacture of semiconductor device | |
JPH03188637A (en) | Manufacture of semiconductor device | |
JPH05291294A (en) | Manufacture of thin film transistor | |
JP2961388B2 (en) | Manufacturing method of nonvolatile semiconductor memory | |
JP3260485B2 (en) | Method for manufacturing semiconductor device | |
JPS6025272A (en) | Insulated gate field-effect type transistor | |
KR930009479B1 (en) | Manufacturing method of insulated gate type fet |