JPH023934A - Semiconductor device with reinforced resistance to radiation - Google Patents

Abstract

PURPOSE:To improve the radiation resistance of an LDD structure MOS transistor by constituting a side wall in a two-layers structure of an Si nitride film formed by CVD method and an Si oxide film formed by CVD method, said oxide film containing either one or both of B and P. CONSTITUTION:The following are provided; a P-type Si oxide film 10, a field oxide film 11 forming an element region, a channel stopper 12, a gate oxide film 8 formed in the element region and a gate electrode 3 wherein a side surface oxide film is formed on the whole surface. An N<-> type region 6 and an N<+> type region 7 formed in the self alignment manner are arranged, wherein the following are used as masks; a side wall of two-layers structure composed of a CVD Si nitride film 1 and a CVD Si oxide film 2a containing P, and the gate electrode 3. In this case, an Si oxide film wherein B or both of P and B are contained, instead of P, in one layer of the side wall material can be used. Thereby the radiation resistance of an MOS transistor can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having enhanced radiation resistance against hot carriers.

[Conventional technology]

In recent years, opportunities to use semiconductor integrated circuit devices in outer space or around nuclear reactors have been increasing.

When placed in such a harsh environment, semiconductor integrated circuit devices are susceptible to various types of radiation damage, causing malfunctions and destruction of the circuits, and tending to degrade the functionality of the system. Therefore, it is desired to develop a semiconductor integrated circuit device that is resistant to radiation.

However, on the one hand, the structure of MO3 type semiconductor devices is becoming finer, and on the other hand, the operating voltage of the transistor itself remains unchanged. The electric field strength in the region tends to continue to increase. Therefore, in a special case where the lateral electric field at the silicon substrate/gate oxide film interface is sufficiently large, the carriers accelerated here will ionize and collide with the crystal lattice of the substrate in the high electric field region near the drain, causing electron-
Generates hole pairs. Normally, when the temperature (electron temperature, hole temperature) of a charged particle system accelerated in a high electric field region exceeds the lattice temperature, this charge is specially called a pot carrier, but in this case, some of these hot carriers are The implantation crosses the substrate silicon/gate oxide barrier and is implanted into the gate oxide film. That is, an electron injection phenomenon occurs in an N-channel transistor, and a hole injection phenomenon occurs in a P-channel transistor. These injected carriers form interface states at the silicon/oxide film interface, or are captured by 1~laps in the oxide film, causing fixed charge accumulation, resulting in fluctuations in the threshold voltage of transistors, etc. in semiconductor devices. reduce reliability. Conventionally, in order to prevent such a decrease in reliability due to element miniaturization, MO8 type semiconductor devices have been manufactured using LDD (Lightly-
It has been attempted to create a doped-drain structure.

FIG. 5 shows a cross-sectional view of a conventional NMO transistor with an LDD structure, in which an 11-type region 6 with a low impurity concentration is formed in the channel region near the drain region 7, and the lateral electric field is concentrated here. It has been relaxed. Normally, this n- type region 6 is formed prior to forming each of the source and train [l+ type regions 7].
In order to prevent implantation into the - type region 6, an insulating layer 5 called a side wall is pre-caulked along the side oxide film 4 of the gate electrode 3 when forming the n+ type region 7. In this case, a silicon oxide film formed by conventional chemical vapor deposition (CVD) is usually used to form the side walls. Although this MO3 type semiconductor device with a 1-7DD structure has excellent hot carrier resistance, it is not sufficient in an environment where it is exposed to strong radiation such as a semiconductor device mounted on an artificial satellite, and the radiation resistance has been further strengthened. There is a need to do something.

[Problem to be solved by the invention]

That is, FIGS. 6(a) and (L)) show the conventional L D
This figure shows test data for the radiation resistance characteristics of a D-structure NMOS transistor, which examines changes in the voltage-current characteristics of the drain depending on the presence or absence of radiation irradiation. Here, Fig. 6(a) shows the case when no radiation is irradiated, and Fig. 6(b) shows the case when radiation (Co60 gamma rays) is irradiated at 105ra.
Data diagrams are shown for each case of d irradiation, and both are based on bias stress under conditions under which hot carriers would be generated under normal conditions (for example, voltage 1 to 5, drain voltage 5, stress time 3000 hours). ) has been investigated with and without addition. That is, the oxide film was formed to a thickness of 20°C in dry oxygen at a temperature of 950°C.
The drain voltage and current characteristics before and after radiation irradiation when using a sample with a gate length of 1.5 μm formed in a 0-layer structure are shown before stress application (solid line) and stress application f, respectively.
& (-) is indicated by (dashed line). As is clear from this test result, the LDD structure has high pot carrier resistance, and even before pot carrier stress is applied? As shown in Figure 6(a), there is almost no change in the characteristics of the transistor before irradiation with radiation, but what happens once radiation is irradiated? As shown in fJ6 diagram (b), the train current (broken line) after pot carrier stress application is significantly reduced compared to before application (solid line). The origin of this drain current variation can be considered to be (1) damage occurring in the gate oxide film and (2) damage occurring in the side/alls. However, even in the MOS transistor using a gate oxide film that is resistant to radiation, which was conducted as a supplementary experiment, the fluctuations are still large [Fig. 6 (b) -
(see dot-dashed line), it is thought that the damage occurring on the side wall in <2) greatly contributes to the original diagram of the characteristic variation. In this way, MO31 with the conventional LDD structure
~Ranjistor irradiates the pot, carrier,
When stress is applied, the train current decreases and the mutual conductance decreases.

The reason for this can be explained as follows. That is, a silicon oxide film formed by CVD is used as a conventional side wall material. When this oxide film is irradiated with ionizing radiation such as gamma rays and X-rays, it generates electron-hole pairs in the j-shape, as is well known. Therefore, if the gate electrode has a positive potential at this time, the generated holes move toward the substrate and form an interface level at the silicon/oxide film interface below the side wall. This interface state is a carrier
To act as a trap, hot carriers 1~
When a voltage is applied, electrons are captured and deplete the n-type region at the silicon/oxide film interface below the wall, increasing the resistance of this region and reducing the drain current. This results in a decrease in mutual contactance. By the way, when the oxide film is irradiated with radiation,
At the same time that interface states are generated in this way, holes are captured by hole traps within the oxide film, and fixed positive charges also accumulate. If the influence of fixed positive charges is a shadow of the interface state 4!
-C, the generation of hot carriers is further promoted.

This is due to the reason explained below.

That is, since the sidewall is positively charged when fixed positive charges are accumulated, the low-type region below the sidewall becomes an n-type region. As a result, the channel length is substantially reduced, and the lateral electric field of the channel is accordingly increased, promoting the generation of hot carriers. So far, we have described the effects of radiation on N-channel transistors, but similar effects appear on P-channel transistors as well.

As already mentioned, the generation of interface states causes depletion of the n-type region, and the accumulation of fixed positive charges causes the depletion of the n-type region.
This leads to + type formation, and changes the l helangister characteristics through these. Therefore, if we can control the amount of interface state generation and the amount of fixed positive charge accumulated, and cancel out the effects of the two, then n
- The mold region can be stably present. However, such control is not only impossible in fact, but the existence of the interface state itself reduces the mobility of electrons in the channel and impairs transistor characteristics. For the reasons described in 1-1 below, in order to increase the reliability of MO8 type semiconductor devices under radiation exposure environments, it is necessary to reduce both the amount of interface states generated and the amount of fixed positive charge accumulated, which are factors that change the I-transistor durability. It is necessary to reduce it. Therefore, the conventional L
When a MOS transistor with a D D structure is irradiated with radiation, (a) silicon/i below the side wall
An interface state is generated at the iu film interface, and (b) specific positive charges are accumulated inside the side wall. If the former effect is large, it causes a decrease in drain current and mutual conductance. In the case of devices where the generation of hot carriers is further promoted by the latter effect, unless effective countermeasures are taken to eliminate both the generation of interface states by side walls and the accumulation of fixed positive charges. , cannot operate normally under radiation exposure environment.

In view of the above-mentioned circumstances, an object of the present invention is to provide a semiconductor device having enhanced radiation resistance and having an LDD structure MOS transistor that can operate satisfactorily in a radiation environment.

[Means to solve the problem]

According to the present invention, a semiconductor device with enhanced radiation resistance characteristics includes an L
In an insulated gate field effect semiconductor device having a DD structure, the side wall comprises a 2X structure of a silicon nitride film formed by chemical vapor deposition and a silicon oxide film containing boron and/or phosphorus.
will be accomplished.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

The first [4] is an LDD structure NMOS showing an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a transistor. According to this embodiment, the semiconductor device of the present invention includes a P-type silicon substrate] 0, a field oxide film 11 forming an element region, a channel stopper 12, and a gate oxide film formed within the element region. film 8 and a gate electrode 3 provided with a side oxide film over the entire surface.
and C■ [) A side wall with a two-layer structure consisting of a silicon nitride film 1 and a CVD silicon oxide film 2a containing phosphorus, and a gate electrode 3 and two-layer side walls are formed in a self-aligned manner using masks, respectively. Formed rl-type region 6
and an LDD structure MOS transistor consisting of an n+ type region 7. As in this embodiment, when the side wall is made of a 2JIM structure using a CVD silicon nitride film 1- and a CVD silicon oxide film 2a containing phosphorus, the inside of the silicon oxide film 2a containing phosphorus formed using the CVD method is Since there are many recombination centers in the film, even if a large number of holes are generated in the film by radiation irradiation, they can be recombined and disappear with a high probability. As a result, the amount of interface states generated and the amount of fixed positive charges accumulated are significantly reduced. Furthermore, since there are many electron and hole traps at the interface between the CVD silicon nitride film 1 and this silicon oxide film 2a, holes in the silicon oxide film 2a generated by radiation irradiation are captured by these traps. Ru.

Therefore, the probability of reaching the silicon/oxide film interface below the side wall is greatly reduced, so the amount of interface states generated is significantly reduced.

Zunawaji, according to this embodiment, the side
The holes generated inside the wall recombine and disappear at the many recombination centers inside the side wall, resulting in the accumulation of fixed charges inside the side wall and at the silicon/oxide film interface below the side wall. In addition to reducing the amount of interface states generated, the probability that internally generated holes will also be captured by the many traps existing at the interface of the two insulating films and reach the silicon/oxide film interface below the side/alls will be significantly increased. The amount of interface states generated also decreases. Therefore, both the amount of interface states generated at the silicon/oxide film interface below the side wall and the amount of fixed positive charge accumulated inside the side wall can be reduced. That is, according to the present invention, both the amount of interface state generation and the amount of fixed positive charge accumulation are significantly reduced, and the drain current, mutual conductance, and fixed positive charge accumulation caused by the generation of interface states are reduced. Since undesirable phenomena such as the generation of hot carriers caused by radiation can be largely suppressed, the reliability of the LDD semiconductor device against radiation can be greatly improved.

FIG. 2 shows the test data of the radiation resistance characteristics of the above-mentioned example, which explains the present invention in detail, and shows the drain current-train voltage characteristics in the state of radiation irradiation under the same conditions as in FIG. 6(b), which has already explained This is what was measured. As is clear from this test data, there is almost no change in drain current between before stress application (solid line) and after stress application (dashed line), indicating that the radiation resistance characteristics have been significantly improved. be understood.

Next, how to make the semiconductor device of the present invention will be briefly explained.

FIGS. 3(a) to 3(c) are process order diagrams showing one of the manufacturing methods of the above embodiment. First, as shown in FIG. 3(a), P-type silicon is manufactured using a known technique. After forming a field oxide film 11 and a stopper region 12 on the substrate 10, and then forming a gate oxide film 8 on the P-type substrate 10 in the element region, a gate oxide film 8 made of polycrystalline silicon or a high melting point metal containing phosphorus or the like is formed. A gate electrode 3 is formed using a known etching technique, and a side oxide film is formed on its surface using a thermal oxidation method. Next, as shown in FIG. 3(b), after ion-implanting low-concentration n-type impurities such as arsenic or phosphorus in a self-aligned manner using the gate electrode [3 as a mask, a silicon nitride film 1' is deposited on the entire surface of the device. Deposition using the CVD method 9 Then, a silicon oxide film 2a' containing phosphorus is deposited over the entire surface of the device on this silicon nitride Ml' using the same CVD method. Next, as shown in FIG. 3(c), the silicon oxide film 2 is etched using an anisotropic chemical ion etching method.
After etching a' and leaving it only on the side surfaces of the gate electrode 3, the silicon nitride film 1 is exposed on the surface using hot phosphoric acid solution.
By etching away the gate electrode 3, a side wall having a two-layer structure of the CVD silicon nitride film 1 and the CVD silicon oxide film 2a containing phosphorus is formed.
High concentration arsenic or phosphorus ions are implanted in a self-aligned manner using the top and side walls as masks, and finally the ion implantation layer is activated by heating in a high temperature nitrogen atmosphere to form the n- type region 6 and the n+ By forming the region t47, a semiconductor device having the structure shown in FIG. 1 is obtained.

The above has explained the case where a CVD silicon oxide film containing phosphorus is used as one layer of the side wall material, but the effect can be obtained by using a silicon oxide film containing boron or both phosphorus and boron instead of phosphorus. are almost equivalent.

FIG. 4 shows an NMO with an LDD structure showing another embodiment of the present invention.
It is a cross-sectional view of an S transistor, and the side walls are formed using the same <CVD method as the silicon nitride film 1 formed by the CVD method.
A silicon oxide film containing boron and phosphorus (B
This figure shows a case in which a two-layer structure is formed consisting of PSG) 2b.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the side
The wall is made of silicon nitride film formed by CVD method and C
By forming a two-layer structure of silicon oxide film containing boron and/or phosphorus formed by the VD method, many holes generated inside the side wall under radiation irradiation can be generated inside the silicon oxide film. This reduces the amount of fixed pressure charges accumulated inside the side wall and the amount of interface states generated at the silicon/oxide film interface below the side wall. Holes that are generated within the silicon oxide film and move below the side wall are captured by a large number of traps mixed at the interface between the two insulating layers, the silicon nitride film and the oxide film, and an interface standard at the silicon/oxide film interface below the side wall is captured. Two actions can be performed simultaneously that significantly reduce the amount of power generated. Therefore, it is possible to effectively suppress the reduction in drain current and mutual conductance caused by the generation of interface states, as well as the generation of carriers in the hole 1 caused by the accumulation of fixed positive charges, which reduces the performance of LDD structure MOS transistors. It is possible to achieve a remarkable effect of greatly improving the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an LDD structure NMOS transistor showing an embodiment of the present invention, FIG.
) to (c) are process sequence diagrams showing one of the manufacturing methods of the above embodiment, FIG. 4 is a sectional view of an LDD structure NMO8) transistor showing another embodiment of the present invention, and FIG. 5 is a conventional LD of
Cross-sectional view of NMO3) transistor with D structure, Figure 6(a)
and (b) is a test data diagram of radiation resistance characteristics of a conventional NMOS transistor with an LDD structure. 1...CVD silicon nitride film, 2a...CVD silicon oxide film containing phosphorus, 2b...CVD silicon oxide film containing phosphorus and boron, 3...gate oxide film, 4...
- Side oxide film, 6... n- type region, 7... n+ type region 8... gate oxide film,... 10... P-type silicon substrate, 11... field oxide film, 12...Channel stopper vine 4- Flash drain electrician Drain electrician (O) Fl, 1n electrician (b) Fig. 6

Claims (1)

[Claims] LDD that forms side walls around the gate electrode
An insulated gate field effect semiconductor device having a radiation-resistant structure, characterized in that the side wall has a two-layer structure of a silicon nitride film formed by chemical vapor deposition and a silicon oxide film containing boron and/or phosphorous. A semiconductor device with enhanced characteristics.