JPS61161730A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS61161730A JPS61161730A JP60002732A JP273285A JPS61161730A JP S61161730 A JPS61161730 A JP S61161730A JP 60002732 A JP60002732 A JP 60002732A JP 273285 A JP273285 A JP 273285A JP S61161730 A JPS61161730 A JP S61161730A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- wire support
- wire
- support table
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関する。
従来、半導体装置を組立てる場合、第4図、第5図に示
すように、リード6を有するケース1のアイランド9の
略中央部にマウントされたペレット5のバットとケース
1上のステッチ2の間は、直接ワイヤ3で配線烙れてい
る。しかし、アイランド9の寸法に対し、ペレット5の
寸法が小さ過ぎるとワイヤ3が長くなるので、ワイヤ3
のたるみを生じ、不具合を生じやすくなる。
すように、リード6を有するケース1のアイランド9の
略中央部にマウントされたペレット5のバットとケース
1上のステッチ2の間は、直接ワイヤ3で配線烙れてい
る。しかし、アイランド9の寸法に対し、ペレット5の
寸法が小さ過ぎるとワイヤ3が長くなるので、ワイヤ3
のたるみを生じ、不具合を生じやすくなる。
このため、新たにペレット5の寸法に合ったアイランド
9を持つケース1を設計・製造しなければならないとい
う欠点がある。
9を持つケース1を設計・製造しなければならないとい
う欠点がある。
本発明の目的は、前述の欠点を除去し、ワイヤのたるみ
事故のない半導体装置を提供することにある。
事故のない半導体装置を提供することにある。
本発明の半導体装置の構成は、アイランドの略中央部に
固定されるペレットとステッチとの間部に、パッドを持
つワイヤ支持台を設けたことを特徴とする。
固定されるペレットとステッチとの間部に、パッドを持
つワイヤ支持台を設けたことを特徴とする。
次に本発明を図面を参照しながら詳細に説明する。
第1図は本発明の本実施例の半導体装置の正面図、第2
図は第1図のA−A’に沿って切断して見た断面図、第
3図は第1図のワイヤー支持台を示す正面図である。
図は第1図のA−A’に沿って切断して見た断面図、第
3図は第1図のワイヤー支持台を示す正面図である。
第1図において、まずケース1上のアイランド9の中央
部にマウントしようとするペレット5をマウントする前
に1第3図のような多数配列されたパット8をもつワイ
ヤ支持台4をマウントしよウトスるペレット5とステッ
チ2との中間部にマウントした後にペレット5をマウン
トする。
部にマウントしようとするペレット5をマウントする前
に1第3図のような多数配列されたパット8をもつワイ
ヤ支持台4をマウントしよウトスるペレット5とステッ
チ2との中間部にマウントした後にペレット5をマウン
トする。
次にボンダにより、ステッチ2→ワイヤ支持台4→ペレ
ット5の順序か、またはペレット5→ワイヤ支持台4→
ステ、チ2の順序で、ワイヤ2をボンディングする。ワ
イヤー支持台4及びペレット5のマウント材はAu−8
iを用いる。
ット5の順序か、またはペレット5→ワイヤ支持台4→
ステ、チ2の順序で、ワイヤ2をボンディングする。ワ
イヤー支持台4及びペレット5のマウント材はAu−8
iを用いる。
このワイヤ支持台4の材質と厚さは、ペレット5と同じ
にする。第3図のワイヤ支持台4の形状は、ケース本体
1のアイランド形状に合せて正方形がよい。
にする。第3図のワイヤ支持台4の形状は、ケース本体
1のアイランド形状に合せて正方形がよい。
以上の説明から明らかな様K、本発明によれば、従来の
方法に比べ、特に多品種少量生産時において、アイラン
ド寸法に合せた最少寸法以下のペレットでも、ワイヤ支
持台を取り付けることによって、ワイヤの間隔が短かく
なるため、ワイヤの強度を一定値以上に保たせることが
可能になり、ペレット寸法に合せたアイランド寸法をも
つケースを新たに設計・製造する必要がなくなる等の効
果が得られる。
方法に比べ、特に多品種少量生産時において、アイラン
ド寸法に合せた最少寸法以下のペレットでも、ワイヤ支
持台を取り付けることによって、ワイヤの間隔が短かく
なるため、ワイヤの強度を一定値以上に保たせることが
可能になり、ペレット寸法に合せたアイランド寸法をも
つケースを新たに設計・製造する必要がなくなる等の効
果が得られる。
第1図は本発明の実施例の半導体装置の正面図、第2図
は第1図のA−A’線に沿って切断して見た断面図、第
3図は第1図に使用するワイヤ支持台の正面図、第4図
は従来の半導体装置の正面図、第5図は第4図のB−B
/線に沿って切断して見た断面図である。同図において
、 1・・・・・・ケース本体、2・・・・・・ステッチ、
3・・・・・ワイヤ、4・・・・・・ワイヤ支持台、5
”°°°°ベレット・ 6・・・・・・リード、7,8
・・・・・・バット、9・・・・・・アイランド。
は第1図のA−A’線に沿って切断して見た断面図、第
3図は第1図に使用するワイヤ支持台の正面図、第4図
は従来の半導体装置の正面図、第5図は第4図のB−B
/線に沿って切断して見た断面図である。同図において
、 1・・・・・・ケース本体、2・・・・・・ステッチ、
3・・・・・ワイヤ、4・・・・・・ワイヤ支持台、5
”°°°°ベレット・ 6・・・・・・リード、7,8
・・・・・・バット、9・・・・・・アイランド。
Claims (1)
- アイランドの略中央部に固定されるペレットとステッ
チとの間部に、パッドを持つワイヤ支持台を設けたこと
を特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60002732A JPS61161730A (ja) | 1985-01-11 | 1985-01-11 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60002732A JPS61161730A (ja) | 1985-01-11 | 1985-01-11 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61161730A true JPS61161730A (ja) | 1986-07-22 |
Family
ID=11537491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60002732A Pending JPS61161730A (ja) | 1985-01-11 | 1985-01-11 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61161730A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03105935A (ja) * | 1989-09-19 | 1991-05-02 | Nec Kyushu Ltd | 半導体装置用セラミックパッケージ |
JPH04306849A (ja) * | 1991-04-03 | 1992-10-29 | Fuji Xerox Co Ltd | 半導体装置 |
-
1985
- 1985-01-11 JP JP60002732A patent/JPS61161730A/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03105935A (ja) * | 1989-09-19 | 1991-05-02 | Nec Kyushu Ltd | 半導体装置用セラミックパッケージ |
JPH04306849A (ja) * | 1991-04-03 | 1992-10-29 | Fuji Xerox Co Ltd | 半導体装置 |
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