JPS61159758A - Semiconductor module - Google Patents

Semiconductor module

Info

Publication number
JPS61159758A
JPS61159758A JP28102284A JP28102284A JPS61159758A JP S61159758 A JPS61159758 A JP S61159758A JP 28102284 A JP28102284 A JP 28102284A JP 28102284 A JP28102284 A JP 28102284A JP S61159758 A JPS61159758 A JP S61159758A
Authority
JP
Japan
Prior art keywords
lead bonding
outer lead
bonding pads
pads
centers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28102284A
Other languages
Japanese (ja)
Inventor
Kimiaki Hoizumi
保泉　公昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP28102284A priority Critical patent/JPS61159758A/en
Publication of JPS61159758A publication Critical patent/JPS61159758A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE:To shorten the intervals of arrangement of semiconductor chips by forming the planes of outer lead bonding pads in a specific polygon and zigzag disposing the outer lead bonding pads so that lines tying the centers of gravity of adjacent outer lead bonding pads each run parallel with the sides of the polygons. CONSTITUTION:The plane of an outer lead bonding pad is formed in a polygon, the end section of a bonding wire thereof is circumscribed to a shape that the end section is brought into contact, which is symmetrized to a perpendicular to a side nearest to a semiconductor chip and positioned onto the perpendicular and both the internal angles of opposite apices thereof take an acute angle. The outer lead bonding pads are zigzag arranged alternately so that lines tying the centers of gravity of adjacent outer lead bonding pads severally run parallel with the sides of the polygons-that is, the lines tying the centers of gravity respectively run approximately parallel with the oblique sides of hexagons forming the external shapes of the outer lead bonding pads 5. The value of a pitch P can be reduced while keeping a gap G at a fixed value by adjusting the values of the internal angles (alpha,beta) of the apices positioned onto the perpendiculars of the outer lead bonding pads 5.

Description

【発明の詳細な説明】 ［発明の技術分野］ 本発明は、回路基板上に半導体チップをダイボンドする
とともに複数のアウターリードボンディングパッドを配
設してなる半導体モジュールに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor module in which a semiconductor chip is die-bonded onto a circuit board and a plurality of outer lead bonding pads are provided.

［発明の技術的背景〕 近年、表面あるいは内部に回路パターンが形成された回
路基板上の所定の位置に半導体チップをダイボンドする
とともに、この半導体チップ上に設けられた複数のイン
ナーリードボンディングパッドと対向して回路基板上に
複数のアウターリードボンディングパッドをそれぞれ設
け、これらのボンディングバットをボンディングワイヤ
を用いてそれぞれ電気的に接続した構造の半導体モジュ
ールが広く用いられている。[Technical Background of the Invention] In recent years, a semiconductor chip is die-bonded to a predetermined position on a circuit board on which a circuit pattern is formed on the surface or inside, and a semiconductor chip is die-bonded to a predetermined position on a circuit board on which a circuit pattern is formed on the surface or inside. Semiconductor modules are widely used in which a plurality of outer lead bonding pads are provided on a circuit board, and these bonding pads are electrically connected to each other using bonding wires.

しかして従来は、第２図に示す・ように、回路基板１上
に半導体チップ２を環状に囲んで矩形のアウターリード
ボンディングパッド３が整列された構造の半導体モジュ
ールが用いられていた。Conventionally, as shown in FIG. 2, a semiconductor module having a structure in which rectangular outer lead bonding pads 3 are arranged on a circuit board 1 to surround a semiconductor chip 2 in an annular manner has been used.

なお、図中符号４はインナーリードボンディングパッド
を示し、また破線で囲んだ円形Ａはボンディングワイヤ
の端部が７ウターリードボンデイングバツド３に当接さ
れた形成された図形示す。In the figure, reference numeral 4 indicates an inner lead bonding pad, and a circle A surrounded by a broken line indicates a figure formed in which the end of the bonding wire is brought into contact with the outer lead bonding pad 3.

［背景技術の問題点１ しかしながらこの°ような半導体モジュールにおいては
、電気的な安全性を確保するため、隣接するアウターリ
ードボンディングパッド３間の最短距離（以下ギャップ
Ｇと示す。）を一定値以下にすることができなにいめ、
ゲートの高密度化およびそれに伴う多ビン化に対処する
ことができないという問題があった。[Background Art Problem 1] However, in such a semiconductor module, in order to ensure electrical safety, the shortest distance between adjacent outer lead bonding pads 3 (hereinafter referred to as gap G) is set to be less than a certain value. What can you do?
There was a problem in that it was not possible to cope with the increase in gate density and the accompanying increase in the number of bins.

［発明の目的］ 本発明はこの問題を解決するためになされたもので、ア
ウターリードボンディングパッドのギャップＧを一定の
値に保ちつつ、従来のものに比べて半導体チップの１辺
に平行にとったＸ方向の配列間隔（以下ピッチＰと示す
。）をはるかに小さくすることができ、ビン数の増加を
図ることができる半導体モジュールを提供することを目
的とする。[Object of the Invention] The present invention has been made to solve this problem, and while keeping the gap G of the outer lead bonding pad at a constant value, it is possible to maintain the gap G of the outer lead bonding pad parallel to one side of the semiconductor chip compared to the conventional one. An object of the present invention is to provide a semiconductor module in which the arrangement interval in the X direction (hereinafter referred to as pitch P) can be made much smaller, and the number of bins can be increased.

［発明の概要］ すなわち本発明の半導体モジュールは、回路基板上のに
所定の位置に、表面に複数のインナーリードボンディン
グパッドが配設された半導体チップをダイボンドすると
ともに、前記回路基板上の前記インナーリードボンディ
ングパッドと対向する位置に、該インナーリードボンデ
ィングパッドとボンディングワイヤにより接続するため
の複数のアウターリードボンディングパッドをそれぞれ
設けてなる半導体モジュールにおいて、アウターリード
ボンディングパッドの平面形状を、前記ボンディングワ
イヤの端部が接する形状に外接し、かつ前記半導体チッ
プの最も近い辺への垂線に対して対称でこの垂線上に位
置し対向する頂点の内角がいずれも鋭角である多角形と
し、しかもこれらのアウターリードボンディングパッド
を、隣接するアウターリードボンディングパッドの重心
を結ぶ線がそれぞれ前記多角形の辺に平行になるよ重心
を結ぶ線がアウターリードボンディングパッド５の外形
を形成する６角形の斜辺にそれぞれほぼ平行になるよう
に千鳥状に交互に配置されている。[Summary of the Invention] That is, the semiconductor module of the present invention includes die-bonding a semiconductor chip having a plurality of inner lead bonding pads on the surface thereof at a predetermined position on a circuit board, and bonding the semiconductor chip to a predetermined position on a circuit board. In a semiconductor module in which a plurality of outer lead bonding pads are respectively provided at positions facing the lead bonding pads for connection to the inner lead bonding pads by bonding wires, the planar shape of the outer lead bonding pads is set according to the planar shape of the bonding wires. A polygon that is circumscribed by the shape in which the ends touch, is symmetrical with respect to a perpendicular to the nearest side of the semiconductor chip, and is located on this perpendicular, and has internal angles of opposing vertices that are all acute angles, and these outer The lines connecting the centers of gravity of adjacent outer lead bonding pads are parallel to the sides of the polygon, and the lines connecting the centers of gravity of the lead bonding pads are approximately parallel to the oblique sides of the hexagon forming the outer shape of the outer lead bonding pad 5. They are arranged alternately in a staggered pattern so that they are parallel to each other.

このように構成された実施例におい・では、アウターリ
ードボンディングパッド５の垂線上に位置する頂点の内
角（α、β）の値を調整することによって、ギャップＧ
を一定値に保ちながらピッチＰの値を従来のものにたい
して２９〜９９％の値に減少させることができる。In the embodiment configured as described above, the gap G is adjusted by adjusting the values of the internal angles (α, β) of the vertices located on the perpendicular line of the outer lead bonding pad 5.
The value of the pitch P can be reduced to a value of 29 to 99% compared to the conventional one while keeping the value constant.

なお、以上の実施例においてはアウターリードボンディ
ングパッド５の平面形状を６角形状とした例について説
明したが、本発明はこのような実施例に限定されるもの
ではな（、線対称でボンディングワイヤの端部が接する
形状に外接しかつ対称となる垂線上のα頂角が鋭角とな
った多角形ならばいかなる平面形状のものでもアウター
リードボンディングパッド５とすることができる。In the above embodiment, an example in which the planar shape of the outer lead bonding pad 5 is hexagonal has been described, but the present invention is not limited to such an embodiment. The outer lead bonding pad 5 can be of any planar shape as long as it is a polygon whose apex angle α on a perpendicular line that is circumscribed and symmetrical with the shape in which the ends thereof are in contact with is an acute angle.

［発明の効果］ 以上の説明から明らかなように、本発明の半導体モジュ
ールにおいては、対向する頂角が鋭角でボンディングワ
イヤが接する形状に外接する線対称な多角形の平面形状
を有するアウターリードボンディングパッドの複数個が
、隣接するアウターリードボンディングパッドの重心を
結ぶ線がこれらの多角形の辺にそれぞれ平行になるよう
に千鳥状に配設されているので、従来のものに比べてア
ウターリードボンディングパッドのピッチＰを著しく小
さくすることができる。[Effects of the Invention] As is clear from the above description, in the semiconductor module of the present invention, the outer lead bonding has a polygonal planar shape that is axisymmetric and circumscribes the shape in which the bonding wires are in contact, and the opposing apex angles are acute angles. Since multiple pads are arranged in a staggered manner so that the lines connecting the centers of gravity of adjacent outer lead bonding pads are parallel to the sides of these polygons, outer lead bonding is easier than with conventional pads. The pitch P of the pads can be significantly reduced.

したがってこの半導体モジュールによればゲートの高密
度化および多ビン化の要求に対処することができる。Therefore, this semiconductor module can meet the demands for higher gate density and increased number of bins.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の半導体モジュールの一実施例の要部を
示す平面図、第２図は従来からの半導体モジュールの平
面図である。FIG. 1 is a plan view showing essential parts of an embodiment of a semiconductor module of the present invention, and FIG. 2 is a plan view of a conventional semiconductor module.

Claims (1)

【特許請求の範囲】[Claims] （１）回路基板上のに所定の位置に、表面に複数のイン
ナーリードボンディングパッドが配設された半導体チッ
プをダイボンドするとともに、前記回路基板上の前記イ
ンナーリードボンディングパッドと対向する位置に、該
インナーリードボンディングパッドとボンディングワイ
ヤにより接続するための複数のアウターリードボンディ
ングパッドをそれぞれ設けてなる半導体モジュールにお
いて、アウターリードボンディングパッドの平面形状を
、前記ボンディングワイヤの端部が接する形状に外接し
、かつ前記半導体チップの最も近い辺への垂線に対して
対称でこの垂線上に位置し対向する頂点の内角がいずれ
も鋭角である多角形とし、しかもこれらのアウターリー
ドボンディングパッドを、隣接するアウターリードボン
ディングパッドの重心を結ぶ線がそれぞれ前記多角形の
辺に平行になるように千鳥状に配置してなることを特徴
とする半導体モジュール。(1) A semiconductor chip having a plurality of inner lead bonding pads on its surface is die-bonded to a predetermined position on a circuit board, and a semiconductor chip having a plurality of inner lead bonding pads arranged on the surface thereof is die-bonded to a predetermined position on the circuit board, and In a semiconductor module including a plurality of outer lead bonding pads for connection to inner lead bonding pads by bonding wires, the planar shape of the outer lead bonding pads is circumscribed to a shape in contact with the ends of the bonding wires, and The polygon is symmetrical with respect to a perpendicular to the nearest side of the semiconductor chip, and the interior angles of opposing vertices located on this perpendicular line are all acute angles, and these outer lead bonding pads are connected to adjacent outer lead bonding pads. A semiconductor module characterized in that the pads are arranged in a staggered manner so that lines connecting the centers of gravity of the pads are parallel to the sides of the polygon.
JP28102284A 1984-12-29 1984-12-29 Semiconductor module Pending JPS61159758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28102284A JPS61159758A (en) 1984-12-29 1984-12-29 Semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28102284A JPS61159758A (en) 1984-12-29 1984-12-29 Semiconductor module

Publications (1)

Publication Number Publication Date
JPS61159758A true JPS61159758A (en) 1986-07-19

Family

ID=17633194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28102284A Pending JPS61159758A (en) 1984-12-29 1984-12-29 Semiconductor module

Country Status (1)

Country Link
JP (1) JPS61159758A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479190B1 (en) * 2001-07-16 2005-03-28 엔이씨 일렉트로닉스 가부시키가이샤 Semiconductor device and wire bonding method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479190B1 (en) * 2001-07-16 2005-03-28 엔이씨 일렉트로닉스 가부시키가이샤 Semiconductor device and wire bonding method therefor
US7514800B2 (en) 2001-07-16 2009-04-07 Nec Electronics Corporation Semiconductor device and wire bonding method therefor

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