JPS61152140A - デ−タ同期回路 - Google Patents

デ−タ同期回路

Info

Publication number
JPS61152140A
JPS61152140A JP59272942A JP27294284A JPS61152140A JP S61152140 A JPS61152140 A JP S61152140A JP 59272942 A JP59272942 A JP 59272942A JP 27294284 A JP27294284 A JP 27294284A JP S61152140 A JPS61152140 A JP S61152140A
Authority
JP
Japan
Prior art keywords
signal
edge
circuit
time
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59272942A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0588578B2 (enrdf_load_stackoverflow
Inventor
Takashi Takeuchi
崇 竹内
Hiroshi Endo
浩 遠藤
Kazumasa Oiso
大磯　一誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59272942A priority Critical patent/JPS61152140A/ja
Publication of JPS61152140A publication Critical patent/JPS61152140A/ja
Publication of JPH0588578B2 publication Critical patent/JPH0588578B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59272942A 1984-12-26 1984-12-26 デ−タ同期回路 Granted JPS61152140A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59272942A JPS61152140A (ja) 1984-12-26 1984-12-26 デ−タ同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59272942A JPS61152140A (ja) 1984-12-26 1984-12-26 デ−タ同期回路

Publications (2)

Publication Number Publication Date
JPS61152140A true JPS61152140A (ja) 1986-07-10
JPH0588578B2 JPH0588578B2 (enrdf_load_stackoverflow) 1993-12-22

Family

ID=17520913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59272942A Granted JPS61152140A (ja) 1984-12-26 1984-12-26 デ−タ同期回路

Country Status (1)

Country Link
JP (1) JPS61152140A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642436A (en) * 1987-06-25 1989-01-06 Oki Electric Ind Co Ltd Clock extracting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642436A (en) * 1987-06-25 1989-01-06 Oki Electric Ind Co Ltd Clock extracting circuit

Also Published As

Publication number Publication date
JPH0588578B2 (enrdf_load_stackoverflow) 1993-12-22

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees